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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
dt-bindings: mfd: syscon: Add missing simple syscon compatibles
Add various "simple" syscon compatibles which were undocumented or
still documented with old text bindings.
apm,xgene-csw, apm,xgene-efuse, apm,xgene-mcb, apm,xgene-rb,
fsl,ls1088a-reset, marvell,armada-3700-cpu-misc,
mediatek,mt2712-pctl-a-syscfg, mediatek,mt6397-pctl-pmic-syscfg, and
mediatek,mt8173-pctl-a-syscfg were all undocumented, but are in use
already. Remove the old text binding docs for the others.
Signed-off-by: Rob Herring <robh@kernel.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240402202413.757283-1-robh@kernel.org
Signed-off-by: Lee Jones <lee@kernel.org>
authored by
Rob Herring
and committed by
Lee Jones
7777dc1f
5549eeed
+15
-95
-12
Documentation/devicetree/bindings/arm/altera/socfpga-sdram-controller.txt
-12
Documentation/devicetree/bindings/arm/altera/socfpga-sdram-controller.txt
···
1
-
Altera SOCFPGA SDRAM Controller
2
-
3
-
Required properties:
4
-
- compatible : Should contain "altr,sdr-ctl" and "syscon".
5
-
syscon is required by the Altera SOCFPGA SDRAM EDAC.
6
-
- reg : Should contain 1 register range (address and length)
7
-
8
-
Example:
9
-
sdr: sdr@ffc25000 {
10
-
compatible = "altr,sdr-ctl", "syscon";
11
-
reg = <0xffc25000 0x1000>;
12
-
};
-17
Documentation/devicetree/bindings/arm/apm/scu.txt
-17
Documentation/devicetree/bindings/arm/apm/scu.txt
···
1
-
APM X-GENE SoC series SCU Registers
2
-
3
-
This system clock unit contain various register that control block resets,
4
-
clock enable/disables, clock divisors and other deepsleep registers.
5
-
6
-
Properties:
7
-
- compatible : should contain two values. First value must be:
8
-
- "apm,xgene-scu"
9
-
second value must be always "syscon".
10
-
11
-
- reg : offset and length of the register set.
12
-
13
-
Example :
14
-
scu: system-clk-controller@17000000 {
15
-
compatible = "apm,xgene-scu","syscon";
16
-
reg = <0x0 0x17000000 0x0 0x400>;
17
-
};
-32
Documentation/devicetree/bindings/arm/marvell/armada-37xx.txt
-32
Documentation/devicetree/bindings/arm/marvell/armada-37xx.txt
···
1
-
Power management
2
-
----------------
3
-
4
-
For power management (particularly DVFS and AVS), the North Bridge
5
-
Power Management component is needed:
6
-
7
-
Required properties:
8
-
- compatible : should contain "marvell,armada-3700-nb-pm", "syscon";
9
-
- reg : the register start and length for the North Bridge
10
-
Power Management
11
-
12
-
Example:
13
-
14
-
nb_pm: syscon@14000 {
15
-
compatible = "marvell,armada-3700-nb-pm", "syscon";
16
-
reg = <0x14000 0x60>;
17
-
}
18
-
19
-
AVS
20
-
---
21
-
22
-
For AVS an other component is needed:
23
-
24
-
Required properties:
25
-
- compatible : should contain "marvell,armada-3700-avs", "syscon";
26
-
- reg : the register start and length for the AVS
27
-
28
-
Example:
29
-
avs: avs@11500 {
30
-
compatible = "marvell,armada-3700-avs", "syscon";
31
-
reg = <0x11500 0x40>;
32
-
}
-16
Documentation/devicetree/bindings/mfd/brcm,iproc-cdru.txt
-16
Documentation/devicetree/bindings/mfd/brcm,iproc-cdru.txt
···
1
-
Broadcom iProc Chip Device Resource Unit (CDRU)
2
-
3
-
Various Broadcom iProc SoCs have a set of registers that provide various
4
-
chip specific device and resource configurations. This node allows access to
5
-
these CDRU registers via syscon.
6
-
7
-
Required properties:
8
-
- compatible: should contain:
9
-
"brcm,sr-cdru", "syscon" for Stingray
10
-
- reg: base address and range of the CDRU registers
11
-
12
-
Example:
13
-
cdru: syscon@6641d000 {
14
-
compatible = "brcm,sr-cdru", "syscon";
15
-
reg = <0 0x6641d000 0 0x400>;
16
-
};
-18
Documentation/devicetree/bindings/mfd/brcm,iproc-mhb.txt
-18
Documentation/devicetree/bindings/mfd/brcm,iproc-mhb.txt
···
1
-
Broadcom iProc Multi Host Bridge (MHB)
2
-
3
-
Certain Broadcom iProc SoCs have a multi host bridge (MHB) block that controls
4
-
the connection and configuration of 1) internal PCIe serdes; 2) PCIe endpoint
5
-
interface; 3) access to the Nitro (network processing) engine
6
-
7
-
This node allows access to these MHB registers via syscon.
8
-
9
-
Required properties:
10
-
- compatible: should contain:
11
-
"brcm,sr-mhb", "syscon" for Stingray
12
-
- reg: base address and range of the MHB registers
13
-
14
-
Example:
15
-
mhb: syscon@60401000 {
16
-
compatible = "brcm,sr-mhb", "syscon";
17
-
reg = <0 0x60401000 0 0x38c>;
18
-
};
+15
Documentation/devicetree/bindings/mfd/syscon.yaml
+15
Documentation/devicetree/bindings/mfd/syscon.yaml
···
38
38
- allwinner,sun8i-h3-system-controller
39
39
- allwinner,sun8i-v3s-system-controller
40
40
- allwinner,sun50i-a64-system-controller
41
+
- altr,sdr-ctl
41
42
- amd,pensando-elba-syscon
43
+
- apm,xgene-csw
44
+
- apm,xgene-efuse
45
+
- apm,xgene-mcb
46
+
- apm,xgene-rb
47
+
- apm,xgene-scu
42
48
- brcm,cru-clkset
49
+
- brcm,sr-cdru
50
+
- brcm,sr-mhb
43
51
- freecom,fsg-cs2-system-controller
44
52
- fsl,imx93-aonmix-ns-syscfg
45
53
- fsl,imx93-wakeupmix-syscfg
54
+
- fsl,ls1088a-reset
46
55
- hisilicon,dsa-subctrl
47
56
- hisilicon,hi6220-sramctrl
48
57
- hisilicon,pcie-sas-subctrl
···
60
51
- intel,lgm-syscon
61
52
- loongson,ls1b-syscon
62
53
- loongson,ls1c-syscon
54
+
- marvell,armada-3700-cpu-misc
55
+
- marvell,armada-3700-nb-pm
56
+
- marvell,armada-3700-avs
63
57
- marvell,armada-3700-usb2-host-misc
58
+
- mediatek,mt2712-pctl-a-syscfg
59
+
- mediatek,mt6397-pctl-pmic-syscfg
64
60
- mediatek,mt8135-pctl-a-syscfg
65
61
- mediatek,mt8135-pctl-b-syscfg
62
+
- mediatek,mt8173-pctl-a-syscfg
66
63
- mediatek,mt8365-syscfg
67
64
- microchip,lan966x-cpu-syscon
68
65
- microchip,sparx5-cpu-syscon