tjh.dev / kernel
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Merge branch 'net-stmmac-rk-final-cleanups-part'

Russell King says:

====================
net: stmmac: rk: final cleanups part

This is the last part of my current dwmac-rk cleanups.
====================

Link: https://patch.msgid.link/aYMN2gZMfLPKuukG@shell.armlinux.org.uk
Signed-off-by: Jakub Kicinski <kuba@kernel.org>

Jakub Kicinski 77dc4a72 7a4cd71f

+150 -211
+150 -211
drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
··· 27 27 struct rk_priv_data; 28 28 29 29 struct rk_clock_fields { 30 + /* io_clksel_cru_mask - io_clksel bit in clock GRF register which, 31 + * when set, selects the tx clock from CRU. 32 + */ 33 + u16 io_clksel_cru_mask; 34 + /* io_clksel_io_mask - io_clksel bit in clock GRF register which, 35 + * when set, selects the tx clock from IO. 36 + */ 37 + u16 io_clksel_io_mask; 30 38 u16 gmii_clk_sel_mask; 31 39 u16 rmii_clk_sel_mask; 40 + u16 rmii_gate_en_mask; 41 + u16 rmii_mode_mask; 32 42 u16 mac_speed_mask; 33 43 }; 34 44 ··· 49 39 void (*set_to_rmii)(struct rk_priv_data *bsp_priv); 50 40 int (*set_speed)(struct rk_priv_data *bsp_priv, 51 41 phy_interface_t interface, int speed); 52 - void (*set_clock_selection)(struct rk_priv_data *bsp_priv, bool input, 53 - bool enable); 54 42 void (*integrated_phy_powerup)(struct rk_priv_data *bsp_priv); 55 43 void (*integrated_phy_powerdown)(struct rk_priv_data *bsp_priv); 56 44 ··· 61 53 62 54 bool gmac_grf_reg_in_php; 63 55 bool clock_grf_reg_in_php; 56 + bool supports_rgmii; 57 + bool supports_rmii; 64 58 bool php_grf_required; 65 59 bool regs_valid; 66 60 u32 regs[]; ··· 96 86 bool clk_enabled; 97 87 bool clock_input; 98 88 bool integrated_phy; 89 + bool supports_rgmii; 90 + bool supports_rmii; 99 91 100 92 struct clk_bulk_data *clks; 101 93 int num_clks; ··· 177 165 regmap = bsp_priv->grf; 178 166 179 167 return regmap_write(regmap, bsp_priv->clock_grf_reg, val); 168 + } 169 + 170 + static int rk_set_rmii_gate_en(struct rk_priv_data *bsp_priv, bool state) 171 + { 172 + u32 val; 173 + 174 + if (!bsp_priv->clock.rmii_gate_en_mask) 175 + return 0; 176 + 177 + val = rk_encode_wm16(state, bsp_priv->clock.rmii_gate_en_mask); 178 + 179 + return rk_write_clock_grf_reg(bsp_priv, val); 180 + } 181 + 182 + static int rk_ungate_rmii_clock(struct rk_priv_data *bsp_priv) 183 + { 184 + return rk_set_rmii_gate_en(bsp_priv, false); 185 + } 186 + 187 + static int rk_gate_rmii_clock(struct rk_priv_data *bsp_priv) 188 + { 189 + return rk_set_rmii_gate_en(bsp_priv, true); 190 + } 191 + 192 + static int rk_configure_io_clksel(struct rk_priv_data *bsp_priv) 193 + { 194 + bool io, cru; 195 + u32 val; 196 + 197 + if (!bsp_priv->clock.io_clksel_io_mask && 198 + !bsp_priv->clock.io_clksel_cru_mask) 199 + return 0; 200 + 201 + io = bsp_priv->clock_input; 202 + cru = !io; 203 + 204 + /* The io_clksel configuration can be either: 205 + * 0=CRU, 1=IO (rk3506, rk3520, rk3576) or 206 + * 0=IO, 1=CRU (rk3588) 207 + * where CRU means the transmit clock comes from the CRU and IO 208 + * means the transmit clock comes from IO. 209 + * 210 + * Handle this by having two masks. 211 + */ 212 + val = rk_encode_wm16(io, bsp_priv->clock.io_clksel_io_mask) | 213 + rk_encode_wm16(cru, bsp_priv->clock.io_clksel_cru_mask); 214 + 215 + return rk_write_clock_grf_reg(bsp_priv, val); 180 216 } 181 217 182 218 static int rk_set_clk_mac_speed(struct rk_priv_data *bsp_priv, ··· 324 264 325 265 #define PX30_GRF_GMAC_CON1 0x0904 326 266 327 - static void px30_set_to_rmii(struct rk_priv_data *bsp_priv) 328 - { 329 - } 330 - 331 267 static const struct rk_gmac_ops px30_ops = { 332 - .set_to_rmii = px30_set_to_rmii, 333 268 .set_speed = rk_set_clk_mac_speed, 334 269 335 270 .gmac_grf_reg = PX30_GRF_GMAC_CON1, ··· 332 277 333 278 .clock_grf_reg = PX30_GRF_GMAC_CON1, 334 279 .clock.mac_speed_mask = BIT_U16(2), 280 + 281 + .supports_rmii = true, 335 282 }; 336 283 337 284 #define RK3128_GRF_MAC_CON0 0x0168 ··· 360 303 RK3128_GMAC_CLK_TX_DL_CFG(tx_delay)); 361 304 } 362 305 363 - static void rk3128_set_to_rmii(struct rk_priv_data *bsp_priv) 364 - { 365 - } 366 - 367 306 static const struct rk_gmac_ops rk3128_ops = { 368 307 .set_to_rgmii = rk3128_set_to_rgmii, 369 - .set_to_rmii = rk3128_set_to_rmii, 370 308 371 309 .gmac_grf_reg = RK3128_GRF_MAC_CON1, 372 310 .gmac_phy_intf_sel_mask = GENMASK_U16(8, 6), ··· 371 319 .clock.gmii_clk_sel_mask = GENMASK_U16(13, 12), 372 320 .clock.rmii_clk_sel_mask = BIT_U16(11), 373 321 .clock.mac_speed_mask = BIT_U16(10), 322 + 323 + .supports_rmii = true, 374 324 }; 375 325 376 326 #define RK3228_GRF_MAC_CON0 0x0900 ··· 460 406 RK3288_GMAC_CLK_TX_DL_CFG(tx_delay)); 461 407 } 462 408 463 - static void rk3288_set_to_rmii(struct rk_priv_data *bsp_priv) 464 - { 465 - } 466 - 467 409 static const struct rk_gmac_ops rk3288_ops = { 468 410 .set_to_rgmii = rk3288_set_to_rgmii, 469 - .set_to_rmii = rk3288_set_to_rmii, 470 411 471 412 .gmac_grf_reg = RK3288_GRF_SOC_CON1, 472 413 .gmac_phy_intf_sel_mask = GENMASK_U16(8, 6), ··· 471 422 .clock.gmii_clk_sel_mask = GENMASK_U16(13, 12), 472 423 .clock.rmii_clk_sel_mask = BIT_U16(11), 473 424 .clock.mac_speed_mask = BIT_U16(10), 425 + 426 + .supports_rmii = true, 474 427 }; 475 428 476 429 #define RK3308_GRF_MAC_CON0 0x04a0 ··· 481 430 #define RK3308_GMAC_FLOW_CTRL GRF_BIT(3) 482 431 #define RK3308_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3) 483 432 484 - static void rk3308_set_to_rmii(struct rk_priv_data *bsp_priv) 485 - { 486 - } 487 - 488 433 static const struct rk_gmac_ops rk3308_ops = { 489 - .set_to_rmii = rk3308_set_to_rmii, 490 - 491 434 .gmac_grf_reg = RK3308_GRF_MAC_CON0, 492 435 .gmac_phy_intf_sel_mask = GENMASK_U16(4, 2), 493 436 494 437 .clock_grf_reg = RK3308_GRF_MAC_CON0, 495 438 .clock.mac_speed_mask = BIT_U16(0), 439 + 440 + .supports_rmii = true, 496 441 }; 497 442 498 443 #define RK3328_GRF_MAC_CON0 0x0900 ··· 521 474 case 1: /* gmac2phy */ 522 475 bsp_priv->gmac_grf_reg = RK3328_GRF_MAC_CON2; 523 476 bsp_priv->clock_grf_reg = RK3328_GRF_MAC_CON2; 477 + bsp_priv->supports_rgmii = false; 524 478 return 0; 525 479 526 480 default: ··· 541 493 RK3328_GMAC_CLK_TX_DL_CFG(tx_delay)); 542 494 } 543 495 544 - static void rk3328_set_to_rmii(struct rk_priv_data *bsp_priv) 545 - { 546 - } 547 - 548 496 static void rk3328_integrated_phy_powerup(struct rk_priv_data *priv) 549 497 { 550 498 regmap_write(priv->grf, RK3328_GRF_MACPHY_CON1, ··· 552 508 static const struct rk_gmac_ops rk3328_ops = { 553 509 .init = rk3328_init, 554 510 .set_to_rgmii = rk3328_set_to_rgmii, 555 - .set_to_rmii = rk3328_set_to_rmii, 556 511 .integrated_phy_powerup = rk3328_integrated_phy_powerup, 557 512 .integrated_phy_powerdown = rk_gmac_integrated_ephy_powerdown, 558 513 ··· 560 517 561 518 .clock.rmii_clk_sel_mask = BIT_U16(7), 562 519 .clock.mac_speed_mask = BIT_U16(2), 520 + 521 + .supports_rmii = true, 563 522 564 523 .regs_valid = true, 565 524 .regs = { ··· 595 550 RK3366_GMAC_CLK_TX_DL_CFG(tx_delay)); 596 551 } 597 552 598 - static void rk3366_set_to_rmii(struct rk_priv_data *bsp_priv) 599 - { 600 - } 601 - 602 553 static const struct rk_gmac_ops rk3366_ops = { 603 554 .set_to_rgmii = rk3366_set_to_rgmii, 604 - .set_to_rmii = rk3366_set_to_rmii, 605 555 606 556 .gmac_grf_reg = RK3366_GRF_SOC_CON6, 607 557 .gmac_phy_intf_sel_mask = GENMASK_U16(11, 9), ··· 606 566 .clock.gmii_clk_sel_mask = GENMASK_U16(5, 4), 607 567 .clock.rmii_clk_sel_mask = BIT_U16(3), 608 568 .clock.mac_speed_mask = BIT_U16(7), 569 + 570 + .supports_rmii = true, 609 571 }; 610 572 611 573 #define RK3368_GRF_SOC_CON15 0x043c ··· 634 592 RK3368_GMAC_CLK_TX_DL_CFG(tx_delay)); 635 593 } 636 594 637 - static void rk3368_set_to_rmii(struct rk_priv_data *bsp_priv) 638 - { 639 - } 640 - 641 595 static const struct rk_gmac_ops rk3368_ops = { 642 596 .set_to_rgmii = rk3368_set_to_rgmii, 643 - .set_to_rmii = rk3368_set_to_rmii, 644 597 645 598 .gmac_grf_reg = RK3368_GRF_SOC_CON15, 646 599 .gmac_phy_intf_sel_mask = GENMASK_U16(11, 9), ··· 645 608 .clock.gmii_clk_sel_mask = GENMASK_U16(5, 4), 646 609 .clock.rmii_clk_sel_mask = BIT_U16(3), 647 610 .clock.mac_speed_mask = BIT_U16(7), 611 + 612 + .supports_rmii = true, 648 613 }; 649 614 650 615 #define RK3399_GRF_SOC_CON5 0xc214 ··· 673 634 RK3399_GMAC_CLK_TX_DL_CFG(tx_delay)); 674 635 } 675 636 676 - static void rk3399_set_to_rmii(struct rk_priv_data *bsp_priv) 677 - { 678 - } 679 - 680 637 static const struct rk_gmac_ops rk3399_ops = { 681 638 .set_to_rgmii = rk3399_set_to_rgmii, 682 - .set_to_rmii = rk3399_set_to_rmii, 683 639 684 640 .gmac_grf_reg = RK3399_GRF_SOC_CON5, 685 641 .gmac_phy_intf_sel_mask = GENMASK_U16(11, 9), ··· 684 650 .clock.gmii_clk_sel_mask = GENMASK_U16(5, 4), 685 651 .clock.rmii_clk_sel_mask = BIT_U16(3), 686 652 .clock.mac_speed_mask = BIT_U16(7), 653 + 654 + .supports_rmii = true, 687 655 }; 688 656 689 657 #define RK3506_GRF_SOC_CON8 0x0020 690 658 #define RK3506_GRF_SOC_CON11 0x002c 691 659 692 660 #define RK3506_GMAC_RMII_MODE GRF_BIT(1) 693 - 694 - #define RK3506_GMAC_CLK_SELECT_CRU GRF_CLR_BIT(5) 695 - #define RK3506_GMAC_CLK_SELECT_IO GRF_BIT(5) 696 - 697 - #define RK3506_GMAC_CLK_RMII_GATE GRF_BIT(2) 698 - #define RK3506_GMAC_CLK_RMII_NOGATE GRF_CLR_BIT(2) 699 661 700 662 static int rk3506_init(struct rk_priv_data *bsp_priv) 701 663 { ··· 709 679 } 710 680 } 711 681 712 - static void rk3506_set_to_rmii(struct rk_priv_data *bsp_priv) 713 - { 714 - unsigned int id = bsp_priv->id, offset; 715 - 716 - offset = (id == 1) ? RK3506_GRF_SOC_CON11 : RK3506_GRF_SOC_CON8; 717 - regmap_write(bsp_priv->grf, offset, RK3506_GMAC_RMII_MODE); 718 - } 719 - 720 - static void rk3506_set_clock_selection(struct rk_priv_data *bsp_priv, 721 - bool input, bool enable) 722 - { 723 - unsigned int value, offset, id = bsp_priv->id; 724 - 725 - offset = (id == 1) ? RK3506_GRF_SOC_CON11 : RK3506_GRF_SOC_CON8; 726 - 727 - value = input ? RK3506_GMAC_CLK_SELECT_IO : 728 - RK3506_GMAC_CLK_SELECT_CRU; 729 - value |= enable ? RK3506_GMAC_CLK_RMII_NOGATE : 730 - RK3506_GMAC_CLK_RMII_GATE; 731 - regmap_write(bsp_priv->grf, offset, value); 732 - } 733 - 734 682 static const struct rk_gmac_ops rk3506_ops = { 735 683 .init = rk3506_init, 736 - .set_to_rmii = rk3506_set_to_rmii, 737 - .set_clock_selection = rk3506_set_clock_selection, 738 684 685 + .clock.io_clksel_io_mask = BIT_U16(5), 739 686 .clock.rmii_clk_sel_mask = BIT_U16(3), 687 + .clock.rmii_gate_en_mask = BIT_U16(2), 688 + .clock.rmii_mode_mask = BIT_U16(1), 689 + 690 + .supports_rmii = true, 740 691 741 692 .regs_valid = true, 742 693 .regs = { ··· 741 730 #define RK3528_GMAC_CLK_RX_DL_CFG(val) GRF_FIELD(15, 8, val) 742 731 #define RK3528_GMAC_CLK_TX_DL_CFG(val) GRF_FIELD(7, 0, val) 743 732 744 - #define RK3528_GMAC0_PHY_INTF_SEL_RMII GRF_BIT(1) 745 - #define RK3528_GMAC1_PHY_INTF_SEL_RGMII GRF_CLR_BIT(8) 746 - #define RK3528_GMAC1_PHY_INTF_SEL_RMII GRF_BIT(8) 747 - 748 - #define RK3528_GMAC1_CLK_SELECT_CRU GRF_CLR_BIT(12) 749 - #define RK3528_GMAC1_CLK_SELECT_IO GRF_BIT(12) 750 - 751 - #define RK3528_GMAC0_CLK_RMII_GATE GRF_BIT(2) 752 - #define RK3528_GMAC0_CLK_RMII_NOGATE GRF_CLR_BIT(2) 753 - #define RK3528_GMAC1_CLK_RMII_GATE GRF_BIT(9) 754 - #define RK3528_GMAC1_CLK_RMII_NOGATE GRF_CLR_BIT(9) 755 - 756 733 static int rk3528_init(struct rk_priv_data *bsp_priv) 757 734 { 758 735 switch (bsp_priv->id) { 759 736 case 0: 760 737 bsp_priv->clock_grf_reg = RK3528_VO_GRF_GMAC_CON; 761 738 bsp_priv->clock.rmii_clk_sel_mask = BIT_U16(3); 739 + bsp_priv->clock.rmii_gate_en_mask = BIT_U16(2); 740 + bsp_priv->clock.rmii_mode_mask = BIT_U16(1); 741 + bsp_priv->supports_rgmii = false; 762 742 return 0; 763 743 764 744 case 1: 765 745 bsp_priv->clock_grf_reg = RK3528_VPU_GRF_GMAC_CON5; 746 + bsp_priv->clock.io_clksel_io_mask = BIT_U16(12); 766 747 bsp_priv->clock.gmii_clk_sel_mask = GENMASK_U16(11, 10); 767 748 bsp_priv->clock.rmii_clk_sel_mask = BIT_U16(10); 749 + bsp_priv->clock.rmii_gate_en_mask = BIT_U16(9); 750 + bsp_priv->clock.rmii_mode_mask = BIT_U16(8); 768 751 return 0; 769 752 770 753 default: ··· 770 765 int tx_delay, int rx_delay) 771 766 { 772 767 regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5, 773 - RK3528_GMAC1_PHY_INTF_SEL_RGMII); 774 - 775 - regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5, 776 768 DELAY_ENABLE(RK3528, tx_delay, rx_delay)); 777 769 778 770 regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON6, 779 771 RK3528_GMAC_CLK_RX_DL_CFG(rx_delay) | 780 772 RK3528_GMAC_CLK_TX_DL_CFG(tx_delay)); 781 - } 782 - 783 - static void rk3528_set_to_rmii(struct rk_priv_data *bsp_priv) 784 - { 785 - if (bsp_priv->id == 1) 786 - regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5, 787 - RK3528_GMAC1_PHY_INTF_SEL_RMII); 788 - else 789 - regmap_write(bsp_priv->grf, RK3528_VO_GRF_GMAC_CON, 790 - RK3528_GMAC0_PHY_INTF_SEL_RMII); 791 - } 792 - 793 - static void rk3528_set_clock_selection(struct rk_priv_data *bsp_priv, 794 - bool input, bool enable) 795 - { 796 - unsigned int val; 797 - 798 - if (bsp_priv->id == 1) { 799 - val = input ? RK3528_GMAC1_CLK_SELECT_IO : 800 - RK3528_GMAC1_CLK_SELECT_CRU; 801 - val |= enable ? RK3528_GMAC1_CLK_RMII_NOGATE : 802 - RK3528_GMAC1_CLK_RMII_GATE; 803 - regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5, val); 804 - } else { 805 - val = enable ? RK3528_GMAC0_CLK_RMII_NOGATE : 806 - RK3528_GMAC0_CLK_RMII_GATE; 807 - regmap_write(bsp_priv->grf, RK3528_VO_GRF_GMAC_CON, val); 808 - } 809 773 } 810 774 811 775 static void rk3528_integrated_phy_powerup(struct rk_priv_data *bsp_priv) ··· 790 816 static const struct rk_gmac_ops rk3528_ops = { 791 817 .init = rk3528_init, 792 818 .set_to_rgmii = rk3528_set_to_rgmii, 793 - .set_to_rmii = rk3528_set_to_rmii, 794 - .set_clock_selection = rk3528_set_clock_selection, 795 819 .integrated_phy_powerup = rk3528_integrated_phy_powerup, 796 820 .integrated_phy_powerdown = rk3528_integrated_phy_powerdown, 821 + 822 + .supports_rmii = true, 823 + 797 824 .regs_valid = true, 798 825 .regs = { 799 826 0xffbd0000, /* gmac0 */ ··· 855 880 RK3568_GMAC_TXCLK_DLY_ENABLE); 856 881 } 857 882 858 - static void rk3568_set_to_rmii(struct rk_priv_data *bsp_priv) 859 - { 860 - } 861 - 862 883 static const struct rk_gmac_ops rk3568_ops = { 863 884 .init = rk3568_init, 864 885 .set_to_rgmii = rk3568_set_to_rgmii, 865 - .set_to_rmii = rk3568_set_to_rmii, 866 886 .set_speed = rk_set_clk_mac_speed, 867 887 868 888 .gmac_phy_intf_sel_mask = GENMASK_U16(6, 4), 889 + 890 + .supports_rmii = true, 869 891 870 892 .regs_valid = true, 871 893 .regs = { ··· 889 917 /* SDGMAC_GRF */ 890 918 #define RK3576_GRF_GMAC_CON0 0X0020 891 919 #define RK3576_GRF_GMAC_CON1 0X0024 892 - 893 - #define RK3576_GMAC_CLK_SELECT_IO GRF_BIT(7) 894 - #define RK3576_GMAC_CLK_SELECT_CRU GRF_CLR_BIT(7) 895 - 896 - #define RK3576_GMAC_CLK_RMII_GATE GRF_BIT(4) 897 - #define RK3576_GMAC_CLK_RMII_NOGATE GRF_CLR_BIT(4) 898 920 899 921 static int rk3576_init(struct rk_priv_data *bsp_priv) 900 922 { ··· 931 965 RK3576_GMAC_CLK_RX_DL_CFG(rx_delay)); 932 966 } 933 967 934 - static void rk3576_set_to_rmii(struct rk_priv_data *bsp_priv) 935 - { 936 - } 937 - 938 - static void rk3576_set_clock_selection(struct rk_priv_data *bsp_priv, bool input, 939 - bool enable) 940 - { 941 - unsigned int val = input ? RK3576_GMAC_CLK_SELECT_IO : 942 - RK3576_GMAC_CLK_SELECT_CRU; 943 - unsigned int offset_con; 944 - 945 - val |= enable ? RK3576_GMAC_CLK_RMII_NOGATE : 946 - RK3576_GMAC_CLK_RMII_GATE; 947 - 948 - offset_con = bsp_priv->id == 1 ? RK3576_GRF_GMAC_CON1 : 949 - RK3576_GRF_GMAC_CON0; 950 - 951 - regmap_write(bsp_priv->grf, offset_con, val); 952 - } 953 - 954 968 static const struct rk_gmac_ops rk3576_ops = { 955 969 .init = rk3576_init, 956 970 .set_to_rgmii = rk3576_set_to_rgmii, 957 - .set_to_rmii = rk3576_set_to_rmii, 958 - .set_clock_selection = rk3576_set_clock_selection, 959 971 960 972 .gmac_rmii_mode_mask = BIT_U16(3), 961 973 974 + .clock.io_clksel_io_mask = BIT_U16(7), 962 975 .clock.gmii_clk_sel_mask = GENMASK_U16(6, 5), 963 976 .clock.rmii_clk_sel_mask = BIT_U16(5), 977 + .clock.rmii_gate_en_mask = BIT_U16(4), 978 + 979 + .supports_rmii = true, 964 980 965 981 .php_grf_required = true, 966 982 .regs_valid = true, ··· 970 1022 #define RK3588_GRF_GMAC_CON0 0X0008 971 1023 #define RK3588_GRF_CLK_CON1 0X0070 972 1024 973 - #define RK3588_GMAC_CLK_RMII_MODE(id) GRF_BIT(5 * (id)) 974 - #define RK3588_GMAC_CLK_RGMII_MODE(id) GRF_CLR_BIT(5 * (id)) 975 - 976 - #define RK3588_GMAC_CLK_SELECT_CRU(id) GRF_BIT(5 * (id) + 4) 977 - #define RK3588_GMAC_CLK_SELECT_IO(id) GRF_CLR_BIT(5 * (id) + 4) 978 - 979 - #define RK3588_GMAC_CLK_RMII_GATE(id) GRF_BIT(5 * (id) + 1) 980 - #define RK3588_GMAC_CLK_RMII_NOGATE(id) GRF_CLR_BIT(5 * (id) + 1) 981 - 982 1025 static int rk3588_init(struct rk_priv_data *bsp_priv) 983 1026 { 984 1027 switch (bsp_priv->id) { 985 1028 case 0: 986 1029 bsp_priv->gmac_phy_intf_sel_mask = GENMASK_U16(5, 3); 1030 + bsp_priv->clock.io_clksel_cru_mask = BIT_U16(4); 987 1031 bsp_priv->clock.gmii_clk_sel_mask = GENMASK_U16(3, 2); 988 1032 bsp_priv->clock.rmii_clk_sel_mask = BIT_U16(2); 1033 + bsp_priv->clock.rmii_gate_en_mask = BIT_U16(1); 1034 + bsp_priv->clock.rmii_mode_mask = BIT_U16(0); 989 1035 return 0; 990 1036 991 1037 case 1: 992 1038 bsp_priv->gmac_phy_intf_sel_mask = GENMASK_U16(11, 9); 1039 + bsp_priv->clock.io_clksel_cru_mask = BIT_U16(9); 993 1040 bsp_priv->clock.gmii_clk_sel_mask = GENMASK_U16(8, 7); 994 1041 bsp_priv->clock.rmii_clk_sel_mask = BIT_U16(7); 1042 + bsp_priv->clock.rmii_gate_en_mask = BIT_U16(6); 1043 + bsp_priv->clock.rmii_mode_mask = BIT_U16(5); 995 1044 return 0; 996 1045 997 1046 default: ··· 1004 1059 offset_con = bsp_priv->id == 1 ? RK3588_GRF_GMAC_CON9 : 1005 1060 RK3588_GRF_GMAC_CON8; 1006 1061 1007 - regmap_write(bsp_priv->php_grf, RK3588_GRF_CLK_CON1, 1008 - RK3588_GMAC_CLK_RGMII_MODE(id)); 1009 - 1010 1062 regmap_write(bsp_priv->grf, RK3588_GRF_GMAC_CON7, 1011 1063 RK3588_GMAC_RXCLK_DLY_ENABLE(id) | 1012 1064 RK3588_GMAC_TXCLK_DLY_ENABLE(id)); ··· 1013 1071 RK3588_GMAC_CLK_TX_DL_CFG(tx_delay)); 1014 1072 } 1015 1073 1016 - static void rk3588_set_to_rmii(struct rk_priv_data *bsp_priv) 1017 - { 1018 - regmap_write(bsp_priv->php_grf, RK3588_GRF_CLK_CON1, 1019 - RK3588_GMAC_CLK_RMII_MODE(bsp_priv->id)); 1020 - } 1021 - 1022 - static void rk3588_set_clock_selection(struct rk_priv_data *bsp_priv, bool input, 1023 - bool enable) 1024 - { 1025 - unsigned int val = input ? RK3588_GMAC_CLK_SELECT_IO(bsp_priv->id) : 1026 - RK3588_GMAC_CLK_SELECT_CRU(bsp_priv->id); 1027 - 1028 - val |= enable ? RK3588_GMAC_CLK_RMII_NOGATE(bsp_priv->id) : 1029 - RK3588_GMAC_CLK_RMII_GATE(bsp_priv->id); 1030 - 1031 - regmap_write(bsp_priv->php_grf, RK3588_GRF_CLK_CON1, val); 1032 - } 1033 - 1034 1074 static const struct rk_gmac_ops rk3588_ops = { 1035 1075 .init = rk3588_init, 1036 1076 .set_to_rgmii = rk3588_set_to_rgmii, 1037 - .set_to_rmii = rk3588_set_to_rmii, 1038 - .set_clock_selection = rk3588_set_clock_selection, 1039 1077 1040 1078 .gmac_grf_reg_in_php = true, 1041 1079 .gmac_grf_reg = RK3588_GRF_GMAC_CON0, 1042 1080 1043 1081 .clock_grf_reg_in_php = true, 1044 1082 .clock_grf_reg = RK3588_GRF_CLK_CON1, 1083 + 1084 + .supports_rmii = true, 1045 1085 1046 1086 .php_grf_required = true, 1047 1087 .regs_valid = true, ··· 1040 1116 #define RV1108_GMAC_FLOW_CTRL GRF_BIT(3) 1041 1117 #define RV1108_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3) 1042 1118 1043 - static void rv1108_set_to_rmii(struct rk_priv_data *bsp_priv) 1044 - { 1045 - } 1046 - 1047 1119 static const struct rk_gmac_ops rv1108_ops = { 1048 - .set_to_rmii = rv1108_set_to_rmii, 1049 - 1050 1120 .gmac_grf_reg = RV1108_GRF_GMAC_CON0, 1051 1121 .gmac_phy_intf_sel_mask = GENMASK_U16(6, 4), 1052 1122 1053 1123 .clock_grf_reg = RV1108_GRF_GMAC_CON0, 1054 1124 .clock.rmii_clk_sel_mask = BIT_U16(7), 1055 1125 .clock.mac_speed_mask = BIT_U16(2), 1126 + 1127 + .supports_rmii = true, 1056 1128 }; 1057 1129 1058 1130 #define RV1126_GRF_GMAC_CON0 0X0070 ··· 1092 1172 RV1126_GMAC_M1_CLK_TX_DL_CFG(tx_delay)); 1093 1173 } 1094 1174 1095 - static void rv1126_set_to_rmii(struct rk_priv_data *bsp_priv) 1096 - { 1097 - } 1098 - 1099 1175 static const struct rk_gmac_ops rv1126_ops = { 1100 1176 .set_to_rgmii = rv1126_set_to_rgmii, 1101 - .set_to_rmii = rv1126_set_to_rmii, 1102 1177 .set_speed = rk_set_clk_mac_speed, 1103 1178 1104 1179 .gmac_grf_reg = RV1126_GRF_GMAC_CON0, 1105 1180 .gmac_phy_intf_sel_mask = GENMASK_U16(6, 4), 1181 + 1182 + .supports_rmii = true, 1106 1183 }; 1107 1184 1108 1185 static int rk_gmac_clk_init(struct plat_stmmacenet_data *plat) ··· 1165 1248 if (ret) 1166 1249 return ret; 1167 1250 1168 - if (bsp_priv->ops && bsp_priv->ops->set_clock_selection) 1169 - bsp_priv->ops->set_clock_selection(bsp_priv, 1170 - bsp_priv->clock_input, true); 1251 + rk_configure_io_clksel(bsp_priv); 1252 + rk_ungate_rmii_clock(bsp_priv); 1171 1253 1172 1254 mdelay(5); 1173 1255 bsp_priv->clk_enabled = true; 1174 1256 } 1175 1257 } else { 1176 1258 if (bsp_priv->clk_enabled) { 1177 - if (bsp_priv->ops && bsp_priv->ops->set_clock_selection) { 1178 - bsp_priv->ops->set_clock_selection(bsp_priv, 1179 - bsp_priv->clock_input, false); 1180 - } 1259 + rk_gate_rmii_clock(bsp_priv); 1181 1260 1182 1261 clk_bulk_disable_unprepare(bsp_priv->num_clks, 1183 1262 bsp_priv->clks); ··· 1328 1415 bsp_priv->clock_grf_reg = ops->clock_grf_reg; 1329 1416 bsp_priv->clock = ops->clock; 1330 1417 1418 + bsp_priv->supports_rgmii = ops->supports_rgmii || !!ops->set_to_rgmii; 1419 + bsp_priv->supports_rmii = ops->supports_rmii || !!ops->set_to_rmii; 1420 + 1331 1421 if (ops->init) { 1332 1422 ret = ops->init(bsp_priv); 1333 1423 if (ret) { ··· 1339 1423 return ERR_PTR(ret); 1340 1424 } 1341 1425 } 1426 + 1427 + if (bsp_priv->clock.io_clksel_cru_mask && 1428 + bsp_priv->clock.io_clksel_io_mask) 1429 + dev_warn(dev, "both CRU and IO io_clksel masks should not be populated - driver may malfunction\n"); 1342 1430 1343 1431 return bsp_priv; 1344 1432 } ··· 1354 1434 case PHY_INTERFACE_MODE_RGMII_ID: 1355 1435 case PHY_INTERFACE_MODE_RGMII_RXID: 1356 1436 case PHY_INTERFACE_MODE_RGMII_TXID: 1357 - if (!bsp_priv->ops->set_to_rgmii) 1437 + if (!bsp_priv->supports_rgmii) 1358 1438 return -EINVAL; 1359 1439 break; 1360 1440 case PHY_INTERFACE_MODE_RMII: 1361 - if (!bsp_priv->ops->set_to_rmii) 1441 + if (!bsp_priv->supports_rmii) 1362 1442 return -EINVAL; 1363 1443 break; 1364 1444 default: ··· 1405 1485 } 1406 1486 } 1407 1487 1488 + if (bsp_priv->clock.rmii_mode_mask) { 1489 + val = rk_encode_wm16(intf == PHY_INTF_SEL_RMII, 1490 + bsp_priv->clock.rmii_mode_mask); 1491 + 1492 + ret = rk_write_clock_grf_reg(bsp_priv, val); 1493 + if (ret < 0) { 1494 + gmac_clk_enable(bsp_priv, false); 1495 + return ret; 1496 + } 1497 + } 1498 + 1408 1499 /*rmii or rgmii*/ 1409 1500 switch (bsp_priv->phy_iface) { 1410 1501 case PHY_INTERFACE_MODE_RGMII: 1411 1502 dev_info(dev, "init for RGMII\n"); 1412 - bsp_priv->ops->set_to_rgmii(bsp_priv, bsp_priv->tx_delay, 1413 - bsp_priv->rx_delay); 1503 + if (bsp_priv->ops->set_to_rgmii) 1504 + bsp_priv->ops->set_to_rgmii(bsp_priv, 1505 + bsp_priv->tx_delay, 1506 + bsp_priv->rx_delay); 1414 1507 break; 1415 1508 case PHY_INTERFACE_MODE_RGMII_ID: 1416 1509 dev_info(dev, "init for RGMII_ID\n"); 1417 - bsp_priv->ops->set_to_rgmii(bsp_priv, 0, 0); 1510 + if (bsp_priv->ops->set_to_rgmii) 1511 + bsp_priv->ops->set_to_rgmii(bsp_priv, 0, 0); 1418 1512 break; 1419 1513 case PHY_INTERFACE_MODE_RGMII_RXID: 1420 1514 dev_info(dev, "init for RGMII_RXID\n"); 1421 - bsp_priv->ops->set_to_rgmii(bsp_priv, bsp_priv->tx_delay, 0); 1515 + if (bsp_priv->ops->set_to_rgmii) 1516 + bsp_priv->ops->set_to_rgmii(bsp_priv, 1517 + bsp_priv->tx_delay, 0); 1422 1518 break; 1423 1519 case PHY_INTERFACE_MODE_RGMII_TXID: 1424 1520 dev_info(dev, "init for RGMII_TXID\n"); 1425 - bsp_priv->ops->set_to_rgmii(bsp_priv, 0, bsp_priv->rx_delay); 1521 + if (bsp_priv->ops->set_to_rgmii) 1522 + bsp_priv->ops->set_to_rgmii(bsp_priv, 1523 + 0, bsp_priv->rx_delay); 1426 1524 break; 1427 1525 case PHY_INTERFACE_MODE_RMII: 1428 1526 dev_info(dev, "init for RMII\n"); 1429 - bsp_priv->ops->set_to_rmii(bsp_priv); 1527 + if (bsp_priv->ops->set_to_rmii) 1528 + bsp_priv->ops->set_to_rmii(bsp_priv); 1430 1529 break; 1431 1530 default: 1432 1531 dev_err(dev, "NO interface defined!\n"); ··· 1481 1542 { 1482 1543 struct rk_priv_data *rk = bsp_priv; 1483 1544 1484 - if (rk->ops->set_to_rgmii) 1545 + if (rk->supports_rgmii) 1485 1546 phy_interface_set_rgmii(interfaces); 1486 1547 1487 - if (rk->ops->set_to_rmii) 1548 + if (rk->supports_rmii) 1488 1549 __set_bit(PHY_INTERFACE_MODE_RMII, interfaces); 1489 1550 } 1490 1551