tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'arm-fixes-6.11-3' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull ARM SoC fixes from Arnd Bergmann:
"The bulk of the changes this time are for device tree files in the
rockchips platform, addressing correctness issues on individual
boards, plus one change in the rk356x SoC file to make it match the
binding.

The only other changes that came in are

- a CPU frequencey scaling fix for JH7110 (RISC-V)

- a build fix for the cznic hwrandom driver

- a fix for a deadlock in qualcomm uefi secure application firmware
driver"

* tag 'arm-fixes-6.11-3' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc:
platform: cznic: turris-omnia-mcu: fix HW_RANDOM dependency
riscv: dts: starfive: jh7110-common: Fix lower rate of CPUfreq by setting PLL0 rate to 1.5GHz
firmware: qcom: uefisecapp: Fix deadlock in qcuefi_acquire()
arm64: dts: rockchip: Fix compatibles for RK3588 VO{0,1}_GRF
dt-bindings: soc: rockchip: Fix compatibles for RK3588 VO{0,1}_GRF
arm64: dts: rockchip: override BIOS_DISABLE signal via GPIO hog on RK3399 Puma
arm64: dts: rockchip: fix eMMC/SPI corruption when audio has been used on RK3399 Puma
arm64: dts: rockchip: fix PMIC interrupt pin in pinctrl for ROCK Pi E
arm64: dts: rockchip: Remove broken tsadc pinctrl binding for rk356x

Linus Torvalds 77f58789 3857c7b0

+60 -13
+9 -1
Documentation/devicetree/bindings/soc/rockchip/grf.yaml
··· 31 31 - rockchip,rk3588-pcie3-pipe-grf 32 32 - rockchip,rk3588-usb-grf 33 33 - rockchip,rk3588-usbdpphy-grf 34 - - rockchip,rk3588-vo-grf 34 + - rockchip,rk3588-vo0-grf 35 + - rockchip,rk3588-vo1-grf 35 36 - rockchip,rk3588-vop-grf 36 37 - rockchip,rv1108-usbgrf 37 38 - const: syscon 39 + - items: 40 + - const: rockchip,rk3588-vo-grf 41 + - const: syscon 42 + deprecated: true 43 + description: Use rockchip,rk3588-vo{0,1}-grf instead. 38 44 - items: 39 45 - enum: 40 46 - rockchip,px30-grf ··· 268 262 contains: 269 263 enum: 270 264 - rockchip,rk3588-vo-grf 265 + - rockchip,rk3588-vo0-grf 266 + - rockchip,rk3588-vo1-grf 271 267 272 268 then: 273 269 required:
+1 -1
arch/arm64/boot/dts/rockchip/rk3328-rock-pi-e.dts
··· 387 387 388 388 pmic { 389 389 pmic_int_l: pmic-int-l { 390 - rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; 390 + rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; 391 391 }; 392 392 }; 393 393
+33 -3
arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi
··· 154 154 }; 155 155 }; 156 156 157 + &gpio3 { 158 + /* 159 + * The Qseven BIOS_DISABLE signal on the RK3399-Q7 keeps the on-module 160 + * eMMC and SPI flash powered-down initially (in fact it keeps the 161 + * reset signal asserted). BIOS_DISABLE_OVERRIDE pin allows to override 162 + * that signal so that eMMC and SPI can be used regardless of the state 163 + * of the signal. 164 + */ 165 + bios-disable-override-hog { 166 + gpios = <RK_PD5 GPIO_ACTIVE_LOW>; 167 + gpio-hog; 168 + line-name = "bios_disable_override"; 169 + output-high; 170 + }; 171 + }; 172 + 157 173 &gmac { 158 174 assigned-clocks = <&cru SCLK_RMII_SRC>; 159 175 assigned-clock-parents = <&clkin_gmac>; ··· 425 409 426 410 &i2s0 { 427 411 pinctrl-0 = <&i2s0_2ch_bus>; 412 + pinctrl-1 = <&i2s0_2ch_bus_bclk_off>; 428 413 rockchip,playback-channels = <2>; 429 414 rockchip,capture-channels = <2>; 430 415 status = "okay"; ··· 434 417 /* 435 418 * As Q7 does not specify neither a global nor a RX clock for I2S these 436 419 * signals are not used. Furthermore I2S0_LRCK_RX is used as GPIO. 437 - * Therefore we have to redefine the i2s0_2ch_bus definition to prevent 438 - * conflicts. 420 + * Therefore we have to redefine the i2s0_2ch_bus and i2s0_2ch_bus_bclk_off 421 + * definitions to prevent conflicts. 439 422 */ 440 423 &i2s0_2ch_bus { 441 424 rockchip,pins = 442 425 <3 RK_PD0 1 &pcfg_pull_none>, 426 + <3 RK_PD2 1 &pcfg_pull_none>, 427 + <3 RK_PD3 1 &pcfg_pull_none>, 428 + <3 RK_PD7 1 &pcfg_pull_none>; 429 + }; 430 + 431 + &i2s0_2ch_bus_bclk_off { 432 + rockchip,pins = 433 + <3 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>, 443 434 <3 RK_PD2 1 &pcfg_pull_none>, 444 435 <3 RK_PD3 1 &pcfg_pull_none>, 445 436 <3 RK_PD7 1 &pcfg_pull_none>; ··· 474 449 475 450 &pinctrl { 476 451 pinctrl-names = "default"; 477 - pinctrl-0 = <&q7_thermal_pin>; 452 + pinctrl-0 = <&q7_thermal_pin &bios_disable_override_hog_pin>; 478 453 479 454 gpios { 455 + bios_disable_override_hog_pin: bios-disable-override-hog-pin { 456 + rockchip,pins = 457 + <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_down>; 458 + }; 459 + 480 460 q7_thermal_pin: q7-thermal-pin { 481 461 rockchip,pins = 482 462 <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
+3 -4
arch/arm64/boot/dts/rockchip/rk356x.dtsi
··· 1592 1592 <&cru SRST_TSADCPHY>; 1593 1593 rockchip,grf = <&grf>; 1594 1594 rockchip,hw-tshut-temp = <95000>; 1595 - pinctrl-names = "init", "default", "sleep"; 1596 - pinctrl-0 = <&tsadc_pin>; 1597 - pinctrl-1 = <&tsadc_shutorg>; 1598 - pinctrl-2 = <&tsadc_pin>; 1595 + pinctrl-names = "default", "sleep"; 1596 + pinctrl-0 = <&tsadc_shutorg>; 1597 + pinctrl-1 = <&tsadc_pin>; 1599 1598 #thermal-sensor-cells = <1>; 1600 1599 status = "disabled"; 1601 1600 };
+3 -3
arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
··· 582 582 }; 583 583 584 584 vo0_grf: syscon@fd5a6000 { 585 - compatible = "rockchip,rk3588-vo-grf", "syscon"; 585 + compatible = "rockchip,rk3588-vo0-grf", "syscon"; 586 586 reg = <0x0 0xfd5a6000 0x0 0x2000>; 587 587 clocks = <&cru PCLK_VO0GRF>; 588 588 }; 589 589 590 590 vo1_grf: syscon@fd5a8000 { 591 - compatible = "rockchip,rk3588-vo-grf", "syscon"; 592 - reg = <0x0 0xfd5a8000 0x0 0x100>; 591 + compatible = "rockchip,rk3588-vo1-grf", "syscon"; 592 + reg = <0x0 0xfd5a8000 0x0 0x4000>; 593 593 clocks = <&cru PCLK_VO1GRF>; 594 594 }; 595 595
+6
arch/riscv/boot/dts/starfive/jh7110-common.dtsi
··· 365 365 }; 366 366 }; 367 367 368 + &syscrg { 369 + assigned-clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>, 370 + <&pllclk JH7110_PLLCLK_PLL0_OUT>; 371 + assigned-clock-rates = <500000000>, <1500000000>; 372 + }; 373 + 368 374 &sysgpio { 369 375 i2c0_pins: i2c0-0 { 370 376 i2c-pins {
+4
drivers/firmware/qcom/qcom_qseecom_uefisecapp.c
··· 715 715 static struct qcuefi_client *qcuefi_acquire(void) 716 716 { 717 717 mutex_lock(&__qcuefi_lock); 718 + if (!__qcuefi) { 719 + mutex_unlock(&__qcuefi_lock); 720 + return NULL; 721 + } 718 722 return __qcuefi; 719 723 } 720 724
+1 -1
drivers/platform/cznic/Kconfig
··· 70 70 bool "Turris Omnia MCU true random number generator" 71 71 default y 72 72 depends on TURRIS_OMNIA_MCU_GPIO 73 - depends on HW_RANDOM 73 + depends on HW_RANDOM=y || HW_RANDOM=TURRIS_OMNIA_MCU 74 74 help 75 75 Say Y here to add support for the true random number generator 76 76 provided by CZ.NIC's Turris Omnia MCU.