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pinctrl: imx: Support NXP scmi extended mux config

i.MX94 has special muxing options for certain pins. Their mux settings
are not in IOMUXC module. i.MX System Manager Firmware includes new vendor
defined pinctrl type to SCMI pinctrl driver to handle these pins. The MUX
value field in the IOMUX table is extended to 16 bits where the lower 8
bits represent the current IOMUX value and the upper 8 bits represent the
new extended mux added in i.MX94.

Signed-off-by: Ranjani Vaidyanathan <ranjani.vaidyanathan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Linus Walleij <linusw@kernel.org>

authored by

Ranjani Vaidyanathan and committed by
Linus Walleij 78160900 34f2866b

+10 -2
+10 -2
drivers/pinctrl/freescale/pinctrl-imx-scmi.c
··· 38 38 }; 39 39 40 40 /* SCMI pin control types, aligned with SCMI firmware */ 41 - #define IMX_SCMI_NUM_CFG 4 41 + #define IMX_SCMI_NUM_CFG 5 42 42 #define IMX_SCMI_PIN_MUX 192 43 43 #define IMX_SCMI_PIN_CONFIG 193 44 44 #define IMX_SCMI_PIN_DAISY_ID 194 45 45 #define IMX_SCMI_PIN_DAISY_CFG 195 46 + #define IMX_SCMI_PIN_EXT 196 46 47 47 48 #define IMX_SCMI_NO_PAD_CTL BIT(31) 48 49 #define IMX_SCMI_PAD_SION BIT(30) ··· 119 118 120 119 pin_id = mux_reg / 4; 121 120 122 - cfg[j++] = pinconf_to_config_packed(IMX_SCMI_PIN_MUX, mux_val); 121 + cfg[j++] = pinconf_to_config_packed(IMX_SCMI_PIN_MUX, (mux_val & 0xFF)); 122 + 123 + if (mux_val & 0xFF00) { 124 + int ext_val = (mux_val & 0xFF00) >> 8; 125 + 126 + cfg[j++] = pinconf_to_config_packed(IMX_SCMI_PIN_EXT, ext_val); 127 + } else 128 + ncfg--; 123 129 124 130 if (!conf_reg || (conf_val & IMX_SCMI_NO_PAD_CTL)) 125 131 ncfg--;