Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC fixes from Olof Johansson:
"A handful of fixes before final release:
Marvell Armada:
- One to fix a typo in the devicetree specifying memory ranges for
the crypto engine
- Two to deal with marking PCI and device-memory as strongly ordered
to avoid hardware deadlocks, in particular when enabling above
crypto driver.
- Compile fix for PM
Allwinner:
- DT clock fixes to deal with u-boot-enabled framebuffer (simplefb).
- Make R8 (C.H.I.P. SoC) inherit system compatibility from A13 to
make clocks register proper.
Tegra:
- Fix SD card voltage setting on the Tegra3 Beaver dev board
Misc:
- Two maintainers updates for STM32 and STi platforms"
* tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
ARM: tegra: beaver: Allow SD card voltage to be changed
MAINTAINERS: update STi maintainer list
MAINTAINERS: update STM32 maintainers list
ARM: mvebu: compile pm code conditionally
ARM: dts: sun7i: Fix pll3x2 and pll7x2 not having a parent clock
ARM: dts: sunxi: Add pll3 to simplefb nodes clocks lists
ARM: dts: armada-38x: fix MBUS_ID for crypto SRAM on Armada 385 Linksys
ARM: mvebu: map PCI I/O regions strongly ordered
ARM: mvebu: fix HW I/O coherency related deadlocks
ARM: sunxi/dt: make the CHIP inherit from allwinner,sun5i-a13
+49
-41
+1
-2
MAINTAINERS
+1
-2
MAINTAINERS
···
1694
1694
F: drivers/edac/altera_edac.
1695
1695
1696
1696
ARM/STI ARCHITECTURE
1697
-
M: Srinivas Kandagatla <srinivas.kandagatla@gmail.com>
1698
-
M: Maxime Coquelin <maxime.coquelin@st.com>
1699
1697
M: Patrice Chotard <patrice.chotard@st.com>
1700
1698
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
1701
1699
L: kernel@stlinux.com
···
1726
1728
1727
1729
ARM/STM32 ARCHITECTURE
1728
1730
M: Maxime Coquelin <mcoquelin.stm32@gmail.com>
1731
+
M: Alexandre Torgue <alexandre.torgue@st.com>
1729
1732
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
1730
1733
S: Maintained
1731
1734
T: git git://git.kernel.org/pub/scm/linux/kernel/git/mcoquelin/stm32.git
+2
-2
arch/arm/boot/dts/armada-385-linksys.dtsi
+2
-2
arch/arm/boot/dts/armada-385-linksys.dtsi
···
58
58
soc {
59
59
ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
60
60
MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
61
-
MBUS_ID(0x09, 0x09) 0 0xf1100000 0x10000
62
-
MBUS_ID(0x09, 0x05) 0 0xf1110000 0x10000>;
61
+
MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
62
+
MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000>;
63
63
64
64
internal-regs {
65
65
+12
-9
arch/arm/boot/dts/sun4i-a10.dtsi
+12
-9
arch/arm/boot/dts/sun4i-a10.dtsi
···
65
65
compatible = "allwinner,simple-framebuffer",
66
66
"simple-framebuffer";
67
67
allwinner,pipeline = "de_be0-lcd0-hdmi";
68
-
clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>,
69
-
<&ahb_gates 44>, <&dram_gates 26>;
68
+
clocks = <&pll3>, <&pll5 1>, <&ahb_gates 36>,
69
+
<&ahb_gates 43>, <&ahb_gates 44>,
70
+
<&dram_gates 26>;
70
71
status = "disabled";
71
72
};
72
73
···
75
74
compatible = "allwinner,simple-framebuffer",
76
75
"simple-framebuffer";
77
76
allwinner,pipeline = "de_fe0-de_be0-lcd0-hdmi";
78
-
clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>,
79
-
<&ahb_gates 44>, <&ahb_gates 46>,
77
+
clocks = <&pll3>, <&pll5 1>, <&ahb_gates 36>,
78
+
<&ahb_gates 43>, <&ahb_gates 44>,
79
+
<&ahb_gates 46>,
80
80
<&dram_gates 25>, <&dram_gates 26>;
81
81
status = "disabled";
82
82
};
···
86
84
compatible = "allwinner,simple-framebuffer",
87
85
"simple-framebuffer";
88
86
allwinner,pipeline = "de_fe0-de_be0-lcd0";
89
-
clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>,
90
-
<&ahb_gates 46>, <&dram_gates 25>,
91
-
<&dram_gates 26>;
87
+
clocks = <&pll3>, <&pll5 1>, <&ahb_gates 36>,
88
+
<&ahb_gates 44>, <&ahb_gates 46>,
89
+
<&dram_gates 25>, <&dram_gates 26>;
92
90
status = "disabled";
93
91
};
94
92
···
96
94
compatible = "allwinner,simple-framebuffer",
97
95
"simple-framebuffer";
98
96
allwinner,pipeline = "de_fe0-de_be0-lcd0-tve0";
99
-
clocks = <&pll5 1>, <&ahb_gates 34>, <&ahb_gates 36>,
100
-
<&ahb_gates 44>, <&ahb_gates 46>,
97
+
clocks = <&pll3>, <&pll5 1>, <&ahb_gates 34>,
98
+
<&ahb_gates 36>, <&ahb_gates 44>,
99
+
<&ahb_gates 46>,
101
100
<&dram_gates 5>, <&dram_gates 25>, <&dram_gates 26>;
102
101
status = "disabled";
103
102
};
+6
-5
arch/arm/boot/dts/sun5i-a10s.dtsi
+6
-5
arch/arm/boot/dts/sun5i-a10s.dtsi
···
65
65
compatible = "allwinner,simple-framebuffer",
66
66
"simple-framebuffer";
67
67
allwinner,pipeline = "de_be0-lcd0-hdmi";
68
-
clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>,
69
-
<&ahb_gates 44>;
68
+
clocks = <&pll3>, <&pll5 1>, <&ahb_gates 36>,
69
+
<&ahb_gates 43>, <&ahb_gates 44>;
70
70
status = "disabled";
71
71
};
72
72
···
74
74
compatible = "allwinner,simple-framebuffer",
75
75
"simple-framebuffer";
76
76
allwinner,pipeline = "de_be0-lcd0";
77
-
clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>;
77
+
clocks = <&pll3>, <&pll5 1>, <&ahb_gates 36>,
78
+
<&ahb_gates 44>;
78
79
status = "disabled";
79
80
};
80
81
···
83
82
compatible = "allwinner,simple-framebuffer",
84
83
"simple-framebuffer";
85
84
allwinner,pipeline = "de_be0-lcd0-tve0";
86
-
clocks = <&pll5 1>, <&ahb_gates 34>, <&ahb_gates 36>,
87
-
<&ahb_gates 44>;
85
+
clocks = <&pll3>, <&pll5 1>, <&ahb_gates 34>,
86
+
<&ahb_gates 36>, <&ahb_gates 44>;
88
87
status = "disabled";
89
88
};
90
89
};
+1
-1
arch/arm/boot/dts/sun5i-r8-chip.dts
+1
-1
arch/arm/boot/dts/sun5i-r8-chip.dts
+8
-5
arch/arm/boot/dts/sun7i-a20.dtsi
+8
-5
arch/arm/boot/dts/sun7i-a20.dtsi
···
67
67
compatible = "allwinner,simple-framebuffer",
68
68
"simple-framebuffer";
69
69
allwinner,pipeline = "de_be0-lcd0-hdmi";
70
-
clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>,
71
-
<&ahb_gates 44>, <&dram_gates 26>;
70
+
clocks = <&pll3>, <&pll5 1>, <&ahb_gates 36>,
71
+
<&ahb_gates 43>, <&ahb_gates 44>,
72
+
<&dram_gates 26>;
72
73
status = "disabled";
73
74
};
74
75
···
77
76
compatible = "allwinner,simple-framebuffer",
78
77
"simple-framebuffer";
79
78
allwinner,pipeline = "de_be0-lcd0";
80
-
clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>,
81
-
<&dram_gates 26>;
79
+
clocks = <&pll3>, <&pll5 1>, <&ahb_gates 36>,
80
+
<&ahb_gates 44>, <&dram_gates 26>;
82
81
status = "disabled";
83
82
};
84
83
···
86
85
compatible = "allwinner,simple-framebuffer",
87
86
"simple-framebuffer";
88
87
allwinner,pipeline = "de_be0-lcd0-tve0";
89
-
clocks = <&pll5 1>,
88
+
clocks = <&pll3>, <&pll5 1>,
90
89
<&ahb_gates 34>, <&ahb_gates 36>, <&ahb_gates 44>,
91
90
<&dram_gates 5>, <&dram_gates 26>;
92
91
status = "disabled";
···
232
231
pll3x2: pll3x2_clk {
233
232
#clock-cells = <0>;
234
233
compatible = "fixed-factor-clock";
234
+
clocks = <&pll3>;
235
235
clock-div = <1>;
236
236
clock-mult = <2>;
237
237
clock-output-names = "pll3-2x";
···
274
272
pll7x2: pll7x2_clk {
275
273
#clock-cells = <0>;
276
274
compatible = "fixed-factor-clock";
275
+
clocks = <&pll7>;
277
276
clock-div = <1>;
278
277
clock-mult = <2>;
279
278
clock-output-names = "pll7-2x";
+2
-1
arch/arm/boot/dts/tegra30-beaver.dts
+2
-1
arch/arm/boot/dts/tegra30-beaver.dts
···
1843
1843
1844
1844
ldo5_reg: ldo5 {
1845
1845
regulator-name = "vddio_sdmmc,avdd_vdac";
1846
-
regulator-min-microvolt = <3300000>;
1846
+
regulator-min-microvolt = <1800000>;
1847
1847
regulator-max-microvolt = <3300000>;
1848
1848
regulator-always-on;
1849
1849
};
···
1914
1914
1915
1915
sdhci@78000000 {
1916
1916
status = "okay";
1917
+
vqmmc-supply = <&ldo5_reg>;
1917
1918
cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
1918
1919
wp-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>;
1919
1920
power-gpios = <&gpio TEGRA_GPIO(D, 7) GPIO_ACTIVE_HIGH>;
+8
-2
arch/arm/mach-mvebu/Makefile
+8
-2
arch/arm/mach-mvebu/Makefile
···
7
7
obj-$(CONFIG_MACH_MVEBU_ANY) += system-controller.o mvebu-soc-id.o
8
8
9
9
ifeq ($(CONFIG_MACH_MVEBU_V7),y)
10
-
obj-y += cpu-reset.o board-v7.o coherency.o coherency_ll.o pmsu.o pmsu_ll.o pm.o pm-board.o
10
+
obj-y += cpu-reset.o board-v7.o coherency.o coherency_ll.o pmsu.o pmsu_ll.o
11
+
12
+
obj-$(CONFIG_PM) += pm.o pm-board.o
11
13
obj-$(CONFIG_SMP) += platsmp.o headsmp.o platsmp-a9.o headsmp-a9.o
12
14
endif
13
15
14
16
obj-$(CONFIG_MACH_DOVE) += dove.o
15
-
obj-$(CONFIG_MACH_KIRKWOOD) += kirkwood.o kirkwood-pm.o
17
+
18
+
ifeq ($(CONFIG_MACH_KIRKWOOD),y)
19
+
obj-y += kirkwood.o
20
+
obj-$(CONFIG_PM) += kirkwood-pm.o
21
+
endif
+9
-14
arch/arm/mach-mvebu/coherency.c
+9
-14
arch/arm/mach-mvebu/coherency.c
···
162
162
}
163
163
164
164
/*
165
-
* This ioremap hook is used on Armada 375/38x to ensure that PCIe
166
-
* memory areas are mapped as MT_UNCACHED instead of MT_DEVICE. This
167
-
* is needed as a workaround for a deadlock issue between the PCIe
168
-
* interface and the cache controller.
165
+
* This ioremap hook is used on Armada 375/38x to ensure that all MMIO
166
+
* areas are mapped as MT_UNCACHED instead of MT_DEVICE. This is
167
+
* needed for the HW I/O coherency mechanism to work properly without
168
+
* deadlock.
169
169
*/
170
170
static void __iomem *
171
-
armada_pcie_wa_ioremap_caller(phys_addr_t phys_addr, size_t size,
172
-
unsigned int mtype, void *caller)
171
+
armada_wa_ioremap_caller(phys_addr_t phys_addr, size_t size,
172
+
unsigned int mtype, void *caller)
173
173
{
174
-
struct resource pcie_mem;
175
-
176
-
mvebu_mbus_get_pcie_mem_aperture(&pcie_mem);
177
-
178
-
if (pcie_mem.start <= phys_addr && (phys_addr + size) <= pcie_mem.end)
179
-
mtype = MT_UNCACHED;
180
-
174
+
mtype = MT_UNCACHED;
181
175
return __arm_ioremap_caller(phys_addr, size, mtype, caller);
182
176
}
183
177
···
180
186
struct device_node *cache_dn;
181
187
182
188
coherency_cpu_base = of_iomap(np, 0);
183
-
arch_ioremap_caller = armada_pcie_wa_ioremap_caller;
189
+
arch_ioremap_caller = armada_wa_ioremap_caller;
190
+
pci_ioremap_set_mem_type(MT_UNCACHED);
184
191
185
192
/*
186
193
* We should switch the PL310 to I/O coherency mode only if