Merge tag 'for-linus-20161104' of git://git.infradead.org/linux-mtd

+15

MAINTAINERS

··· 7925 7925 MEMORY TECHNOLOGY DEVICES (MTD) 7926 7926 M: David Woodhouse <dwmw2@infradead.org> 7927 7927 M: Brian Norris <computersforpeace@gmail.com> 7928 + M: Boris Brezillon <boris.brezillon@free-electrons.com> 7929 + M: Marek Vasut <marek.vasut@gmail.com> 7930 + M: Richard Weinberger <richard@nod.at> 7931 + M: Cyrille Pitchen <cyrille.pitchen@atmel.com> 7928 7932 L: linux-mtd@lists.infradead.org 7929 7933 W: http://www.linux-mtd.infradead.org/ 7930 7934 Q: http://patchwork.ozlabs.org/project/linux-mtd/list/ ··· 11407 11403 W: http://www.st.com/spear 11408 11404 S: Maintained 11409 11405 F: drivers/clk/spear/ 11406 + 11407 + SPI NOR SUBSYSTEM 11408 + M: Cyrille Pitchen <cyrille.pitchen@atmel.com> 11409 + M: Marek Vasut <marek.vasut@gmail.com> 11410 + L: linux-mtd@lists.infradead.org 11411 + W: http://www.linux-mtd.infradead.org/ 11412 + Q: http://patchwork.ozlabs.org/project/linux-mtd/list/ 11413 + T: git git://github.com/spi-nor/linux.git 11414 + S: Maintained 11415 + F: drivers/mtd/spi-nor/ 11416 + F: include/linux/mtd/spi-nor.h 11410 11417 11411 11418 SPI SUBSYSTEM 11412 11419 M: Mark Brown <broonie@kernel.org>

+4 -2

drivers/mtd/nand/gpmi-nand/gpmi-lib.c

··· 161 161 162 162 ret = gpmi_enable_clk(this); 163 163 if (ret) 164 - goto err_out; 164 + return ret; 165 165 ret = gpmi_reset_block(r->gpmi_regs, false); 166 166 if (ret) 167 167 goto err_out; ··· 197 197 gpmi_disable_clk(this); 198 198 return 0; 199 199 err_out: 200 + gpmi_disable_clk(this); 200 201 return ret; 201 202 } 202 203 ··· 271 270 272 271 ret = gpmi_enable_clk(this); 273 272 if (ret) 274 - goto err_out; 273 + return ret; 275 274 276 275 /* 277 276 * Due to erratum #2847 of the MX23, the BCH cannot be soft reset on this ··· 309 308 gpmi_disable_clk(this); 310 309 return 0; 311 310 err_out: 311 + gpmi_disable_clk(this); 312 312 return ret; 313 313 } 314 314

+9 -10

drivers/mtd/nand/mtk_ecc.c

··· 86 86 struct completion done; 87 87 struct mutex lock; 88 88 u32 sectors; 89 + 90 + u8 eccdata[112]; 89 91 }; 90 92 91 93 static inline void mtk_ecc_wait_idle(struct mtk_ecc *ecc, ··· 368 366 u8 *data, u32 bytes) 369 367 { 370 368 dma_addr_t addr; 371 - u8 *p; 372 - u32 len, i, val; 373 - int ret = 0; 369 + u32 len; 370 + int ret; 374 371 375 372 addr = dma_map_single(ecc->dev, data, bytes, DMA_TO_DEVICE); 376 373 ret = dma_mapping_error(ecc->dev, addr); ··· 394 393 395 394 /* Program ECC bytes to OOB: per sector oob = FDM + ECC + SPARE */ 396 395 len = (config->strength * ECC_PARITY_BITS + 7) >> 3; 397 - p = data + bytes; 398 396 399 - /* write the parity bytes generated by the ECC back to the OOB region */ 400 - for (i = 0; i < len; i++) { 401 - if ((i % 4) == 0) 402 - val = readl(ecc->regs + ECC_ENCPAR(i / 4)); 403 - p[i] = (val >> ((i % 4) * 8)) & 0xff; 404 - } 397 + /* write the parity bytes generated by the ECC back to temp buffer */ 398 + __ioread32_copy(ecc->eccdata, ecc->regs + ECC_ENCPAR(0), round_up(len, 4)); 399 + 400 + /* copy into possibly unaligned OOB region with actual length */ 401 + memcpy(data + bytes, ecc->eccdata, len); 405 402 timeout: 406 403 407 404 dma_unmap_single(ecc->dev, addr, bytes, DMA_TO_DEVICE);

+42 -18

drivers/mtd/nand/nand_base.c

··· 1095 1095 /** 1096 1096 * nand_reset - Reset and initialize a NAND device 1097 1097 * @chip: The NAND chip 1098 + * @chipnr: Internal die id 1098 1099 * 1099 1100 * Returns 0 for success or negative error code otherwise 1100 1101 */ 1101 - int nand_reset(struct nand_chip *chip) 1102 + int nand_reset(struct nand_chip *chip, int chipnr) 1102 1103 { 1103 1104 struct mtd_info *mtd = nand_to_mtd(chip); 1104 1105 int ret; ··· 1108 1107 if (ret) 1109 1108 return ret; 1110 1109 1110 + /* 1111 + * The CS line has to be released before we can apply the new NAND 1112 + * interface settings, hence this weird ->select_chip() dance. 1113 + */ 1114 + chip->select_chip(mtd, chipnr); 1111 1115 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); 1116 + chip->select_chip(mtd, -1); 1112 1117 1118 + chip->select_chip(mtd, chipnr); 1113 1119 ret = nand_setup_data_interface(chip); 1120 + chip->select_chip(mtd, -1); 1114 1121 if (ret) 1115 1122 return ret; 1116 1123 ··· 1194 1185 /* Shift to get chip number */ 1195 1186 chipnr = ofs >> chip->chip_shift; 1196 1187 1197 - chip->select_chip(mtd, chipnr); 1198 - 1199 1188 /* 1200 1189 * Reset the chip. 1201 1190 * If we want to check the WP through READ STATUS and check the bit 7 ··· 1201 1194 * some operation can also clear the bit 7 of status register 1202 1195 * eg. erase/program a locked block 1203 1196 */ 1204 - nand_reset(chip); 1197 + nand_reset(chip, chipnr); 1198 + 1199 + chip->select_chip(mtd, chipnr); 1205 1200 1206 1201 /* Check, if it is write protected */ 1207 1202 if (nand_check_wp(mtd)) { ··· 1253 1244 /* Shift to get chip number */ 1254 1245 chipnr = ofs >> chip->chip_shift; 1255 1246 1256 - chip->select_chip(mtd, chipnr); 1257 - 1258 1247 /* 1259 1248 * Reset the chip. 1260 1249 * If we want to check the WP through READ STATUS and check the bit 7 ··· 1260 1253 * some operation can also clear the bit 7 of status register 1261 1254 * eg. erase/program a locked block 1262 1255 */ 1263 - nand_reset(chip); 1256 + nand_reset(chip, chipnr); 1257 + 1258 + chip->select_chip(mtd, chipnr); 1264 1259 1265 1260 /* Check, if it is write protected */ 1266 1261 if (nand_check_wp(mtd)) { ··· 2949 2940 } 2950 2941 2951 2942 chipnr = (int)(to >> chip->chip_shift); 2952 - chip->select_chip(mtd, chipnr); 2953 - 2954 - /* Shift to get page */ 2955 - page = (int)(to >> chip->page_shift); 2956 2943 2957 2944 /* 2958 2945 * Reset the chip. Some chips (like the Toshiba TC5832DC found in one ··· 2956 2951 * if we don't do this. I have no clue why, but I seem to have 'fixed' 2957 2952 * it in the doc2000 driver in August 1999. dwmw2. 2958 2953 */ 2959 - nand_reset(chip); 2954 + nand_reset(chip, chipnr); 2955 + 2956 + chip->select_chip(mtd, chipnr); 2957 + 2958 + /* Shift to get page */ 2959 + page = (int)(to >> chip->page_shift); 2960 2960 2961 2961 /* Check, if it is write protected */ 2962 2962 if (nand_check_wp(mtd)) { ··· 3994 3984 int i, maf_idx; 3995 3985 u8 id_data[8]; 3996 3986 3997 - /* Select the device */ 3998 - chip->select_chip(mtd, 0); 3999 - 4000 3987 /* 4001 3988 * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx) 4002 3989 * after power-up. 4003 3990 */ 4004 - nand_reset(chip); 3991 + nand_reset(chip, 0); 3992 + 3993 + /* Select the device */ 3994 + chip->select_chip(mtd, 0); 4005 3995 4006 3996 /* Send the command for reading device ID */ 4007 3997 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); ··· 4339 4329 return PTR_ERR(type); 4340 4330 } 4341 4331 4332 + /* Initialize the ->data_interface field. */ 4342 4333 ret = nand_init_data_interface(chip); 4334 + if (ret) 4335 + return ret; 4336 + 4337 + /* 4338 + * Setup the data interface correctly on the chip and controller side. 4339 + * This explicit call to nand_setup_data_interface() is only required 4340 + * for the first die, because nand_reset() has been called before 4341 + * ->data_interface and ->default_onfi_timing_mode were set. 4342 + * For the other dies, nand_reset() will automatically switch to the 4343 + * best mode for us. 4344 + */ 4345 + ret = nand_setup_data_interface(chip); 4343 4346 if (ret) 4344 4347 return ret; 4345 4348 ··· 4360 4337 4361 4338 /* Check for a chip array */ 4362 4339 for (i = 1; i < maxchips; i++) { 4363 - chip->select_chip(mtd, i); 4364 4340 /* See comment in nand_get_flash_type for reset */ 4365 - nand_reset(chip); 4341 + nand_reset(chip, i); 4342 + 4343 + chip->select_chip(mtd, i); 4366 4344 /* Send the command for reading device ID */ 4367 4345 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); 4368 4346 /* Read manufacturer and device IDs */

+1 -1

include/linux/mtd/nand.h

··· 1184 1184 int page); 1185 1185 1186 1186 /* Reset and initialize a NAND device */ 1187 - int nand_reset(struct nand_chip *chip); 1187 + int nand_reset(struct nand_chip *chip, int chipnr); 1188 1188 1189 1189 /* Free resources held by the NAND device */ 1190 1190 void nand_cleanup(struct nand_chip *chip);

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