Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch '20240202-x1e80100-clock-controllers-v4-5-7fb08c861c7c@linaro.org' into clk-for-6.9
Merge X1E clock bindings through a topic branch, to make the defines
available for inclusion in DeviceTree branches as well.
+327
-107
+2
Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml
+2
Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml
···
17
17
include/dt-bindings/clock/qcom,sm8450-camcc.h
18
18
include/dt-bindings/clock/qcom,sm8550-camcc.h
19
19
include/dt-bindings/clock/qcom,sc8280xp-camcc.h
20
+
include/dt-bindings/clock/qcom,x1e80100-camcc.h
20
21
21
22
allOf:
22
23
- $ref: qcom,gcc.yaml#
···
28
27
- qcom,sc8280xp-camcc
29
28
- qcom,sm8450-camcc
30
29
- qcom,sm8550-camcc
30
+
- qcom,x1e80100-camcc
31
31
32
32
clocks:
33
33
items:
+2
Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml
+2
Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml
···
18
18
include/dt-bindings/clock/qcom,sm8550-gpucc.h
19
19
include/dt-bindings/reset/qcom,sm8450-gpucc.h
20
20
include/dt-bindings/reset/qcom,sm8650-gpucc.h
21
+
include/dt-bindings/reset/qcom,x1e80100-gpucc.h
21
22
22
23
properties:
23
24
compatible:
···
26
25
- qcom,sm8450-gpucc
27
26
- qcom,sm8550-gpucc
28
27
- qcom,sm8650-gpucc
28
+
- qcom,x1e80100-gpucc
29
29
30
30
clocks:
31
31
items:
+6
-1
Documentation/devicetree/bindings/clock/qcom,sm8550-dispcc.yaml
+6
-1
Documentation/devicetree/bindings/clock/qcom,sm8550-dispcc.yaml
···
14
14
Qualcomm display clock control module provides the clocks, resets and power
15
15
domains on SM8550.
16
16
17
-
See also:: include/dt-bindings/clock/qcom,sm8550-dispcc.h
17
+
See also:
18
+
- include/dt-bindings/clock/qcom,sm8550-dispcc.h
19
+
- include/dt-bindings/clock/qcom,sm8650-dispcc.h
20
+
- include/dt-bindings/clock/qcom,x1e80100-dispcc.h
18
21
19
22
properties:
20
23
compatible:
21
24
enum:
22
25
- qcom,sm8550-dispcc
26
+
- qcom,sm8650-dispcc
27
+
- qcom,x1e80100-dispcc
23
28
24
29
clocks:
25
30
items:
+1
Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml
+1
Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml
-106
Documentation/devicetree/bindings/clock/qcom,sm8650-dispcc.yaml
-106
Documentation/devicetree/bindings/clock/qcom,sm8650-dispcc.yaml
···
1
-
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
-
%YAML 1.2
3
-
---
4
-
$id: http://devicetree.org/schemas/clock/qcom,sm8650-dispcc.yaml#
5
-
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
-
7
-
title: Qualcomm Display Clock & Reset Controller for SM8650
8
-
9
-
maintainers:
10
-
- Bjorn Andersson <andersson@kernel.org>
11
-
- Neil Armstrong <neil.armstrong@linaro.org>
12
-
13
-
description: |
14
-
Qualcomm display clock control module provides the clocks, resets and power
15
-
domains on SM8650.
16
-
17
-
See also:: include/dt-bindings/clock/qcom,sm8650-dispcc.h
18
-
19
-
properties:
20
-
compatible:
21
-
enum:
22
-
- qcom,sm8650-dispcc
23
-
24
-
clocks:
25
-
items:
26
-
- description: Board XO source
27
-
- description: Board Always On XO source
28
-
- description: Display's AHB clock
29
-
- description: sleep clock
30
-
- description: Byte clock from DSI PHY0
31
-
- description: Pixel clock from DSI PHY0
32
-
- description: Byte clock from DSI PHY1
33
-
- description: Pixel clock from DSI PHY1
34
-
- description: Link clock from DP PHY0
35
-
- description: VCO DIV clock from DP PHY0
36
-
- description: Link clock from DP PHY1
37
-
- description: VCO DIV clock from DP PHY1
38
-
- description: Link clock from DP PHY2
39
-
- description: VCO DIV clock from DP PHY2
40
-
- description: Link clock from DP PHY3
41
-
- description: VCO DIV clock from DP PHY3
42
-
43
-
'#clock-cells':
44
-
const: 1
45
-
46
-
'#reset-cells':
47
-
const: 1
48
-
49
-
'#power-domain-cells':
50
-
const: 1
51
-
52
-
reg:
53
-
maxItems: 1
54
-
55
-
power-domains:
56
-
description:
57
-
A phandle and PM domain specifier for the MMCX power domain.
58
-
maxItems: 1
59
-
60
-
required-opps:
61
-
description:
62
-
A phandle to an OPP node describing required MMCX performance point.
63
-
maxItems: 1
64
-
65
-
required:
66
-
- compatible
67
-
- reg
68
-
- clocks
69
-
- '#clock-cells'
70
-
- '#reset-cells'
71
-
- '#power-domain-cells'
72
-
73
-
additionalProperties: false
74
-
75
-
examples:
76
-
- |
77
-
#include <dt-bindings/clock/qcom,sm8650-gcc.h>
78
-
#include <dt-bindings/clock/qcom,rpmh.h>
79
-
#include <dt-bindings/power/qcom-rpmpd.h>
80
-
#include <dt-bindings/power/qcom,rpmhpd.h>
81
-
clock-controller@af00000 {
82
-
compatible = "qcom,sm8650-dispcc";
83
-
reg = <0x0af00000 0x10000>;
84
-
clocks = <&rpmhcc RPMH_CXO_CLK>,
85
-
<&rpmhcc RPMH_CXO_CLK_A>,
86
-
<&gcc GCC_DISP_AHB_CLK>,
87
-
<&sleep_clk>,
88
-
<&dsi0_phy 0>,
89
-
<&dsi0_phy 1>,
90
-
<&dsi1_phy 0>,
91
-
<&dsi1_phy 1>,
92
-
<&dp0_phy 0>,
93
-
<&dp0_phy 1>,
94
-
<&dp1_phy 0>,
95
-
<&dp1_phy 1>,
96
-
<&dp2_phy 0>,
97
-
<&dp2_phy 1>,
98
-
<&dp3_phy 0>,
99
-
<&dp3_phy 1>;
100
-
#clock-cells = <1>;
101
-
#reset-cells = <1>;
102
-
#power-domain-cells = <1>;
103
-
power-domains = <&rpmhpd RPMHPD_MMCX>;
104
-
required-opps = <&rpmhpd_opp_low_svs>;
105
-
};
106
-
...
+135
include/dt-bindings/clock/qcom,x1e80100-camcc.h
+135
include/dt-bindings/clock/qcom,x1e80100-camcc.h
···
1
+
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2
+
/*
3
+
* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
4
+
*/
5
+
6
+
#ifndef _DT_BINDINGS_CLK_QCOM_CAM_CC_X1E80100_H
7
+
#define _DT_BINDINGS_CLK_QCOM_CAM_CC_X1E80100_H
8
+
9
+
/* CAM_CC clocks */
10
+
#define CAM_CC_BPS_AHB_CLK 0
11
+
#define CAM_CC_BPS_CLK 1
12
+
#define CAM_CC_BPS_CLK_SRC 2
13
+
#define CAM_CC_BPS_FAST_AHB_CLK 3
14
+
#define CAM_CC_CAMNOC_AXI_NRT_CLK 4
15
+
#define CAM_CC_CAMNOC_AXI_RT_CLK 5
16
+
#define CAM_CC_CAMNOC_AXI_RT_CLK_SRC 6
17
+
#define CAM_CC_CAMNOC_DCD_XO_CLK 7
18
+
#define CAM_CC_CAMNOC_XO_CLK 8
19
+
#define CAM_CC_CCI_0_CLK 9
20
+
#define CAM_CC_CCI_0_CLK_SRC 10
21
+
#define CAM_CC_CCI_1_CLK 11
22
+
#define CAM_CC_CCI_1_CLK_SRC 12
23
+
#define CAM_CC_CORE_AHB_CLK 13
24
+
#define CAM_CC_CPAS_AHB_CLK 14
25
+
#define CAM_CC_CPAS_BPS_CLK 15
26
+
#define CAM_CC_CPAS_FAST_AHB_CLK 16
27
+
#define CAM_CC_CPAS_IFE_0_CLK 17
28
+
#define CAM_CC_CPAS_IFE_1_CLK 18
29
+
#define CAM_CC_CPAS_IFE_LITE_CLK 19
30
+
#define CAM_CC_CPAS_IPE_NPS_CLK 20
31
+
#define CAM_CC_CPAS_SFE_0_CLK 21
32
+
#define CAM_CC_CPHY_RX_CLK_SRC 22
33
+
#define CAM_CC_CSI0PHYTIMER_CLK 23
34
+
#define CAM_CC_CSI0PHYTIMER_CLK_SRC 24
35
+
#define CAM_CC_CSI1PHYTIMER_CLK 25
36
+
#define CAM_CC_CSI1PHYTIMER_CLK_SRC 26
37
+
#define CAM_CC_CSI2PHYTIMER_CLK 27
38
+
#define CAM_CC_CSI2PHYTIMER_CLK_SRC 28
39
+
#define CAM_CC_CSI3PHYTIMER_CLK 29
40
+
#define CAM_CC_CSI3PHYTIMER_CLK_SRC 30
41
+
#define CAM_CC_CSI4PHYTIMER_CLK 31
42
+
#define CAM_CC_CSI4PHYTIMER_CLK_SRC 32
43
+
#define CAM_CC_CSI5PHYTIMER_CLK 33
44
+
#define CAM_CC_CSI5PHYTIMER_CLK_SRC 34
45
+
#define CAM_CC_CSID_CLK 35
46
+
#define CAM_CC_CSID_CLK_SRC 36
47
+
#define CAM_CC_CSID_CSIPHY_RX_CLK 37
48
+
#define CAM_CC_CSIPHY0_CLK 38
49
+
#define CAM_CC_CSIPHY1_CLK 39
50
+
#define CAM_CC_CSIPHY2_CLK 40
51
+
#define CAM_CC_CSIPHY3_CLK 41
52
+
#define CAM_CC_CSIPHY4_CLK 42
53
+
#define CAM_CC_CSIPHY5_CLK 43
54
+
#define CAM_CC_FAST_AHB_CLK_SRC 44
55
+
#define CAM_CC_GDSC_CLK 45
56
+
#define CAM_CC_ICP_AHB_CLK 46
57
+
#define CAM_CC_ICP_CLK 47
58
+
#define CAM_CC_ICP_CLK_SRC 48
59
+
#define CAM_CC_IFE_0_CLK 49
60
+
#define CAM_CC_IFE_0_CLK_SRC 50
61
+
#define CAM_CC_IFE_0_DSP_CLK 51
62
+
#define CAM_CC_IFE_0_FAST_AHB_CLK 52
63
+
#define CAM_CC_IFE_1_CLK 53
64
+
#define CAM_CC_IFE_1_CLK_SRC 54
65
+
#define CAM_CC_IFE_1_DSP_CLK 55
66
+
#define CAM_CC_IFE_1_FAST_AHB_CLK 56
67
+
#define CAM_CC_IFE_LITE_AHB_CLK 57
68
+
#define CAM_CC_IFE_LITE_CLK 58
69
+
#define CAM_CC_IFE_LITE_CLK_SRC 59
70
+
#define CAM_CC_IFE_LITE_CPHY_RX_CLK 60
71
+
#define CAM_CC_IFE_LITE_CSID_CLK 61
72
+
#define CAM_CC_IFE_LITE_CSID_CLK_SRC 62
73
+
#define CAM_CC_IPE_NPS_AHB_CLK 63
74
+
#define CAM_CC_IPE_NPS_CLK 64
75
+
#define CAM_CC_IPE_NPS_CLK_SRC 65
76
+
#define CAM_CC_IPE_NPS_FAST_AHB_CLK 66
77
+
#define CAM_CC_IPE_PPS_CLK 67
78
+
#define CAM_CC_IPE_PPS_FAST_AHB_CLK 68
79
+
#define CAM_CC_JPEG_CLK 69
80
+
#define CAM_CC_JPEG_CLK_SRC 70
81
+
#define CAM_CC_MCLK0_CLK 71
82
+
#define CAM_CC_MCLK0_CLK_SRC 72
83
+
#define CAM_CC_MCLK1_CLK 73
84
+
#define CAM_CC_MCLK1_CLK_SRC 74
85
+
#define CAM_CC_MCLK2_CLK 75
86
+
#define CAM_CC_MCLK2_CLK_SRC 76
87
+
#define CAM_CC_MCLK3_CLK 77
88
+
#define CAM_CC_MCLK3_CLK_SRC 78
89
+
#define CAM_CC_MCLK4_CLK 79
90
+
#define CAM_CC_MCLK4_CLK_SRC 80
91
+
#define CAM_CC_MCLK5_CLK 81
92
+
#define CAM_CC_MCLK5_CLK_SRC 82
93
+
#define CAM_CC_MCLK6_CLK 83
94
+
#define CAM_CC_MCLK6_CLK_SRC 84
95
+
#define CAM_CC_MCLK7_CLK 85
96
+
#define CAM_CC_MCLK7_CLK_SRC 86
97
+
#define CAM_CC_PLL0 87
98
+
#define CAM_CC_PLL0_OUT_EVEN 88
99
+
#define CAM_CC_PLL0_OUT_ODD 89
100
+
#define CAM_CC_PLL1 90
101
+
#define CAM_CC_PLL1_OUT_EVEN 91
102
+
#define CAM_CC_PLL2 92
103
+
#define CAM_CC_PLL3 93
104
+
#define CAM_CC_PLL3_OUT_EVEN 94
105
+
#define CAM_CC_PLL4 95
106
+
#define CAM_CC_PLL4_OUT_EVEN 96
107
+
#define CAM_CC_PLL6 97
108
+
#define CAM_CC_PLL6_OUT_EVEN 98
109
+
#define CAM_CC_PLL8 99
110
+
#define CAM_CC_PLL8_OUT_EVEN 100
111
+
#define CAM_CC_SFE_0_CLK 101
112
+
#define CAM_CC_SFE_0_CLK_SRC 102
113
+
#define CAM_CC_SFE_0_FAST_AHB_CLK 103
114
+
#define CAM_CC_SLEEP_CLK 104
115
+
#define CAM_CC_SLEEP_CLK_SRC 105
116
+
#define CAM_CC_SLOW_AHB_CLK_SRC 106
117
+
#define CAM_CC_XO_CLK_SRC 107
118
+
119
+
/* CAM_CC power domains */
120
+
#define CAM_CC_BPS_GDSC 0
121
+
#define CAM_CC_IFE_0_GDSC 1
122
+
#define CAM_CC_IFE_1_GDSC 2
123
+
#define CAM_CC_IPE_0_GDSC 3
124
+
#define CAM_CC_SFE_0_GDSC 4
125
+
#define CAM_CC_TITAN_TOP_GDSC 5
126
+
127
+
/* CAM_CC resets */
128
+
#define CAM_CC_BPS_BCR 0
129
+
#define CAM_CC_ICP_BCR 1
130
+
#define CAM_CC_IFE_0_BCR 2
131
+
#define CAM_CC_IFE_1_BCR 3
132
+
#define CAM_CC_IPE_0_BCR 4
133
+
#define CAM_CC_SFE_0_BCR 5
134
+
135
+
#endif
+98
include/dt-bindings/clock/qcom,x1e80100-dispcc.h
+98
include/dt-bindings/clock/qcom,x1e80100-dispcc.h
···
1
+
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2
+
/*
3
+
* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
4
+
*/
5
+
6
+
#ifndef _DT_BINDINGS_CLK_QCOM_X1E80100_DISP_CC_H
7
+
#define _DT_BINDINGS_CLK_QCOM_X1E80100_DISP_CC_H
8
+
9
+
/* DISP_CC clocks */
10
+
#define DISP_CC_MDSS_ACCU_CLK 0
11
+
#define DISP_CC_MDSS_AHB1_CLK 1
12
+
#define DISP_CC_MDSS_AHB_CLK 2
13
+
#define DISP_CC_MDSS_AHB_CLK_SRC 3
14
+
#define DISP_CC_MDSS_BYTE0_CLK 4
15
+
#define DISP_CC_MDSS_BYTE0_CLK_SRC 5
16
+
#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 6
17
+
#define DISP_CC_MDSS_BYTE0_INTF_CLK 7
18
+
#define DISP_CC_MDSS_BYTE1_CLK 8
19
+
#define DISP_CC_MDSS_BYTE1_CLK_SRC 9
20
+
#define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC 10
21
+
#define DISP_CC_MDSS_BYTE1_INTF_CLK 11
22
+
#define DISP_CC_MDSS_DPTX0_AUX_CLK 12
23
+
#define DISP_CC_MDSS_DPTX0_AUX_CLK_SRC 13
24
+
#define DISP_CC_MDSS_DPTX0_LINK_CLK 14
25
+
#define DISP_CC_MDSS_DPTX0_LINK_CLK_SRC 15
26
+
#define DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC 16
27
+
#define DISP_CC_MDSS_DPTX0_LINK_INTF_CLK 17
28
+
#define DISP_CC_MDSS_DPTX0_PIXEL0_CLK 18
29
+
#define DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC 19
30
+
#define DISP_CC_MDSS_DPTX0_PIXEL1_CLK 20
31
+
#define DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC 21
32
+
#define DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK 22
33
+
#define DISP_CC_MDSS_DPTX1_AUX_CLK 23
34
+
#define DISP_CC_MDSS_DPTX1_AUX_CLK_SRC 24
35
+
#define DISP_CC_MDSS_DPTX1_LINK_CLK 25
36
+
#define DISP_CC_MDSS_DPTX1_LINK_CLK_SRC 26
37
+
#define DISP_CC_MDSS_DPTX1_LINK_DIV_CLK_SRC 27
38
+
#define DISP_CC_MDSS_DPTX1_LINK_INTF_CLK 28
39
+
#define DISP_CC_MDSS_DPTX1_PIXEL0_CLK 29
40
+
#define DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC 30
41
+
#define DISP_CC_MDSS_DPTX1_PIXEL1_CLK 31
42
+
#define DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC 32
43
+
#define DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK 33
44
+
#define DISP_CC_MDSS_DPTX2_AUX_CLK 34
45
+
#define DISP_CC_MDSS_DPTX2_AUX_CLK_SRC 35
46
+
#define DISP_CC_MDSS_DPTX2_LINK_CLK 36
47
+
#define DISP_CC_MDSS_DPTX2_LINK_CLK_SRC 37
48
+
#define DISP_CC_MDSS_DPTX2_LINK_DIV_CLK_SRC 38
49
+
#define DISP_CC_MDSS_DPTX2_LINK_INTF_CLK 39
50
+
#define DISP_CC_MDSS_DPTX2_PIXEL0_CLK 40
51
+
#define DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC 41
52
+
#define DISP_CC_MDSS_DPTX2_PIXEL1_CLK 42
53
+
#define DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC 43
54
+
#define DISP_CC_MDSS_DPTX2_USB_ROUTER_LINK_INTF_CLK 44
55
+
#define DISP_CC_MDSS_DPTX3_AUX_CLK 45
56
+
#define DISP_CC_MDSS_DPTX3_AUX_CLK_SRC 46
57
+
#define DISP_CC_MDSS_DPTX3_LINK_CLK 47
58
+
#define DISP_CC_MDSS_DPTX3_LINK_CLK_SRC 48
59
+
#define DISP_CC_MDSS_DPTX3_LINK_DIV_CLK_SRC 49
60
+
#define DISP_CC_MDSS_DPTX3_LINK_INTF_CLK 50
61
+
#define DISP_CC_MDSS_DPTX3_PIXEL0_CLK 51
62
+
#define DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC 52
63
+
#define DISP_CC_MDSS_ESC0_CLK 53
64
+
#define DISP_CC_MDSS_ESC0_CLK_SRC 54
65
+
#define DISP_CC_MDSS_ESC1_CLK 55
66
+
#define DISP_CC_MDSS_ESC1_CLK_SRC 56
67
+
#define DISP_CC_MDSS_MDP1_CLK 57
68
+
#define DISP_CC_MDSS_MDP_CLK 58
69
+
#define DISP_CC_MDSS_MDP_CLK_SRC 59
70
+
#define DISP_CC_MDSS_MDP_LUT1_CLK 60
71
+
#define DISP_CC_MDSS_MDP_LUT_CLK 61
72
+
#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 62
73
+
#define DISP_CC_MDSS_PCLK0_CLK 63
74
+
#define DISP_CC_MDSS_PCLK0_CLK_SRC 64
75
+
#define DISP_CC_MDSS_PCLK1_CLK 65
76
+
#define DISP_CC_MDSS_PCLK1_CLK_SRC 66
77
+
#define DISP_CC_MDSS_RSCC_AHB_CLK 67
78
+
#define DISP_CC_MDSS_RSCC_VSYNC_CLK 68
79
+
#define DISP_CC_MDSS_VSYNC1_CLK 69
80
+
#define DISP_CC_MDSS_VSYNC_CLK 70
81
+
#define DISP_CC_MDSS_VSYNC_CLK_SRC 71
82
+
#define DISP_CC_PLL0 72
83
+
#define DISP_CC_PLL1 73
84
+
#define DISP_CC_SLEEP_CLK 74
85
+
#define DISP_CC_SLEEP_CLK_SRC 75
86
+
#define DISP_CC_XO_CLK 76
87
+
#define DISP_CC_XO_CLK_SRC 77
88
+
89
+
/* DISP_CC resets */
90
+
#define DISP_CC_MDSS_CORE_BCR 0
91
+
#define DISP_CC_MDSS_CORE_INT2_BCR 1
92
+
#define DISP_CC_MDSS_RSCC_BCR 2
93
+
94
+
/* DISP_CC GDSCR */
95
+
#define MDSS_GDSC 0
96
+
#define MDSS_INT2_GDSC 1
97
+
98
+
#endif
+41
include/dt-bindings/clock/qcom,x1e80100-gpucc.h
+41
include/dt-bindings/clock/qcom,x1e80100-gpucc.h
···
1
+
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2
+
/*
3
+
* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
4
+
*/
5
+
6
+
#ifndef _DT_BINDINGS_CLK_QCOM_X1E80100_GPU_CC_H
7
+
#define _DT_BINDINGS_CLK_QCOM_X1E80100_GPU_CC_H
8
+
9
+
/* GPU_CC clocks */
10
+
#define GPU_CC_AHB_CLK 0
11
+
#define GPU_CC_CB_CLK 1
12
+
#define GPU_CC_CRC_AHB_CLK 2
13
+
#define GPU_CC_CX_FF_CLK 3
14
+
#define GPU_CC_CX_GMU_CLK 4
15
+
#define GPU_CC_CXO_AON_CLK 5
16
+
#define GPU_CC_CXO_CLK 6
17
+
#define GPU_CC_DEMET_CLK 7
18
+
#define GPU_CC_DEMET_DIV_CLK_SRC 8
19
+
#define GPU_CC_FF_CLK_SRC 9
20
+
#define GPU_CC_FREQ_MEASURE_CLK 10
21
+
#define GPU_CC_GMU_CLK_SRC 11
22
+
#define GPU_CC_GX_GMU_CLK 12
23
+
#define GPU_CC_GX_VSENSE_CLK 13
24
+
#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 14
25
+
#define GPU_CC_HUB_AON_CLK 15
26
+
#define GPU_CC_HUB_CLK_SRC 16
27
+
#define GPU_CC_HUB_CX_INT_CLK 17
28
+
#define GPU_CC_MEMNOC_GFX_CLK 18
29
+
#define GPU_CC_MND1X_0_GFX3D_CLK 19
30
+
#define GPU_CC_MND1X_1_GFX3D_CLK 20
31
+
#define GPU_CC_PLL0 21
32
+
#define GPU_CC_PLL1 22
33
+
#define GPU_CC_SLEEP_CLK 23
34
+
#define GPU_CC_XO_CLK_SRC 24
35
+
#define GPU_CC_XO_DIV_CLK_SRC 25
36
+
37
+
/* GDSCs */
38
+
#define GPU_CX_GDSC 0
39
+
#define GPU_GX_GDSC 1
40
+
41
+
#endif
+23
include/dt-bindings/clock/qcom,x1e80100-tcsr.h
+23
include/dt-bindings/clock/qcom,x1e80100-tcsr.h
···
1
+
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2
+
/*
3
+
* Copyright (c) 2023, Linaro Limited
4
+
*/
5
+
6
+
#ifndef _DT_BINDINGS_CLK_QCOM_X1E80100_TCSR_CC_H
7
+
#define _DT_BINDINGS_CLK_QCOM_X1E80100_TCSR_CC_H
8
+
9
+
/* TCSR CC clocks */
10
+
#define TCSR_PCIE_2L_4_CLKREF_EN 0
11
+
#define TCSR_PCIE_2L_5_CLKREF_EN 1
12
+
#define TCSR_PCIE_8L_CLKREF_EN 2
13
+
#define TCSR_USB3_MP0_CLKREF_EN 3
14
+
#define TCSR_USB3_MP1_CLKREF_EN 4
15
+
#define TCSR_USB2_1_CLKREF_EN 5
16
+
#define TCSR_UFS_PHY_CLKREF_EN 6
17
+
#define TCSR_USB4_1_CLKREF_EN 7
18
+
#define TCSR_USB4_2_CLKREF_EN 8
19
+
#define TCSR_USB2_2_CLKREF_EN 9
20
+
#define TCSR_PCIE_4L_CLKREF_EN 10
21
+
#define TCSR_EDP_CLKREF_EN 11
22
+
23
+
#endif
+19
include/dt-bindings/reset/qcom,x1e80100-gpucc.h
+19
include/dt-bindings/reset/qcom,x1e80100-gpucc.h
···
1
+
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2
+
/*
3
+
* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
4
+
*/
5
+
6
+
#ifndef _DT_BINDINGS_RESET_QCOM_X1E80100_GPU_CC_H
7
+
#define _DT_BINDINGS_RESET_QCOM_X1E80100_GPU_CC_H
8
+
9
+
#define GPUCC_GPU_CC_ACD_BCR 0
10
+
#define GPUCC_GPU_CC_CB_BCR 1
11
+
#define GPUCC_GPU_CC_CX_BCR 2
12
+
#define GPUCC_GPU_CC_FAST_HUB_BCR 3
13
+
#define GPUCC_GPU_CC_FF_BCR 4
14
+
#define GPUCC_GPU_CC_GFX3D_AON_BCR 5
15
+
#define GPUCC_GPU_CC_GMU_BCR 6
16
+
#define GPUCC_GPU_CC_GX_BCR 7
17
+
#define GPUCC_GPU_CC_XO_BCR 8
18
+
19
+
#endif