Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'kvm-updates/2.6.35' of git://git.kernel.org/pub/scm/virt/kvm/kvm
* 'kvm-updates/2.6.35' of git://git.kernel.org/pub/scm/virt/kvm/kvm:
KVM: read apic->irr with ioapic lock held
KVM: ia64: Add missing spin_unlock in kvm_arch_hardware_enable()
KVM: Fix order passed to iommu_unmap
KVM: MMU: Remove user access when allowing kernel access to gpte.w=0 page
KVM: MMU: invalidate and flush on spte small->large page size change
KVM: SVM: Implement workaround for Erratum 383
KVM: SVM: Handle MCEs early in the vmexit process
KVM: powerpc: fix init/exit annotation
+106
-4
+1
arch/ia64/kvm/kvm-ia64.c
+1
arch/ia64/kvm/kvm-ia64.c
+1
-1
arch/powerpc/kvm/e500.c
+1
-1
arch/powerpc/kvm/e500.c
+1
arch/x86/include/asm/msr-index.h
+1
arch/x86/include/asm/msr-index.h
···
110
110
#define MSR_AMD64_PATCH_LOADER 0xc0010020
111
111
#define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140
112
112
#define MSR_AMD64_OSVW_STATUS 0xc0010141
113
+
#define MSR_AMD64_DC_CFG 0xc0011022
113
114
#define MSR_AMD64_IBSFETCHCTL 0xc0011030
114
115
#define MSR_AMD64_IBSFETCHLINAD 0xc0011031
115
116
#define MSR_AMD64_IBSFETCHPHYSAD 0xc0011032
+5
arch/x86/kvm/mmu.c
+5
arch/x86/kvm/mmu.c
···
1815
1815
1816
1816
spte |= PT_WRITABLE_MASK;
1817
1817
1818
+
if (!tdp_enabled && !(pte_access & ACC_WRITE_MASK))
1819
+
spte &= ~PT_USER_MASK;
1820
+
1818
1821
/*
1819
1822
* Optimization: for pte sync, if spte was writable the hash
1820
1823
* lookup is unnecessary (and expensive). Write protection
···
1873
1870
1874
1871
child = page_header(pte & PT64_BASE_ADDR_MASK);
1875
1872
mmu_page_remove_parent_pte(child, sptep);
1873
+
__set_spte(sptep, shadow_trap_nonpresent_pte);
1874
+
kvm_flush_remote_tlbs(vcpu->kvm);
1876
1875
} else if (pfn != spte_to_pfn(*sptep)) {
1877
1876
pgprintk("hfn old %lx new %lx\n",
1878
1877
spte_to_pfn(*sptep), pfn);
+95
-1
arch/x86/kvm/svm.c
+95
-1
arch/x86/kvm/svm.c
···
28
28
#include <linux/ftrace_event.h>
29
29
#include <linux/slab.h>
30
30
31
+
#include <asm/tlbflush.h>
31
32
#include <asm/desc.h>
32
33
33
34
#include <asm/virtext.h>
···
56
55
#define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
57
56
58
57
#define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
58
+
59
+
static bool erratum_383_found __read_mostly;
59
60
60
61
static const u32 host_save_user_msrs[] = {
61
62
#ifdef CONFIG_X86_64
···
377
374
svm->vmcb->control.event_inj_err = error_code;
378
375
}
379
376
377
+
static void svm_init_erratum_383(void)
378
+
{
379
+
u32 low, high;
380
+
int err;
381
+
u64 val;
382
+
383
+
/* Only Fam10h is affected */
384
+
if (boot_cpu_data.x86 != 0x10)
385
+
return;
386
+
387
+
/* Use _safe variants to not break nested virtualization */
388
+
val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
389
+
if (err)
390
+
return;
391
+
392
+
val |= (1ULL << 47);
393
+
394
+
low = lower_32_bits(val);
395
+
high = upper_32_bits(val);
396
+
397
+
native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
398
+
399
+
erratum_383_found = true;
400
+
}
401
+
380
402
static int has_svm(void)
381
403
{
382
404
const char *msg;
···
456
428
wrmsrl(MSR_EFER, efer | EFER_SVME);
457
429
458
430
wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
431
+
432
+
svm_init_erratum_383();
459
433
460
434
return 0;
461
435
}
···
1440
1410
return 1;
1441
1411
}
1442
1412
1443
-
static int mc_interception(struct vcpu_svm *svm)
1413
+
static bool is_erratum_383(void)
1444
1414
{
1415
+
int err, i;
1416
+
u64 value;
1417
+
1418
+
if (!erratum_383_found)
1419
+
return false;
1420
+
1421
+
value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
1422
+
if (err)
1423
+
return false;
1424
+
1425
+
/* Bit 62 may or may not be set for this mce */
1426
+
value &= ~(1ULL << 62);
1427
+
1428
+
if (value != 0xb600000000010015ULL)
1429
+
return false;
1430
+
1431
+
/* Clear MCi_STATUS registers */
1432
+
for (i = 0; i < 6; ++i)
1433
+
native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
1434
+
1435
+
value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
1436
+
if (!err) {
1437
+
u32 low, high;
1438
+
1439
+
value &= ~(1ULL << 2);
1440
+
low = lower_32_bits(value);
1441
+
high = upper_32_bits(value);
1442
+
1443
+
native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
1444
+
}
1445
+
1446
+
/* Flush tlb to evict multi-match entries */
1447
+
__flush_tlb_all();
1448
+
1449
+
return true;
1450
+
}
1451
+
1452
+
static void svm_handle_mce(struct vcpu_svm *svm)
1453
+
{
1454
+
if (is_erratum_383()) {
1455
+
/*
1456
+
* Erratum 383 triggered. Guest state is corrupt so kill the
1457
+
* guest.
1458
+
*/
1459
+
pr_err("KVM: Guest triggered AMD Erratum 383\n");
1460
+
1461
+
set_bit(KVM_REQ_TRIPLE_FAULT, &svm->vcpu.requests);
1462
+
1463
+
return;
1464
+
}
1465
+
1445
1466
/*
1446
1467
* On an #MC intercept the MCE handler is not called automatically in
1447
1468
* the host. So do it by hand here.
···
1501
1420
"int $0x12\n");
1502
1421
/* not sure if we ever come back to this point */
1503
1422
1423
+
return;
1424
+
}
1425
+
1426
+
static int mc_interception(struct vcpu_svm *svm)
1427
+
{
1504
1428
return 1;
1505
1429
}
1506
1430
···
3174
3088
vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
3175
3089
vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
3176
3090
}
3091
+
3092
+
/*
3093
+
* We need to handle MC intercepts here before the vcpu has a chance to
3094
+
* change the physical cpu
3095
+
*/
3096
+
if (unlikely(svm->vmcb->control.exit_code ==
3097
+
SVM_EXIT_EXCP_BASE + MC_VECTOR))
3098
+
svm_handle_mce(svm);
3177
3099
}
3178
3100
3179
3101
#undef R
+2
-1
virt/kvm/ioapic.c
+2
-1
virt/kvm/ioapic.c
···
192
192
193
193
int kvm_ioapic_set_irq(struct kvm_ioapic *ioapic, int irq, int level)
194
194
{
195
-
u32 old_irr = ioapic->irr;
195
+
u32 old_irr;
196
196
u32 mask = 1 << irq;
197
197
union kvm_ioapic_redirect_entry entry;
198
198
int ret = 1;
199
199
200
200
spin_lock(&ioapic->lock);
201
+
old_irr = ioapic->irr;
201
202
if (irq >= 0 && irq < IOAPIC_NUM_PINS) {
202
203
entry = ioapic->redirtbl[irq];
203
204
level ^= entry.fields.polarity;
+1
-1
virt/kvm/iommu.c
+1
-1
virt/kvm/iommu.c
···
271
271
pfn = phys >> PAGE_SHIFT;
272
272
273
273
/* Unmap address from IO address space */
274
-
order = iommu_unmap(domain, gfn_to_gpa(gfn), PAGE_SIZE);
274
+
order = iommu_unmap(domain, gfn_to_gpa(gfn), 0);
275
275
unmap_pages = 1ULL << order;
276
276
277
277
/* Unpin all pages we just unmapped to not leak any memory */