Merge branch 'fixes' of master.kernel.org:/home/rmk/linux-2.6-arm

+17 -16

arch/arm/include/asm/io.h

··· 95 95 return (void __iomem *)addr; 96 96 } 97 97 98 + /* IO barriers */ 99 + #ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE 100 + #define __iormb() rmb() 101 + #define __iowmb() wmb() 102 + #else 103 + #define __iormb() do { } while (0) 104 + #define __iowmb() do { } while (0) 105 + #endif 106 + 98 107 /* 99 108 * Now, pick up the machine-defined IO definitions 100 109 */ ··· 134 125 * The {in,out}[bwl] macros are for emulating x86-style PCI/ISA IO space. 135 126 */ 136 127 #ifdef __io 137 - #define outb(v,p) __raw_writeb(v,__io(p)) 138 - #define outw(v,p) __raw_writew((__force __u16) \ 139 - cpu_to_le16(v),__io(p)) 140 - #define outl(v,p) __raw_writel((__force __u32) \ 141 - cpu_to_le32(v),__io(p)) 128 + #define outb(v,p) ({ __iowmb(); __raw_writeb(v,__io(p)); }) 129 + #define outw(v,p) ({ __iowmb(); __raw_writew((__force __u16) \ 130 + cpu_to_le16(v),__io(p)); }) 131 + #define outl(v,p) ({ __iowmb(); __raw_writel((__force __u32) \ 132 + cpu_to_le32(v),__io(p)); }) 142 133 143 - #define inb(p) ({ __u8 __v = __raw_readb(__io(p)); __v; }) 134 + #define inb(p) ({ __u8 __v = __raw_readb(__io(p)); __iormb(); __v; }) 144 135 #define inw(p) ({ __u16 __v = le16_to_cpu((__force __le16) \ 145 - __raw_readw(__io(p))); __v; }) 136 + __raw_readw(__io(p))); __iormb(); __v; }) 146 137 #define inl(p) ({ __u32 __v = le32_to_cpu((__force __le32) \ 147 - __raw_readl(__io(p))); __v; }) 138 + __raw_readl(__io(p))); __iormb(); __v; }) 148 139 149 140 #define outsb(p,d,l) __raw_writesb(__io(p),d,l) 150 141 #define outsw(p,d,l) __raw_writesw(__io(p),d,l) ··· 200 191 cpu_to_le16(v),__mem_pci(c))) 201 192 #define writel_relaxed(v,c) ((void)__raw_writel((__force u32) \ 202 193 cpu_to_le32(v),__mem_pci(c))) 203 - 204 - #ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE 205 - #define __iormb() rmb() 206 - #define __iowmb() wmb() 207 - #else 208 - #define __iormb() do { } while (0) 209 - #define __iowmb() do { } while (0) 210 - #endif 211 194 212 195 #define readb(c) ({ u8 __v = readb_relaxed(c); __iormb(); __v; }) 213 196 #define readw(c) ({ u16 __v = readw_relaxed(c); __iormb(); __v; })

+10 -12

arch/arm/kernel/head.S

··· 392 392 393 393 #ifdef CONFIG_SMP_ON_UP 394 394 __fixup_smp: 395 - mov r4, #0x00070000 396 - orr r3, r4, #0xff000000 @ mask 0xff070000 397 - orr r4, r4, #0x41000000 @ val 0x41070000 398 - and r0, r9, r3 399 - teq r0, r4 @ ARM CPU and ARMv6/v7? 395 + and r3, r9, #0x000f0000 @ architecture version 396 + teq r3, #0x000f0000 @ CPU ID supported? 400 397 bne __fixup_smp_on_up @ no, assume UP 401 398 402 - orr r3, r3, #0x0000ff00 403 - orr r3, r3, #0x000000f0 @ mask 0xff07fff0 399 + bic r3, r9, #0x00ff0000 400 + bic r3, r3, #0x0000000f @ mask 0xff00fff0 401 + mov r4, #0x41000000 404 402 orr r4, r4, #0x0000b000 405 - orr r4, r4, #0x00000020 @ val 0x4107b020 406 - and r0, r9, r3 407 - teq r0, r4 @ ARM 11MPCore? 403 + orr r4, r4, #0x00000020 @ val 0x4100b020 404 + teq r3, r4 @ ARM 11MPCore? 408 405 moveq pc, lr @ yes, assume SMP 409 406 410 407 mrc p15, 0, r0, c0, c0, 5 @ read MPIDR 411 - tst r0, #1 << 31 412 - movne pc, lr @ bit 31 => SMP 408 + and r0, r0, #0xc0000000 @ multiprocessing extensions and 409 + teq r0, #0x80000000 @ not part of a uniprocessor system? 410 + moveq pc, lr @ yes, assume SMP 413 411 414 412 __fixup_smp_on_up: 415 413 adr r0, 1f

+2 -2

arch/arm/mach-footbridge/include/mach/debug-macro.S

··· 17 17 /* For NetWinder debugging */ 18 18 .macro addruart, rp, rv 19 19 mov \rp, #0x000003f8 20 - orr \rv, \rp, #0x7c000000 @ physical 21 - orr \rp, \rp, #0xff000000 @ virtual 20 + orr \rv, \rp, #0xff000000 @ virtual 21 + orr \rp, \rp, #0x7c000000 @ physical 22 22 .endm 23 23 24 24 #define UART_SHIFT 0

+6

arch/arm/mm/init.c

··· 297 297 memblock_reserve(__pa(_stext), _end - _stext); 298 298 #endif 299 299 #ifdef CONFIG_BLK_DEV_INITRD 300 + if (phys_initrd_size && 301 + memblock_is_region_reserved(phys_initrd_start, phys_initrd_size)) { 302 + pr_err("INITRD: 0x%08lx+0x%08lx overlaps in-use memory region - disabling initrd\n", 303 + phys_initrd_start, phys_initrd_size); 304 + phys_initrd_start = phys_initrd_size = 0; 305 + } 300 306 if (phys_initrd_size) { 301 307 memblock_reserve(phys_initrd_start, phys_initrd_size); 302 308

+6 -5

drivers/mmc/host/mmci.c

··· 14 14 #include <linux/ioport.h> 15 15 #include <linux/device.h> 16 16 #include <linux/interrupt.h> 17 + #include <linux/kernel.h> 17 18 #include <linux/delay.h> 18 19 #include <linux/err.h> 19 20 #include <linux/highmem.h> ··· 284 283 u32 remain, success; 285 284 286 285 /* Calculate how far we are into the transfer */ 287 - remain = readl(host->base + MMCIDATACNT) << 2; 286 + remain = readl(host->base + MMCIDATACNT); 288 287 success = data->blksz * data->blocks - remain; 289 288 290 289 dev_dbg(mmc_dev(host->mmc), "MCI ERROR IRQ (status %08x)\n", status); 291 290 if (status & MCI_DATACRCFAIL) { 292 291 /* Last block was not successful */ 293 - host->data_xfered = ((success / data->blksz) - 1 * data->blksz); 292 + host->data_xfered = round_down(success - 1, data->blksz); 294 293 data->error = -EILSEQ; 295 294 } else if (status & MCI_DATATIMEOUT) { 296 - host->data_xfered = success; 295 + host->data_xfered = round_down(success, data->blksz); 297 296 data->error = -ETIMEDOUT; 298 297 } else if (status & (MCI_TXUNDERRUN|MCI_RXOVERRUN)) { 299 - host->data_xfered = success; 298 + host->data_xfered = round_down(success, data->blksz); 300 299 data->error = -EIO; 301 300 } 302 301 ··· 320 319 if (status & MCI_DATABLOCKEND) 321 320 dev_err(mmc_dev(host->mmc), "stray MCI_DATABLOCKEND interrupt\n"); 322 321 323 - if (status & MCI_DATAEND) { 322 + if (status & MCI_DATAEND || data->error) { 324 323 mmci_stop_data(host); 325 324 326 325 if (!data->error)

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