Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/i915/display: update to plane_wm register access function
Future platforms can have new additions in the plane_wm
registers. So update skl_wm_level_from_reg_val() to have
possiblity for such platform differentiations. This is in
preparation for the rest of the patches in this series where
hw support for the minimum and interim ddb allocations for
async flip is added. Replace all the i915 uses to intel_display
in this function while updating this function
Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20241121112726.510220-2-vinod.govindapillai@intel.com
+16
-16
+16
-16
drivers/gpu/drm/i915/display/skl_watermark.c
+16
-16
drivers/gpu/drm/i915/display/skl_watermark.c
···
2938
2938
return 0;
2939
2939
}
2940
2940
2941
-
static void skl_wm_level_from_reg_val(u32 val, struct skl_wm_level *level)
2941
+
static void skl_wm_level_from_reg_val(struct intel_display *display,
2942
+
u32 val, struct skl_wm_level *level)
2942
2943
{
2943
2944
level->enable = val & PLANE_WM_EN;
2944
2945
level->ignore_lines = val & PLANE_WM_IGNORE_LINES;
···
2951
2950
struct skl_pipe_wm *out)
2952
2951
{
2953
2952
struct intel_display *display = to_intel_display(crtc);
2954
-
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
2955
2953
enum pipe pipe = crtc->pipe;
2956
2954
enum plane_id plane_id;
2957
2955
int level;
···
2959
2959
for_each_plane_id_on_crtc(crtc, plane_id) {
2960
2960
struct skl_plane_wm *wm = &out->planes[plane_id];
2961
2961
2962
-
for (level = 0; level < i915->display.wm.num_levels; level++) {
2962
+
for (level = 0; level < display->wm.num_levels; level++) {
2963
2963
if (plane_id != PLANE_CURSOR)
2964
-
val = intel_de_read(i915, PLANE_WM(pipe, plane_id, level));
2964
+
val = intel_de_read(display, PLANE_WM(pipe, plane_id, level));
2965
2965
else
2966
-
val = intel_de_read(i915, CUR_WM(pipe, level));
2966
+
val = intel_de_read(display, CUR_WM(pipe, level));
2967
2967
2968
-
skl_wm_level_from_reg_val(val, &wm->wm[level]);
2968
+
skl_wm_level_from_reg_val(display, val, &wm->wm[level]);
2969
2969
}
2970
2970
2971
2971
if (plane_id != PLANE_CURSOR)
2972
-
val = intel_de_read(i915, PLANE_WM_TRANS(pipe, plane_id));
2972
+
val = intel_de_read(display, PLANE_WM_TRANS(pipe, plane_id));
2973
2973
else
2974
-
val = intel_de_read(i915, CUR_WM_TRANS(pipe));
2974
+
val = intel_de_read(display, CUR_WM_TRANS(pipe));
2975
2975
2976
-
skl_wm_level_from_reg_val(val, &wm->trans_wm);
2976
+
skl_wm_level_from_reg_val(display, val, &wm->trans_wm);
2977
2977
2978
2978
if (HAS_HW_SAGV_WM(display)) {
2979
2979
if (plane_id != PLANE_CURSOR)
2980
-
val = intel_de_read(i915, PLANE_WM_SAGV(pipe, plane_id));
2980
+
val = intel_de_read(display, PLANE_WM_SAGV(pipe, plane_id));
2981
2981
else
2982
-
val = intel_de_read(i915, CUR_WM_SAGV(pipe));
2982
+
val = intel_de_read(display, CUR_WM_SAGV(pipe));
2983
2983
2984
-
skl_wm_level_from_reg_val(val, &wm->sagv.wm0);
2984
+
skl_wm_level_from_reg_val(display, val, &wm->sagv.wm0);
2985
2985
2986
2986
if (plane_id != PLANE_CURSOR)
2987
-
val = intel_de_read(i915, PLANE_WM_SAGV_TRANS(pipe, plane_id));
2987
+
val = intel_de_read(display, PLANE_WM_SAGV_TRANS(pipe, plane_id));
2988
2988
else
2989
-
val = intel_de_read(i915, CUR_WM_SAGV_TRANS(pipe));
2989
+
val = intel_de_read(display, CUR_WM_SAGV_TRANS(pipe));
2990
2990
2991
-
skl_wm_level_from_reg_val(val, &wm->sagv.trans_wm);
2992
-
} else if (DISPLAY_VER(i915) >= 12) {
2991
+
skl_wm_level_from_reg_val(display, val, &wm->sagv.trans_wm);
2992
+
} else if (DISPLAY_VER(display) >= 12) {
2993
2993
wm->sagv.wm0 = wm->wm[0];
2994
2994
wm->sagv.trans_wm = wm->trans_wm;
2995
2995
}