Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'drm-fixes-2024-08-24' of https://gitlab.freedesktop.org/drm/kernel
Pull drm fixes from Dave Airlie:
"Weekly fixes. xe and msm are the major groups, with
amdgpu/i915/nouveau having smaller bits. xe has a bunch of hw
workaround fixes that were found to be missing, so that is why there
are a bunch of scattered fixes, and one larger one. But overall size
doesn't look too out of the ordinary.
msm:
- virtual plane fixes:
- drop yuv on hw where not supported
- csc vs yuv format fix
- rotation fix
- fix fb cleanup on close
- reset phy before link training
- fix visual corruption at 4K
- fix NULL ptr crash on hotplug
- simplify debug macros
- sc7180 fix
- adreno firmware name error path fix
amdgpu:
- GFX10 firmware loading fix
- SDMA 5.2 fix
- Debugfs parameter validation fix
- eGPU hotplug fix
i915:
- fix HDCP timeouts
nouveau:
- fix SG_DEBUG crash
xe:
- Fix OA format masks which were breaking build with gcc-5
- Fix opregion leak (Lucas)
- Fix OA sysfs entry (Ashutosh)
- Fix VM dma-resv lock (Brost)
- Fix tile fini sequence (Brost)
- Prevent UAF around preempt fence (Auld)
- Fix DGFX display suspend/resume (Maarten)
- Many Xe/Xe2 critical workarounds (Auld, Ngai-Mint, Bommu, Tejas, Daniele)
- Fix devm/drmm issues (Daniele)
- Fix missing workqueue destroy in xe_gt_pagefault (Stuart)
- Drop HW fence pointer to HW fence ctx (Brost)
- Free job before xe_exec_queue_put (Brost)"
* tag 'drm-fixes-2024-08-24' of https://gitlab.freedesktop.org/drm/kernel: (35 commits)
drm/xe: Free job before xe_exec_queue_put
drm/xe: Drop HW fence pointer to HW fence ctx
drm/xe: Fix missing workqueue destroy in xe_gt_pagefault
drm/amdgpu: fix eGPU hotplug regression
drm/amdgpu: Validate TA binary size
drm/amdgpu/sdma5.2: limit wptr workaround to sdma 5.2.1
drm/amdgpu: fixing rlc firmware loading failure issue
drm/xe/uc: Use devm to register cleanup that includes exec_queues
drm/xe: use devm instead of drmm for managed bo
drm/xe/xe2hpg: Add Wa_14021821874
drm/xe: fix WA 14018094691
drm/xe/xe2: Add Wa_15015404425
drm/xe/xe2: Make subsequent L2 flush sequential
drm/xe/xe2lpg: Extend workaround 14021402888
drm/xe/xe2lpm: Extend Wa_16021639441
drm/xe/bmg: implement Wa_16023588340
drm/xe/oa/uapi: Make bit masks unsigned
drm/xe/display: Make display suspend/resume work on discrete
drm/xe: prevent UAF around preempt fence
drm/xe: Fix tile fini sequence
...
+334
-90
+1
-1
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
+1
-1
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
+3
drivers/gpu/drm/amd/amdgpu/amdgpu_psp_ta.c
+3
drivers/gpu/drm/amd/amdgpu/amdgpu_psp_ta.c
+3
-2
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+3
-2
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
···
4116
4116
4117
4117
static int gfx_v10_0_init_microcode(struct amdgpu_device *adev)
4118
4118
{
4119
+
char fw_name[53];
4119
4120
char ucode_prefix[30];
4120
4121
const char *wks = "";
4121
4122
int err;
···
4150
4149
amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_CE);
4151
4150
4152
4151
if (!amdgpu_sriov_vf(adev)) {
4153
-
err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw,
4154
-
"amdgpu/%s_rlc.bin", ucode_prefix);
4152
+
snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", ucode_prefix);
4153
+
err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
4155
4154
if (err)
4156
4155
goto out;
4157
4156
+10
-8
drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
+10
-8
drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
···
176
176
DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
177
177
ring->doorbell_index, ring->wptr << 2);
178
178
WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
179
-
/* SDMA seems to miss doorbells sometimes when powergating kicks in.
180
-
* Updating the wptr directly will wake it. This is only safe because
181
-
* we disallow gfxoff in begin_use() and then allow it again in end_use().
182
-
*/
183
-
WREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR),
184
-
lower_32_bits(ring->wptr << 2));
185
-
WREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI),
186
-
upper_32_bits(ring->wptr << 2));
179
+
if (amdgpu_ip_version(adev, SDMA0_HWIP, 0) == IP_VERSION(5, 2, 1)) {
180
+
/* SDMA seems to miss doorbells sometimes when powergating kicks in.
181
+
* Updating the wptr directly will wake it. This is only safe because
182
+
* we disallow gfxoff in begin_use() and then allow it again in end_use().
183
+
*/
184
+
WREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR),
185
+
lower_32_bits(ring->wptr << 2));
186
+
WREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI),
187
+
upper_32_bits(ring->wptr << 2));
188
+
}
187
189
} else {
188
190
DRM_DEBUG("Not using doorbell -- "
189
191
"mmSDMA%i_GFX_RB_WPTR == 0x%08x "
+3
-1
drivers/gpu/drm/i915/display/intel_dp_hdcp.c
+3
-1
drivers/gpu/drm/i915/display/intel_dp_hdcp.c
···
39
39
static void intel_dp_hdcp_wait_for_cp_irq(struct intel_connector *connector,
40
40
int timeout)
41
41
{
42
-
struct intel_hdcp *hdcp = &connector->hdcp;
42
+
struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
43
+
struct intel_dp *dp = &dig_port->dp;
44
+
struct intel_hdcp *hdcp = &dp->attached_connector->hdcp;
43
45
long ret;
44
46
45
47
#define C (hdcp->cp_irq_count_cached != atomic_read(&hdcp->cp_irq_count))
+1
-1
drivers/gpu/drm/msm/adreno/adreno_gpu.c
+1
-1
drivers/gpu/drm/msm/adreno/adreno_gpu.c
+2
-2
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+2
-2
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
···
1171
1171
1172
1172
cstate->num_mixers = num_lm;
1173
1173
1174
-
dpu_enc->connector = conn_state->connector;
1175
-
1176
1174
for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1177
1175
struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
1178
1176
···
1267
1269
mutex_lock(&dpu_enc->enc_lock);
1268
1270
1269
1271
dpu_enc->commit_done_timedout = false;
1272
+
1273
+
dpu_enc->connector = drm_atomic_get_new_connector_for_encoder(state, drm_enc);
1270
1274
1271
1275
cur_mode = &dpu_enc->base.crtc->state->adjusted_mode;
1272
1276
+2
-2
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+2
-2
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
···
308
308
{ \
309
309
.maxdwnscale = SSPP_UNITY_SCALE, \
310
310
.maxupscale = SSPP_UNITY_SCALE, \
311
-
.format_list = plane_formats_yuv, \
312
-
.num_formats = ARRAY_SIZE(plane_formats_yuv), \
311
+
.format_list = plane_formats, \
312
+
.num_formats = ARRAY_SIZE(plane_formats), \
313
313
.virt_format_list = plane_formats, \
314
314
.virt_num_formats = ARRAY_SIZE(plane_formats), \
315
315
}
+2
-12
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
+2
-12
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
···
31
31
* @fmt: Pointer to format string
32
32
*/
33
33
#define DPU_DEBUG(fmt, ...) \
34
-
do { \
35
-
if (drm_debug_enabled(DRM_UT_KMS)) \
36
-
DRM_DEBUG(fmt, ##__VA_ARGS__); \
37
-
else \
38
-
pr_debug(fmt, ##__VA_ARGS__); \
39
-
} while (0)
34
+
DRM_DEBUG_DRIVER(fmt, ##__VA_ARGS__)
40
35
41
36
/**
42
37
* DPU_DEBUG_DRIVER - macro for hardware driver logging
43
38
* @fmt: Pointer to format string
44
39
*/
45
40
#define DPU_DEBUG_DRIVER(fmt, ...) \
46
-
do { \
47
-
if (drm_debug_enabled(DRM_UT_DRIVER)) \
48
-
DRM_ERROR(fmt, ##__VA_ARGS__); \
49
-
else \
50
-
pr_debug(fmt, ##__VA_ARGS__); \
51
-
} while (0)
41
+
DRM_DEBUG_DRIVER(fmt, ##__VA_ARGS__)
52
42
53
43
#define DPU_ERROR(fmt, ...) pr_err("[dpu error]" fmt, ##__VA_ARGS__)
54
44
#define DPU_ERROR_RATELIMITED(fmt, ...) pr_err_ratelimited("[dpu error]" fmt, ##__VA_ARGS__)
+17
-3
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
+17
-3
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
···
681
681
new_state->fb, &layout);
682
682
if (ret) {
683
683
DPU_ERROR_PLANE(pdpu, "failed to get format layout, %d\n", ret);
684
+
if (pstate->aspace)
685
+
msm_framebuffer_cleanup(new_state->fb, pstate->aspace,
686
+
pstate->needs_dirtyfb);
684
687
return ret;
685
688
}
686
689
···
747
744
min_src_size = MSM_FORMAT_IS_YUV(fmt) ? 2 : 1;
748
745
749
746
if (MSM_FORMAT_IS_YUV(fmt) &&
750
-
(!pipe->sspp->cap->sblk->scaler_blk.len ||
751
-
!pipe->sspp->cap->sblk->csc_blk.len)) {
747
+
!pipe->sspp->cap->sblk->csc_blk.len) {
752
748
DPU_DEBUG_PLANE(pdpu,
753
-
"plane doesn't have scaler/csc for yuv\n");
749
+
"plane doesn't have csc for yuv\n");
754
750
return -EINVAL;
755
751
}
756
752
···
866
864
867
865
max_linewidth = pdpu->catalog->caps->max_linewidth;
868
866
867
+
drm_rect_rotate(&pipe_cfg->src_rect,
868
+
new_plane_state->fb->width, new_plane_state->fb->height,
869
+
new_plane_state->rotation);
870
+
869
871
if ((drm_rect_width(&pipe_cfg->src_rect) > max_linewidth) ||
870
872
_dpu_plane_calc_clk(&crtc_state->adjusted_mode, pipe_cfg) > max_mdp_clk_rate) {
871
873
/*
···
918
912
r_pipe_cfg->src_rect.x1 = pipe_cfg->src_rect.x2;
919
913
r_pipe_cfg->dst_rect.x1 = pipe_cfg->dst_rect.x2;
920
914
}
915
+
916
+
drm_rect_rotate_inv(&pipe_cfg->src_rect,
917
+
new_plane_state->fb->width, new_plane_state->fb->height,
918
+
new_plane_state->rotation);
919
+
if (r_pipe->sspp)
920
+
drm_rect_rotate_inv(&r_pipe_cfg->src_rect,
921
+
new_plane_state->fb->width, new_plane_state->fb->height,
922
+
new_plane_state->rotation);
921
923
922
924
ret = dpu_plane_atomic_check_pipe(pdpu, pipe, pipe_cfg, fmt, &crtc_state->adjusted_mode);
923
925
if (ret)
+2
drivers/gpu/drm/msm/dp/dp_ctrl.c
+2
drivers/gpu/drm/msm/dp/dp_ctrl.c
···
1286
1286
link_info.rate = ctrl->link->link_params.rate;
1287
1287
link_info.capabilities = DP_LINK_CAP_ENHANCED_FRAMING;
1288
1288
1289
+
dp_link_reset_phy_params_vx_px(ctrl->link);
1290
+
1289
1291
dp_aux_link_configure(ctrl->aux, &link_info);
1290
1292
1291
1293
if (drm_dp_max_downspread(dpcd))
+10
-9
drivers/gpu/drm/msm/dp/dp_panel.c
+10
-9
drivers/gpu/drm/msm/dp/dp_panel.c
···
90
90
static u32 dp_panel_get_supported_bpp(struct dp_panel *dp_panel,
91
91
u32 mode_edid_bpp, u32 mode_pclk_khz)
92
92
{
93
-
struct dp_link_info *link_info;
93
+
const struct dp_link_info *link_info;
94
94
const u32 max_supported_bpp = 30, min_supported_bpp = 18;
95
-
u32 bpp = 0, data_rate_khz = 0;
95
+
u32 bpp, data_rate_khz;
96
96
97
-
bpp = min_t(u32, mode_edid_bpp, max_supported_bpp);
97
+
bpp = min(mode_edid_bpp, max_supported_bpp);
98
98
99
99
link_info = &dp_panel->link_info;
100
100
data_rate_khz = link_info->num_lanes * link_info->rate * 8;
101
101
102
-
while (bpp > min_supported_bpp) {
102
+
do {
103
103
if (mode_pclk_khz * bpp <= data_rate_khz)
104
-
break;
104
+
return bpp;
105
105
bpp -= 6;
106
-
}
106
+
} while (bpp > min_supported_bpp);
107
107
108
-
return bpp;
108
+
return min_supported_bpp;
109
109
}
110
110
111
111
int dp_panel_read_sink_caps(struct dp_panel *dp_panel,
···
423
423
drm_mode->clock);
424
424
drm_dbg_dp(panel->drm_dev, "bpp = %d\n", dp_panel->dp_mode.bpp);
425
425
426
-
dp_panel->dp_mode.bpp = max_t(u32, 18,
427
-
min_t(u32, dp_panel->dp_mode.bpp, 30));
426
+
dp_panel->dp_mode.bpp = dp_panel_get_mode_bpp(dp_panel, dp_panel->dp_mode.bpp,
427
+
dp_panel->dp_mode.drm_mode.clock);
428
+
428
429
drm_dbg_dp(panel->drm_dev, "updated bpp = %d\n",
429
430
dp_panel->dp_mode.bpp);
430
431
+1
-1
drivers/gpu/drm/msm/msm_mdss.c
+1
-1
drivers/gpu/drm/msm/msm_mdss.c
+6
-3
drivers/gpu/drm/nouveau/nvkm/core/firmware.c
+6
-3
drivers/gpu/drm/nouveau/nvkm/core/firmware.c
···
205
205
break;
206
206
case NVKM_FIRMWARE_IMG_DMA:
207
207
nvkm_memory_unref(&memory);
208
-
dma_free_coherent(fw->device->dev, sg_dma_len(&fw->mem.sgl), fw->img, fw->phys);
208
+
dma_free_noncoherent(fw->device->dev, sg_dma_len(&fw->mem.sgl),
209
+
fw->img, fw->phys, DMA_TO_DEVICE);
209
210
break;
210
211
case NVKM_FIRMWARE_IMG_SGT:
211
212
nvkm_memory_unref(&memory);
···
237
236
break;
238
237
case NVKM_FIRMWARE_IMG_DMA: {
239
238
dma_addr_t addr;
240
-
241
239
len = ALIGN(fw->len, PAGE_SIZE);
242
240
243
-
fw->img = dma_alloc_coherent(fw->device->dev, len, &addr, GFP_KERNEL);
241
+
fw->img = dma_alloc_noncoherent(fw->device->dev,
242
+
len, &addr,
243
+
DMA_TO_DEVICE,
244
+
GFP_KERNEL);
244
245
if (fw->img) {
245
246
memcpy(fw->img, src, fw->len);
246
247
fw->phys = addr;
+6
drivers/gpu/drm/nouveau/nvkm/falcon/fw.c
+6
drivers/gpu/drm/nouveau/nvkm/falcon/fw.c
···
89
89
nvkm_falcon_fw_dtor_sigs(fw);
90
90
}
91
91
92
+
/* after last write to the img, sync dma mappings */
93
+
dma_sync_single_for_device(fw->fw.device->dev,
94
+
fw->fw.phys,
95
+
sg_dma_len(&fw->fw.mem.sgl),
96
+
DMA_TO_DEVICE);
97
+
92
98
FLCNFW_DBG(fw, "resetting");
93
99
fw->func->reset(fw);
94
100
+2
drivers/gpu/drm/xe/Makefile
+2
drivers/gpu/drm/xe/Makefile
···
25
25
26
26
uses_generated_oob := \
27
27
$(obj)/xe_ggtt.o \
28
+
$(obj)/xe_device.o \
28
29
$(obj)/xe_gsc.o \
29
30
$(obj)/xe_gt.o \
30
31
$(obj)/xe_guc.o \
31
32
$(obj)/xe_guc_ads.o \
32
33
$(obj)/xe_guc_pc.o \
33
34
$(obj)/xe_migrate.o \
35
+
$(obj)/xe_pat.o \
34
36
$(obj)/xe_ring_ops.o \
35
37
$(obj)/xe_vm.o \
36
38
$(obj)/xe_wa.o \
+27
-1
drivers/gpu/drm/xe/display/xe_display.c
+27
-1
drivers/gpu/drm/xe/display/xe_display.c
···
132
132
return;
133
133
134
134
intel_display_driver_remove_noirq(xe);
135
+
intel_opregion_cleanup(xe);
135
136
}
136
137
137
138
int xe_display_init_noirq(struct xe_device *xe)
···
158
157
intel_display_device_info_runtime_init(xe);
159
158
160
159
err = intel_display_driver_probe_noirq(xe);
161
-
if (err)
160
+
if (err) {
161
+
intel_opregion_cleanup(xe);
162
162
return err;
163
+
}
163
164
164
165
return devm_add_action_or_reset(xe->drm.dev, xe_display_fini_noirq, xe);
165
166
}
···
283
280
return false;
284
281
}
285
282
283
+
static void xe_display_flush_cleanup_work(struct xe_device *xe)
284
+
{
285
+
struct intel_crtc *crtc;
286
+
287
+
for_each_intel_crtc(&xe->drm, crtc) {
288
+
struct drm_crtc_commit *commit;
289
+
290
+
spin_lock(&crtc->base.commit_lock);
291
+
commit = list_first_entry_or_null(&crtc->base.commit_list,
292
+
struct drm_crtc_commit, commit_entry);
293
+
if (commit)
294
+
drm_crtc_commit_get(commit);
295
+
spin_unlock(&crtc->base.commit_lock);
296
+
297
+
if (commit) {
298
+
wait_for_completion(&commit->cleanup_done);
299
+
drm_crtc_commit_put(commit);
300
+
}
301
+
}
302
+
}
303
+
286
304
void xe_display_pm_suspend(struct xe_device *xe, bool runtime)
287
305
{
288
306
bool s2idle = suspend_to_idle();
···
320
296
321
297
if (!runtime)
322
298
intel_display_driver_suspend(xe);
299
+
300
+
xe_display_flush_cleanup_work(xe);
323
301
324
302
intel_dp_mst_suspend(xe);
325
303
+8
drivers/gpu/drm/xe/display/xe_dsb_buffer.c
+8
drivers/gpu/drm/xe/display/xe_dsb_buffer.c
···
7
7
#include "intel_display_types.h"
8
8
#include "intel_dsb_buffer.h"
9
9
#include "xe_bo.h"
10
+
#include "xe_device.h"
11
+
#include "xe_device_types.h"
10
12
#include "xe_gt.h"
11
13
12
14
u32 intel_dsb_buffer_ggtt_offset(struct intel_dsb_buffer *dsb_buf)
···
18
16
19
17
void intel_dsb_buffer_write(struct intel_dsb_buffer *dsb_buf, u32 idx, u32 val)
20
18
{
19
+
struct xe_device *xe = dsb_buf->vma->bo->tile->xe;
20
+
21
21
iosys_map_wr(&dsb_buf->vma->bo->vmap, idx * 4, u32, val);
22
+
xe_device_l2_flush(xe);
22
23
}
23
24
24
25
u32 intel_dsb_buffer_read(struct intel_dsb_buffer *dsb_buf, u32 idx)
···
31
26
32
27
void intel_dsb_buffer_memset(struct intel_dsb_buffer *dsb_buf, u32 idx, u32 val, size_t size)
33
28
{
29
+
struct xe_device *xe = dsb_buf->vma->bo->tile->xe;
30
+
34
31
WARN_ON(idx > (dsb_buf->buf_size - size) / sizeof(*dsb_buf->cmd_buf));
35
32
36
33
iosys_map_memset(&dsb_buf->vma->bo->vmap, idx * 4, val, size);
34
+
xe_device_l2_flush(xe);
37
35
}
38
36
39
37
bool intel_dsb_buffer_create(struct intel_crtc *crtc, struct intel_dsb_buffer *dsb_buf, size_t size)
+3
drivers/gpu/drm/xe/display/xe_fb_pin.c
+3
drivers/gpu/drm/xe/display/xe_fb_pin.c
···
10
10
#include "intel_fb.h"
11
11
#include "intel_fb_pin.h"
12
12
#include "xe_bo.h"
13
+
#include "xe_device.h"
13
14
#include "xe_ggtt.h"
14
15
#include "xe_gt.h"
15
16
#include "xe_pm.h"
···
305
304
if (ret)
306
305
goto err_unpin;
307
306
307
+
/* Ensure DPT writes are flushed */
308
+
xe_device_l2_flush(xe);
308
309
return vma;
309
310
310
311
err_unpin:
+9
drivers/gpu/drm/xe/regs/xe_gt_regs.h
+9
drivers/gpu/drm/xe/regs/xe_gt_regs.h
···
80
80
#define LE_CACHEABILITY_MASK REG_GENMASK(1, 0)
81
81
#define LE_CACHEABILITY(value) REG_FIELD_PREP(LE_CACHEABILITY_MASK, value)
82
82
83
+
#define XE2_GAMREQSTRM_CTRL XE_REG(0x4194)
84
+
#define CG_DIS_CNTLBUS REG_BIT(6)
85
+
83
86
#define CCS_AUX_INV XE_REG(0x4208)
84
87
85
88
#define VD0_AUX_INV XE_REG(0x4218)
···
375
372
376
373
#define XEHPC_L3CLOS_MASK(i) XE_REG_MCR(0xb194 + (i) * 8)
377
374
375
+
#define XE2_GLOBAL_INVAL XE_REG(0xb404)
376
+
377
+
#define SCRATCH1LPFC XE_REG(0xb474)
378
+
#define EN_L3_RW_CCS_CACHE_FLUSH REG_BIT(0)
379
+
378
380
#define XE2LPM_L3SQCREG5 XE_REG_MCR(0xb658)
379
381
380
382
#define XE2_TDF_CTRL XE_REG(0xb418)
···
437
429
#define DIS_FIX_EOT1_FLUSH REG_BIT(9)
438
430
439
431
#define TDL_TSL_CHICKEN XE_REG_MCR(0xe4c4, XE_REG_OPTION_MASKED)
432
+
#define STK_ID_RESTRICT REG_BIT(12)
440
433
#define SLM_WMTP_RESTORE REG_BIT(11)
441
434
442
435
#define ROW_CHICKEN XE_REG_MCR(0xe4f0, XE_REG_OPTION_MASKED)
+3
-3
drivers/gpu/drm/xe/xe_bo.c
+3
-3
drivers/gpu/drm/xe/xe_bo.c
···
1575
1575
return bo;
1576
1576
}
1577
1577
1578
-
static void __xe_bo_unpin_map_no_vm(struct drm_device *drm, void *arg)
1578
+
static void __xe_bo_unpin_map_no_vm(void *arg)
1579
1579
{
1580
1580
xe_bo_unpin_map_no_vm(arg);
1581
1581
}
···
1590
1590
if (IS_ERR(bo))
1591
1591
return bo;
1592
1592
1593
-
ret = drmm_add_action_or_reset(&xe->drm, __xe_bo_unpin_map_no_vm, bo);
1593
+
ret = devm_add_action_or_reset(xe->drm.dev, __xe_bo_unpin_map_no_vm, bo);
1594
1594
if (ret)
1595
1595
return ERR_PTR(ret);
1596
1596
···
1638
1638
if (IS_ERR(bo))
1639
1639
return PTR_ERR(bo);
1640
1640
1641
-
drmm_release_action(&xe->drm, __xe_bo_unpin_map_no_vm, *src);
1641
+
devm_release_action(xe->drm.dev, __xe_bo_unpin_map_no_vm, *src);
1642
1642
*src = bo;
1643
1643
1644
1644
return 0;
+32
drivers/gpu/drm/xe/xe_device.c
+32
drivers/gpu/drm/xe/xe_device.c
···
54
54
#include "xe_vm.h"
55
55
#include "xe_vram.h"
56
56
#include "xe_wait_user_fence.h"
57
+
#include "xe_wa.h"
58
+
59
+
#include <generated/xe_wa_oob.h>
57
60
58
61
static int xe_file_open(struct drm_device *dev, struct drm_file *file)
59
62
{
···
823
820
if (!IS_DGFX(xe) || GRAPHICS_VER(xe) < 20)
824
821
return;
825
822
823
+
if (XE_WA(xe_root_mmio_gt(xe), 16023588340)) {
824
+
xe_device_l2_flush(xe);
825
+
return;
826
+
}
827
+
826
828
for_each_gt(gt, xe, id) {
827
829
if (xe_gt_is_media_type(gt))
828
830
continue;
···
849
841
850
842
xe_force_wake_put(gt_to_fw(gt), XE_FW_GT);
851
843
}
844
+
}
845
+
846
+
void xe_device_l2_flush(struct xe_device *xe)
847
+
{
848
+
struct xe_gt *gt;
849
+
int err;
850
+
851
+
gt = xe_root_mmio_gt(xe);
852
+
853
+
if (!XE_WA(gt, 16023588340))
854
+
return;
855
+
856
+
err = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT);
857
+
if (err)
858
+
return;
859
+
860
+
spin_lock(>->global_invl_lock);
861
+
xe_mmio_write32(gt, XE2_GLOBAL_INVAL, 0x1);
862
+
863
+
if (xe_mmio_wait32(gt, XE2_GLOBAL_INVAL, 0x1, 0x0, 150, NULL, true))
864
+
xe_gt_err_once(gt, "Global invalidation timeout\n");
865
+
spin_unlock(>->global_invl_lock);
866
+
867
+
xe_force_wake_put(gt_to_fw(gt), XE_FW_GT);
852
868
}
853
869
854
870
u32 xe_device_ccs_bytes(struct xe_device *xe, u64 size)
+1
drivers/gpu/drm/xe/xe_device.h
+1
drivers/gpu/drm/xe/xe_device.h
+14
-10
drivers/gpu/drm/xe/xe_exec_queue.c
+14
-10
drivers/gpu/drm/xe/xe_exec_queue.c
···
105
105
106
106
static int __xe_exec_queue_init(struct xe_exec_queue *q)
107
107
{
108
+
struct xe_vm *vm = q->vm;
108
109
int i, err;
110
+
111
+
if (vm) {
112
+
err = xe_vm_lock(vm, true);
113
+
if (err)
114
+
return err;
115
+
}
109
116
110
117
for (i = 0; i < q->width; ++i) {
111
118
q->lrc[i] = xe_lrc_create(q->hwe, q->vm, SZ_16K);
112
119
if (IS_ERR(q->lrc[i])) {
113
120
err = PTR_ERR(q->lrc[i]);
114
-
goto err_lrc;
121
+
goto err_unlock;
115
122
}
116
123
}
124
+
125
+
if (vm)
126
+
xe_vm_unlock(vm);
117
127
118
128
err = q->ops->init(q);
119
129
if (err)
···
131
121
132
122
return 0;
133
123
124
+
err_unlock:
125
+
if (vm)
126
+
xe_vm_unlock(vm);
134
127
err_lrc:
135
128
for (i = i - 1; i >= 0; --i)
136
129
xe_lrc_put(q->lrc[i]);
···
153
140
if (IS_ERR(q))
154
141
return q;
155
142
156
-
if (vm) {
157
-
err = xe_vm_lock(vm, true);
158
-
if (err)
159
-
goto err_post_alloc;
160
-
}
161
-
162
143
err = __xe_exec_queue_init(q);
163
-
if (vm)
164
-
xe_vm_unlock(vm);
165
144
if (err)
166
145
goto err_post_alloc;
167
146
···
643
638
644
639
if (xe_vm_in_preempt_fence_mode(vm)) {
645
640
q->lr.context = dma_fence_context_alloc(1);
646
-
spin_lock_init(&q->lr.lock);
647
641
648
642
err = xe_vm_add_compute_exec_queue(vm, q);
649
643
if (XE_IOCTL_DBG(xe, err))
-2
drivers/gpu/drm/xe/xe_exec_queue_types.h
-2
drivers/gpu/drm/xe/xe_exec_queue_types.h
+4
-4
drivers/gpu/drm/xe/xe_gsc.c
+4
-4
drivers/gpu/drm/xe/xe_gsc.c
···
260
260
struct xe_tile *tile = gt_to_tile(gt);
261
261
int ret;
262
262
263
-
if (XE_WA(gt, 14018094691)) {
263
+
if (XE_WA(tile->primary_gt, 14018094691)) {
264
264
ret = xe_force_wake_get(gt_to_fw(tile->primary_gt), XE_FORCEWAKE_ALL);
265
265
266
266
/*
···
278
278
279
279
ret = gsc_upload(gsc);
280
280
281
-
if (XE_WA(gt, 14018094691))
281
+
if (XE_WA(tile->primary_gt, 14018094691))
282
282
xe_force_wake_put(gt_to_fw(tile->primary_gt), XE_FORCEWAKE_ALL);
283
283
284
284
if (ret)
···
437
437
return ret;
438
438
}
439
439
440
-
static void free_resources(struct drm_device *drm, void *arg)
440
+
static void free_resources(void *arg)
441
441
{
442
442
struct xe_gsc *gsc = arg;
443
443
···
501
501
gsc->q = q;
502
502
gsc->wq = wq;
503
503
504
-
err = drmm_add_action_or_reset(&xe->drm, free_resources, gsc);
504
+
err = devm_add_action_or_reset(xe->drm.dev, free_resources, gsc);
505
505
if (err)
506
506
return err;
507
507
+55
drivers/gpu/drm/xe/xe_gt.c
+55
drivers/gpu/drm/xe/xe_gt.c
···
11
11
#include <drm/xe_drm.h>
12
12
#include <generated/xe_wa_oob.h>
13
13
14
+
#include <generated/xe_wa_oob.h>
15
+
14
16
#include "instructions/xe_gfxpipe_commands.h"
15
17
#include "instructions/xe_mi_commands.h"
16
18
#include "regs/xe_gt_regs.h"
···
97
95
gt->uc.guc.submission_state.enabled = false;
98
96
}
99
97
98
+
static void xe_gt_enable_host_l2_vram(struct xe_gt *gt)
99
+
{
100
+
u32 reg;
101
+
int err;
102
+
103
+
if (!XE_WA(gt, 16023588340))
104
+
return;
105
+
106
+
err = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT);
107
+
if (WARN_ON(err))
108
+
return;
109
+
110
+
if (!xe_gt_is_media_type(gt)) {
111
+
xe_mmio_write32(gt, SCRATCH1LPFC, EN_L3_RW_CCS_CACHE_FLUSH);
112
+
reg = xe_mmio_read32(gt, XE2_GAMREQSTRM_CTRL);
113
+
reg |= CG_DIS_CNTLBUS;
114
+
xe_mmio_write32(gt, XE2_GAMREQSTRM_CTRL, reg);
115
+
}
116
+
117
+
xe_gt_mcr_multicast_write(gt, XEHPC_L3CLOS_MASK(3), 0x3);
118
+
xe_force_wake_put(gt_to_fw(gt), XE_FW_GT);
119
+
}
120
+
121
+
static void xe_gt_disable_host_l2_vram(struct xe_gt *gt)
122
+
{
123
+
u32 reg;
124
+
int err;
125
+
126
+
if (!XE_WA(gt, 16023588340))
127
+
return;
128
+
129
+
if (xe_gt_is_media_type(gt))
130
+
return;
131
+
132
+
err = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT);
133
+
if (WARN_ON(err))
134
+
return;
135
+
136
+
reg = xe_mmio_read32(gt, XE2_GAMREQSTRM_CTRL);
137
+
reg &= ~CG_DIS_CNTLBUS;
138
+
xe_mmio_write32(gt, XE2_GAMREQSTRM_CTRL, reg);
139
+
140
+
xe_force_wake_put(gt_to_fw(gt), XE_FW_GT);
141
+
}
142
+
100
143
/**
101
144
* xe_gt_remove() - Clean up the GT structures before driver removal
102
145
* @gt: the GT object
···
158
111
159
112
for (i = 0; i < XE_ENGINE_CLASS_MAX; ++i)
160
113
xe_hw_fence_irq_finish(>->fence_irq[i]);
114
+
115
+
xe_gt_disable_host_l2_vram(gt);
161
116
}
162
117
163
118
static void gt_reset_worker(struct work_struct *w);
···
388
339
389
340
xe_force_wake_init_gt(gt, gt_to_fw(gt));
390
341
xe_pcode_init(gt);
342
+
spin_lock_init(>->global_invl_lock);
391
343
392
344
return 0;
393
345
}
···
558
508
559
509
xe_gt_mcr_init_early(gt);
560
510
xe_pat_init(gt);
511
+
xe_gt_enable_host_l2_vram(gt);
561
512
562
513
err = xe_uc_init(>->uc);
563
514
if (err)
···
693
642
return vf_gt_restart(gt);
694
643
695
644
xe_pat_init(gt);
645
+
646
+
xe_gt_enable_host_l2_vram(gt);
696
647
697
648
xe_gt_mcr_set_implicit_defaults(gt);
698
649
xe_reg_sr_apply_mmio(>->reg_sr, gt);
···
848
795
goto err_force_wake;
849
796
850
797
xe_gt_idle_disable_pg(gt);
798
+
799
+
xe_gt_disable_host_l2_vram(gt);
851
800
852
801
XE_WARN_ON(xe_force_wake_put(gt_to_fw(gt), XE_FORCEWAKE_ALL));
853
802
xe_gt_dbg(gt, "suspended\n");
+16
-2
drivers/gpu/drm/xe/xe_gt_pagefault.c
+16
-2
drivers/gpu/drm/xe/xe_gt_pagefault.c
···
382
382
383
383
static void acc_queue_work_func(struct work_struct *w);
384
384
385
+
static void pagefault_fini(void *arg)
386
+
{
387
+
struct xe_gt *gt = arg;
388
+
struct xe_device *xe = gt_to_xe(gt);
389
+
390
+
if (!xe->info.has_usm)
391
+
return;
392
+
393
+
destroy_workqueue(gt->usm.acc_wq);
394
+
destroy_workqueue(gt->usm.pf_wq);
395
+
}
396
+
385
397
int xe_gt_pagefault_init(struct xe_gt *gt)
386
398
{
387
399
struct xe_device *xe = gt_to_xe(gt);
···
421
409
gt->usm.acc_wq = alloc_workqueue("xe_gt_access_counter_work_queue",
422
410
WQ_UNBOUND | WQ_HIGHPRI,
423
411
NUM_ACC_QUEUE);
424
-
if (!gt->usm.acc_wq)
412
+
if (!gt->usm.acc_wq) {
413
+
destroy_workqueue(gt->usm.pf_wq);
425
414
return -ENOMEM;
415
+
}
426
416
427
-
return 0;
417
+
return devm_add_action_or_reset(xe->drm.dev, pagefault_fini, gt);
428
418
}
429
419
430
420
void xe_gt_pagefault_reset(struct xe_gt *gt)
+6
drivers/gpu/drm/xe/xe_gt_types.h
+6
drivers/gpu/drm/xe/xe_gt_types.h
···
362
362
*/
363
363
spinlock_t mcr_lock;
364
364
365
+
/**
366
+
* @global_invl_lock: protects the register for the duration
367
+
* of a global invalidation of l2 cache
368
+
*/
369
+
spinlock_t global_invl_lock;
370
+
365
371
/** @wa_active: keep track of active workarounds */
366
372
struct {
367
373
/** @wa_active.gt: bitmap with active GT workarounds */
+2
-2
drivers/gpu/drm/xe/xe_guc_submit.c
+2
-2
drivers/gpu/drm/xe/xe_guc_submit.c
···
284
284
free_submit_wq(guc);
285
285
}
286
286
287
-
static void guc_submit_wedged_fini(struct drm_device *drm, void *arg)
287
+
static void guc_submit_wedged_fini(void *arg)
288
288
{
289
289
struct xe_guc *guc = arg;
290
290
struct xe_exec_queue *q;
···
877
877
878
878
xe_gt_assert(guc_to_gt(guc), guc_to_xe(guc)->wedged.mode);
879
879
880
-
err = drmm_add_action_or_reset(&guc_to_xe(guc)->drm,
880
+
err = devm_add_action_or_reset(guc_to_xe(guc)->drm.dev,
881
881
guc_submit_wedged_fini, guc);
882
882
if (err) {
883
883
drm_err(&xe->drm, "Failed to register xe_guc_submit clean-up on wedged.mode=2. Although device is wedged.\n");
+5
-4
drivers/gpu/drm/xe/xe_hw_fence.c
+5
-4
drivers/gpu/drm/xe/xe_hw_fence.c
···
148
148
{
149
149
struct xe_hw_fence *fence = to_xe_hw_fence(dma_fence);
150
150
151
-
return dev_name(gt_to_xe(fence->ctx->gt)->drm.dev);
151
+
return dev_name(fence->xe->drm.dev);
152
152
}
153
153
154
154
static const char *xe_hw_fence_get_timeline_name(struct dma_fence *dma_fence)
155
155
{
156
156
struct xe_hw_fence *fence = to_xe_hw_fence(dma_fence);
157
157
158
-
return fence->ctx->name;
158
+
return fence->name;
159
159
}
160
160
161
161
static bool xe_hw_fence_signaled(struct dma_fence *dma_fence)
162
162
{
163
163
struct xe_hw_fence *fence = to_xe_hw_fence(dma_fence);
164
-
struct xe_device *xe = gt_to_xe(fence->ctx->gt);
164
+
struct xe_device *xe = fence->xe;
165
165
u32 seqno = xe_map_rd(xe, &fence->seqno_map, 0, u32);
166
166
167
167
return dma_fence->error ||
···
253
253
struct xe_hw_fence *hw_fence =
254
254
container_of(fence, typeof(*hw_fence), dma);
255
255
256
-
hw_fence->ctx = ctx;
256
+
hw_fence->xe = gt_to_xe(ctx->gt);
257
+
snprintf(hw_fence->name, sizeof(hw_fence->name), "%s", ctx->name);
257
258
hw_fence->seqno_map = seqno_map;
258
259
INIT_LIST_HEAD(&hw_fence->irq_link);
259
260
+5
-2
drivers/gpu/drm/xe/xe_hw_fence_types.h
+5
-2
drivers/gpu/drm/xe/xe_hw_fence_types.h
···
12
12
#include <linux/list.h>
13
13
#include <linux/spinlock.h>
14
14
15
+
struct xe_device;
15
16
struct xe_gt;
16
17
17
18
/**
···
62
61
struct xe_hw_fence {
63
62
/** @dma: base dma fence for hardware fence context */
64
63
struct dma_fence dma;
65
-
/** @ctx: hardware fence context */
66
-
struct xe_hw_fence_ctx *ctx;
64
+
/** @xe: Xe device for hw fence driver name */
65
+
struct xe_device *xe;
66
+
/** @name: name of hardware fence context */
67
+
char name[MAX_FENCE_NAME_LEN];
67
68
/** @seqno_map: I/O map for seqno */
68
69
struct iosys_map seqno_map;
69
70
/** @irq_link: Link in struct xe_hw_fence_irq.pending */
+27
-1
drivers/gpu/drm/xe/xe_mmio.c
+27
-1
drivers/gpu/drm/xe/xe_mmio.c
···
30
30
int id;
31
31
32
32
for_each_tile(tile, xe, id)
33
-
tile->mmio.regs = NULL;
33
+
if (tile != xe_device_get_root_tile(xe))
34
+
tile->mmio.regs = NULL;
34
35
}
35
36
36
37
int xe_mmio_probe_tiles(struct xe_device *xe)
···
92
91
static void mmio_fini(void *arg)
93
92
{
94
93
struct xe_device *xe = arg;
94
+
struct xe_tile *root_tile = xe_device_get_root_tile(xe);
95
95
96
96
pci_iounmap(to_pci_dev(xe->drm.dev), xe->mmio.regs);
97
97
xe->mmio.regs = NULL;
98
+
root_tile->mmio.regs = NULL;
98
99
}
99
100
100
101
int xe_mmio_init(struct xe_device *xe)
···
124
121
return devm_add_action_or_reset(xe->drm.dev, mmio_fini, xe);
125
122
}
126
123
124
+
static void mmio_flush_pending_writes(struct xe_gt *gt)
125
+
{
126
+
#define DUMMY_REG_OFFSET 0x130030
127
+
struct xe_tile *tile = gt_to_tile(gt);
128
+
int i;
129
+
130
+
if (tile->xe->info.platform != XE_LUNARLAKE)
131
+
return;
132
+
133
+
/* 4 dummy writes */
134
+
for (i = 0; i < 4; i++)
135
+
writel(0, tile->mmio.regs + DUMMY_REG_OFFSET);
136
+
}
137
+
127
138
u8 xe_mmio_read8(struct xe_gt *gt, struct xe_reg reg)
128
139
{
129
140
struct xe_tile *tile = gt_to_tile(gt);
130
141
u32 addr = xe_mmio_adjusted_addr(gt, reg.addr);
131
142
u8 val;
143
+
144
+
/* Wa_15015404425 */
145
+
mmio_flush_pending_writes(gt);
132
146
133
147
val = readb((reg.ext ? tile->mmio_ext.regs : tile->mmio.regs) + addr);
134
148
trace_xe_reg_rw(gt, false, addr, val, sizeof(val));
···
158
138
struct xe_tile *tile = gt_to_tile(gt);
159
139
u32 addr = xe_mmio_adjusted_addr(gt, reg.addr);
160
140
u16 val;
141
+
142
+
/* Wa_15015404425 */
143
+
mmio_flush_pending_writes(gt);
161
144
162
145
val = readw((reg.ext ? tile->mmio_ext.regs : tile->mmio.regs) + addr);
163
146
trace_xe_reg_rw(gt, false, addr, val, sizeof(val));
···
182
159
struct xe_tile *tile = gt_to_tile(gt);
183
160
u32 addr = xe_mmio_adjusted_addr(gt, reg.addr);
184
161
u32 val;
162
+
163
+
/* Wa_15015404425 */
164
+
mmio_flush_pending_writes(gt);
185
165
186
166
if (!reg.vf && IS_SRIOV_VF(gt_to_xe(gt)))
187
167
val = xe_gt_sriov_vf_read32(gt, reg);
-1
drivers/gpu/drm/xe/xe_observation.c
-1
drivers/gpu/drm/xe/xe_observation.c
+10
-1
drivers/gpu/drm/xe/xe_pat.c
+10
-1
drivers/gpu/drm/xe/xe_pat.c
···
7
7
8
8
#include <drm/xe_drm.h>
9
9
10
+
#include <generated/xe_wa_oob.h>
11
+
10
12
#include "regs/xe_reg_defs.h"
11
13
#include "xe_assert.h"
12
14
#include "xe_device.h"
···
17
15
#include "xe_gt_mcr.h"
18
16
#include "xe_mmio.h"
19
17
#include "xe_sriov.h"
18
+
#include "xe_wa.h"
20
19
21
20
#define _PAT_ATS 0x47fc
22
21
#define _PAT_INDEX(index) _PICK_EVEN_2RANGES(index, 8, \
···
385
382
if (GRAPHICS_VER(xe) == 20) {
386
383
xe->pat.ops = &xe2_pat_ops;
387
384
xe->pat.table = xe2_pat_table;
388
-
xe->pat.n_entries = ARRAY_SIZE(xe2_pat_table);
385
+
386
+
/* Wa_16023588340. XXX: Should use XE_WA */
387
+
if (GRAPHICS_VERx100(xe) == 2001)
388
+
xe->pat.n_entries = 28; /* Disable CLOS3 */
389
+
else
390
+
xe->pat.n_entries = ARRAY_SIZE(xe2_pat_table);
391
+
389
392
xe->pat.idx[XE_CACHE_NONE] = 3;
390
393
xe->pat.idx[XE_CACHE_WT] = 15;
391
394
xe->pat.idx[XE_CACHE_WB] = 2;
+6
-5
drivers/gpu/drm/xe/xe_pm.c
+6
-5
drivers/gpu/drm/xe/xe_pm.c
···
91
91
for_each_gt(gt, xe, id)
92
92
xe_gt_suspend_prepare(gt);
93
93
94
+
xe_display_pm_suspend(xe, false);
95
+
94
96
/* FIXME: Super racey... */
95
97
err = xe_bo_evict_all(xe);
96
98
if (err)
97
99
goto err;
98
-
99
-
xe_display_pm_suspend(xe, false);
100
100
101
101
for_each_gt(gt, xe, id) {
102
102
err = xe_gt_suspend(gt);
···
151
151
152
152
xe_irq_resume(xe);
153
153
154
-
xe_display_pm_resume(xe, false);
155
-
156
154
for_each_gt(gt, xe, id)
157
155
xe_gt_resume(gt);
156
+
157
+
xe_display_pm_resume(xe, false);
158
158
159
159
err = xe_bo_restore_user(xe);
160
160
if (err)
···
363
363
mutex_unlock(&xe->mem_access.vram_userfault.lock);
364
364
365
365
if (xe->d3cold.allowed) {
366
+
xe_display_pm_suspend(xe, true);
367
+
366
368
err = xe_bo_evict_all(xe);
367
369
if (err)
368
370
goto out;
369
-
xe_display_pm_suspend(xe, true);
370
371
}
371
372
372
373
for_each_gt(gt, xe, id) {
+2
-1
drivers/gpu/drm/xe/xe_preempt_fence.c
+2
-1
drivers/gpu/drm/xe/xe_preempt_fence.c
···
128
128
{
129
129
list_del_init(&pfence->link);
130
130
pfence->q = xe_exec_queue_get(q);
131
+
spin_lock_init(&pfence->lock);
131
132
dma_fence_init(&pfence->base, &preempt_fence_ops,
132
-
&q->lr.lock, context, seqno);
133
+
&pfence->lock, context, seqno);
133
134
134
135
return &pfence->base;
135
136
}
+2
drivers/gpu/drm/xe/xe_preempt_fence_types.h
+2
drivers/gpu/drm/xe/xe_preempt_fence_types.h
+2
-1
drivers/gpu/drm/xe/xe_sched_job.c
+2
-1
drivers/gpu/drm/xe/xe_sched_job.c
···
171
171
struct xe_sched_job *job =
172
172
container_of(ref, struct xe_sched_job, refcount);
173
173
struct xe_device *xe = job_to_xe(job);
174
+
struct xe_exec_queue *q = job->q;
174
175
175
176
xe_sched_job_free_fences(job);
176
-
xe_exec_queue_put(job->q);
177
177
dma_fence_put(job->fence);
178
178
drm_sched_job_cleanup(&job->drm);
179
179
job_free(job);
180
+
xe_exec_queue_put(q);
180
181
xe_pm_runtime_put(xe);
181
182
}
182
183
+1
-1
drivers/gpu/drm/xe/xe_trace.h
+1
-1
drivers/gpu/drm/xe/xe_trace.h
+18
drivers/gpu/drm/xe/xe_wa.c
+18
drivers/gpu/drm/xe/xe_wa.c
···
486
486
XE_RTP_RULES(GRAPHICS_VERSION(2004), FUNC(xe_rtp_match_first_render_or_compute)),
487
487
XE_RTP_ACTIONS(SET(TDL_TSL_CHICKEN, SLM_WMTP_RESTORE))
488
488
},
489
+
{ XE_RTP_NAME("14021402888"),
490
+
XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)),
491
+
XE_RTP_ACTIONS(SET(HALF_SLICE_CHICKEN7, CLEAR_OPTIMIZATION_DISABLE))
492
+
},
489
493
490
494
/* Xe2_HPG */
491
495
···
541
537
{ XE_RTP_NAME("14021402888"),
542
538
XE_RTP_RULES(GRAPHICS_VERSION(2001), ENGINE_CLASS(RENDER)),
543
539
XE_RTP_ACTIONS(SET(HALF_SLICE_CHICKEN7, CLEAR_OPTIMIZATION_DISABLE))
540
+
},
541
+
{ XE_RTP_NAME("14021821874"),
542
+
XE_RTP_RULES(GRAPHICS_VERSION(2001), FUNC(xe_rtp_match_first_render_or_compute)),
543
+
XE_RTP_ACTIONS(SET(TDL_TSL_CHICKEN, STK_ID_RESTRICT))
544
+
},
545
+
546
+
/* Xe2_LPM */
547
+
548
+
{ XE_RTP_NAME("16021639441"),
549
+
XE_RTP_RULES(MEDIA_VERSION(2000)),
550
+
XE_RTP_ACTIONS(SET(CSFE_CHICKEN1(0),
551
+
GHWSP_CSB_REPORT_DIS |
552
+
PPHWSP_CSB_AND_TIMESTAMP_REPORT_DIS,
553
+
XE_RTP_ACTION_FLAG(ENGINE_BASE)))
544
554
},
545
555
546
556
/* Xe2_HPM */
+1
drivers/gpu/drm/xe/xe_wa_oob.rules
+1
drivers/gpu/drm/xe/xe_wa_oob.rules
+4
-4
include/uapi/drm/xe_drm.h
+4
-4
include/uapi/drm/xe_drm.h
···
1590
1590
* b. Counter select c. Counter size and d. BC report. Also refer to the
1591
1591
* oa_formats array in drivers/gpu/drm/xe/xe_oa.c.
1592
1592
*/
1593
-
#define DRM_XE_OA_FORMAT_MASK_FMT_TYPE (0xff << 0)
1594
-
#define DRM_XE_OA_FORMAT_MASK_COUNTER_SEL (0xff << 8)
1595
-
#define DRM_XE_OA_FORMAT_MASK_COUNTER_SIZE (0xff << 16)
1596
-
#define DRM_XE_OA_FORMAT_MASK_BC_REPORT (0xff << 24)
1593
+
#define DRM_XE_OA_FORMAT_MASK_FMT_TYPE (0xffu << 0)
1594
+
#define DRM_XE_OA_FORMAT_MASK_COUNTER_SEL (0xffu << 8)
1595
+
#define DRM_XE_OA_FORMAT_MASK_COUNTER_SIZE (0xffu << 16)
1596
+
#define DRM_XE_OA_FORMAT_MASK_BC_REPORT (0xffu << 24)
1597
1597
1598
1598
/**
1599
1599
* @DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT: Requests periodic OA unit