Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'drm-fixes-for-v4.10-rc7' of git://people.freedesktop.org/~airlied/linux
Pull drm fixes from Dave Airlie:
"Another fixes pull for v4.10, it's a bit big due to the backport of
the VMA fixes for i915 that should fix the oops on shutdown problems
that you've worked around.
There are also two drm core connector registration fixes, a bunch of
nouveau regression fixes and two AMD fixes"
* tag 'drm-fixes-for-v4.10-rc7' of git://people.freedesktop.org/~airlied/linux:
drm/radeon: Fix vram_size/visible values in DRM_RADEON_GEM_INFO ioctl
drm/amdgpu/si: fix crash on headless asics
drm/i915: Track pinned vma in intel_plane_state
drm/atomic: Unconditionally call prepare_fb.
drm/atomic: Fix double free in drm_atomic_state_default_clear
drm/nouveau/kms/nv50: request vblank events for commits that send completion events
drm/nouveau/nv1a,nv1f/disp: fix memory clock rate retrieval
drm/nouveau/disp/gt215: Fix HDA ELD handling (thus, HDMI audio) on gt215
drm/nouveau/nouveau/led: prevent compiling the led-code if nouveau=y and leds=m
drm/nouveau/disp/mcp7x: disable dptmds workaround
drm/nouveau: prevent userspace from deleting client object
drm/nouveau/fence/g84-: protect against concurrent access to semaphore buffers
drm: Don't race connector registration
drm: prevent double-(un)registration for connectors
+171
-165
+3
-1
drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
+3
-1
drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
···
254
254
}
255
255
WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0);
256
256
257
+
if (adev->mode_info.num_crtc)
258
+
amdgpu_display_set_vga_render_state(adev, false);
259
+
257
260
gmc_v6_0_mc_stop(adev, &save);
258
261
259
262
if (gmc_v6_0_wait_for_idle((void *)adev)) {
···
286
283
dev_warn(adev->dev, "Wait for MC idle timedout !\n");
287
284
}
288
285
gmc_v6_0_mc_resume(adev, &save);
289
-
amdgpu_display_set_vga_render_state(adev, false);
290
286
}
291
287
292
288
static int gmc_v6_0_mc_init(struct amdgpu_device *adev)
+8
-5
drivers/gpu/drm/drm_atomic.c
+8
-5
drivers/gpu/drm/drm_atomic.c
···
2032
2032
}
2033
2033
2034
2034
for_each_crtc_in_state(state, crtc, crtc_state, i) {
2035
+
struct drm_pending_vblank_event *event = crtc_state->event;
2035
2036
/*
2036
-
* TEST_ONLY and PAGE_FLIP_EVENT are mutually
2037
-
* exclusive, if they weren't, this code should be
2038
-
* called on success for TEST_ONLY too.
2037
+
* Free the allocated event. drm_atomic_helper_setup_commit
2038
+
* can allocate an event too, so only free it if it's ours
2039
+
* to prevent a double free in drm_atomic_state_clear.
2039
2040
*/
2040
-
if (crtc_state->event)
2041
-
drm_event_cancel_free(dev, &crtc_state->event->base);
2041
+
if (event && (event->base.fence || event->base.file_priv)) {
2042
+
drm_event_cancel_free(dev, &event->base);
2043
+
crtc_state->event = NULL;
2044
+
}
2042
2045
}
2043
2046
2044
2047
if (!fence_state)
-9
drivers/gpu/drm/drm_atomic_helper.c
-9
drivers/gpu/drm/drm_atomic_helper.c
···
1666
1666
1667
1667
funcs = plane->helper_private;
1668
1668
1669
-
if (!drm_atomic_helper_framebuffer_changed(dev, state, plane_state->crtc))
1670
-
continue;
1671
-
1672
1669
if (funcs->prepare_fb) {
1673
1670
ret = funcs->prepare_fb(plane, plane_state);
1674
1671
if (ret)
···
1680
1683
const struct drm_plane_helper_funcs *funcs;
1681
1684
1682
1685
if (j >= i)
1683
-
continue;
1684
-
1685
-
if (!drm_atomic_helper_framebuffer_changed(dev, state, plane_state->crtc))
1686
1686
continue;
1687
1687
1688
1688
funcs = plane->helper_private;
···
1947
1953
1948
1954
for_each_plane_in_state(old_state, plane, plane_state, i) {
1949
1955
const struct drm_plane_helper_funcs *funcs;
1950
-
1951
-
if (!drm_atomic_helper_framebuffer_changed(dev, old_state, plane_state->crtc))
1952
-
continue;
1953
1956
1954
1957
funcs = plane->helper_private;
1955
1958
+18
-5
drivers/gpu/drm/drm_connector.c
+18
-5
drivers/gpu/drm/drm_connector.c
···
225
225
226
226
INIT_LIST_HEAD(&connector->probed_modes);
227
227
INIT_LIST_HEAD(&connector->modes);
228
+
mutex_init(&connector->mutex);
228
229
connector->edid_blob_ptr = NULL;
229
230
connector->status = connector_status_unknown;
230
231
···
360
359
connector->funcs->atomic_destroy_state(connector,
361
360
connector->state);
362
361
362
+
mutex_destroy(&connector->mutex);
363
+
363
364
memset(connector, 0, sizeof(*connector));
364
365
}
365
366
EXPORT_SYMBOL(drm_connector_cleanup);
···
377
374
*/
378
375
int drm_connector_register(struct drm_connector *connector)
379
376
{
380
-
int ret;
377
+
int ret = 0;
381
378
382
-
if (connector->registered)
379
+
if (!connector->dev->registered)
383
380
return 0;
381
+
382
+
mutex_lock(&connector->mutex);
383
+
if (connector->registered)
384
+
goto unlock;
384
385
385
386
ret = drm_sysfs_connector_add(connector);
386
387
if (ret)
387
-
return ret;
388
+
goto unlock;
388
389
389
390
ret = drm_debugfs_connector_add(connector);
390
391
if (ret) {
···
404
397
drm_mode_object_register(connector->dev, &connector->base);
405
398
406
399
connector->registered = true;
407
-
return 0;
400
+
goto unlock;
408
401
409
402
err_debugfs:
410
403
drm_debugfs_connector_remove(connector);
411
404
err_sysfs:
412
405
drm_sysfs_connector_remove(connector);
406
+
unlock:
407
+
mutex_unlock(&connector->mutex);
413
408
return ret;
414
409
}
415
410
EXPORT_SYMBOL(drm_connector_register);
···
424
415
*/
425
416
void drm_connector_unregister(struct drm_connector *connector)
426
417
{
427
-
if (!connector->registered)
418
+
mutex_lock(&connector->mutex);
419
+
if (!connector->registered) {
420
+
mutex_unlock(&connector->mutex);
428
421
return;
422
+
}
429
423
430
424
if (connector->funcs->early_unregister)
431
425
connector->funcs->early_unregister(connector);
···
437
425
drm_debugfs_connector_remove(connector);
438
426
439
427
connector->registered = false;
428
+
mutex_unlock(&connector->mutex);
440
429
}
441
430
EXPORT_SYMBOL(drm_connector_unregister);
442
431
+4
drivers/gpu/drm/drm_drv.c
+4
drivers/gpu/drm/drm_drv.c
···
745
745
if (ret)
746
746
goto err_minors;
747
747
748
+
dev->registered = true;
749
+
748
750
if (dev->driver->load) {
749
751
ret = dev->driver->load(dev, flags);
750
752
if (ret)
···
786
784
struct drm_map_list *r_list, *list_temp;
787
785
788
786
drm_lastclose(dev);
787
+
788
+
dev->registered = false;
789
789
790
790
if (drm_core_check_feature(dev, DRIVER_MODESET))
791
791
drm_modeset_unregister_all(dev);
+4
-12
drivers/gpu/drm/i915/i915_drv.h
+4
-12
drivers/gpu/drm/i915/i915_drv.h
···
1012
1012
struct work_struct underrun_work;
1013
1013
1014
1014
struct intel_fbc_state_cache {
1015
+
struct i915_vma *vma;
1016
+
1015
1017
struct {
1016
1018
unsigned int mode_flags;
1017
1019
uint32_t hsw_bdw_pixel_rate;
···
1027
1025
} plane;
1028
1026
1029
1027
struct {
1030
-
u64 ilk_ggtt_offset;
1031
1028
uint32_t pixel_format;
1032
1029
unsigned int stride;
1033
-
int fence_reg;
1034
-
unsigned int tiling_mode;
1035
1030
} fb;
1036
1031
} state_cache;
1037
1032
1038
1033
struct intel_fbc_reg_params {
1034
+
struct i915_vma *vma;
1035
+
1039
1036
struct {
1040
1037
enum pipe pipe;
1041
1038
enum plane plane;
···
1042
1041
} crtc;
1043
1042
1044
1043
struct {
1045
-
u64 ggtt_offset;
1046
1044
uint32_t pixel_format;
1047
1045
unsigned int stride;
1048
-
int fence_reg;
1049
1046
} fb;
1050
1047
1051
1048
int cfb_size;
···
3165
3166
const struct i915_ggtt_view *view)
3166
3167
{
3167
3168
return i915_gem_obj_to_vma(obj, &to_i915(obj->base.dev)->ggtt.base, view);
3168
-
}
3169
-
3170
-
static inline unsigned long
3171
-
i915_gem_object_ggtt_offset(struct drm_i915_gem_object *o,
3172
-
const struct i915_ggtt_view *view)
3173
-
{
3174
-
return i915_ggtt_offset(i915_gem_object_to_ggtt(o, view));
3175
3169
}
3176
3170
3177
3171
/* i915_gem_fence_reg.c */
+20
drivers/gpu/drm/i915/intel_atomic_plane.c
+20
drivers/gpu/drm/i915/intel_atomic_plane.c
···
85
85
86
86
__drm_atomic_helper_plane_duplicate_state(plane, state);
87
87
88
+
intel_state->vma = NULL;
89
+
88
90
return state;
89
91
}
90
92
···
102
100
intel_plane_destroy_state(struct drm_plane *plane,
103
101
struct drm_plane_state *state)
104
102
{
103
+
struct i915_vma *vma;
104
+
105
+
vma = fetch_and_zero(&to_intel_plane_state(state)->vma);
106
+
107
+
/*
108
+
* FIXME: Normally intel_cleanup_plane_fb handles destruction of vma.
109
+
* We currently don't clear all planes during driver unload, so we have
110
+
* to be able to unpin vma here for now.
111
+
*
112
+
* Normally this can only happen during unload when kmscon is disabled
113
+
* and userspace doesn't attempt to set a framebuffer at all.
114
+
*/
115
+
if (vma) {
116
+
mutex_lock(&plane->dev->struct_mutex);
117
+
intel_unpin_fb_vma(vma);
118
+
mutex_unlock(&plane->dev->struct_mutex);
119
+
}
120
+
105
121
drm_atomic_helper_plane_destroy_state(plane, state);
106
122
}
107
123
+42
-83
drivers/gpu/drm/i915/intel_display.c
+42
-83
drivers/gpu/drm/i915/intel_display.c
···
2235
2235
i915_vma_pin_fence(vma);
2236
2236
}
2237
2237
2238
+
i915_vma_get(vma);
2238
2239
err:
2239
2240
intel_runtime_pm_put(dev_priv);
2240
2241
return vma;
2241
2242
}
2242
2243
2243
-
void intel_unpin_fb_obj(struct drm_framebuffer *fb, unsigned int rotation)
2244
+
void intel_unpin_fb_vma(struct i915_vma *vma)
2244
2245
{
2245
-
struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2246
-
struct i915_ggtt_view view;
2247
-
struct i915_vma *vma;
2248
-
2249
-
WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2250
-
2251
-
intel_fill_fb_ggtt_view(&view, fb, rotation);
2252
-
vma = i915_gem_object_to_ggtt(obj, &view);
2246
+
lockdep_assert_held(&vma->vm->dev->struct_mutex);
2253
2247
2254
2248
if (WARN_ON_ONCE(!vma))
2255
2249
return;
2256
2250
2257
2251
i915_vma_unpin_fence(vma);
2258
2252
i915_gem_object_unpin_from_display_plane(vma);
2253
+
i915_vma_put(vma);
2259
2254
}
2260
2255
2261
2256
static int intel_fb_pitch(const struct drm_framebuffer *fb, int plane,
···
2745
2750
struct drm_device *dev = intel_crtc->base.dev;
2746
2751
struct drm_i915_private *dev_priv = to_i915(dev);
2747
2752
struct drm_crtc *c;
2748
-
struct intel_crtc *i;
2749
2753
struct drm_i915_gem_object *obj;
2750
2754
struct drm_plane *primary = intel_crtc->base.primary;
2751
2755
struct drm_plane_state *plane_state = primary->state;
···
2769
2775
* an fb with another CRTC instead
2770
2776
*/
2771
2777
for_each_crtc(dev, c) {
2772
-
i = to_intel_crtc(c);
2778
+
struct intel_plane_state *state;
2773
2779
2774
2780
if (c == &intel_crtc->base)
2775
2781
continue;
2776
2782
2777
-
if (!i->active)
2783
+
if (!to_intel_crtc(c)->active)
2778
2784
continue;
2779
2785
2780
-
fb = c->primary->fb;
2781
-
if (!fb)
2786
+
state = to_intel_plane_state(c->primary->state);
2787
+
if (!state->vma)
2782
2788
continue;
2783
2789
2784
-
obj = intel_fb_obj(fb);
2785
-
if (i915_gem_object_ggtt_offset(obj, NULL) == plane_config->base) {
2790
+
if (intel_plane_ggtt_offset(state) == plane_config->base) {
2791
+
fb = c->primary->fb;
2786
2792
drm_framebuffer_reference(fb);
2787
2793
goto valid_fb;
2788
2794
}
···
2803
2809
return;
2804
2810
2805
2811
valid_fb:
2812
+
mutex_lock(&dev->struct_mutex);
2813
+
intel_state->vma =
2814
+
intel_pin_and_fence_fb_obj(fb, primary->state->rotation);
2815
+
mutex_unlock(&dev->struct_mutex);
2816
+
if (IS_ERR(intel_state->vma)) {
2817
+
DRM_ERROR("failed to pin boot fb on pipe %d: %li\n",
2818
+
intel_crtc->pipe, PTR_ERR(intel_state->vma));
2819
+
2820
+
intel_state->vma = NULL;
2821
+
drm_framebuffer_unreference(fb);
2822
+
return;
2823
+
}
2824
+
2806
2825
plane_state->src_x = 0;
2807
2826
plane_state->src_y = 0;
2808
2827
plane_state->src_w = fb->width << 16;
···
3111
3104
I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
3112
3105
if (INTEL_GEN(dev_priv) >= 4) {
3113
3106
I915_WRITE(DSPSURF(plane),
3114
-
intel_fb_gtt_offset(fb, rotation) +
3107
+
intel_plane_ggtt_offset(plane_state) +
3115
3108
intel_crtc->dspaddr_offset);
3116
3109
I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
3117
3110
I915_WRITE(DSPLINOFF(plane), linear_offset);
3118
3111
} else {
3119
3112
I915_WRITE(DSPADDR(plane),
3120
-
intel_fb_gtt_offset(fb, rotation) +
3113
+
intel_plane_ggtt_offset(plane_state) +
3121
3114
intel_crtc->dspaddr_offset);
3122
3115
}
3123
3116
POSTING_READ(reg);
···
3214
3207
3215
3208
I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
3216
3209
I915_WRITE(DSPSURF(plane),
3217
-
intel_fb_gtt_offset(fb, rotation) +
3210
+
intel_plane_ggtt_offset(plane_state) +
3218
3211
intel_crtc->dspaddr_offset);
3219
3212
if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
3220
3213
I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
···
3235
3228
3236
3229
return intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
3237
3230
}
3238
-
}
3239
-
3240
-
u32 intel_fb_gtt_offset(struct drm_framebuffer *fb,
3241
-
unsigned int rotation)
3242
-
{
3243
-
struct drm_i915_gem_object *obj = intel_fb_obj(fb);
3244
-
struct i915_ggtt_view view;
3245
-
struct i915_vma *vma;
3246
-
3247
-
intel_fill_fb_ggtt_view(&view, fb, rotation);
3248
-
3249
-
vma = i915_gem_object_to_ggtt(obj, &view);
3250
-
if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n",
3251
-
view.type))
3252
-
return -1;
3253
-
3254
-
return i915_ggtt_offset(vma);
3255
3231
}
3256
3232
3257
3233
static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
···
3431
3441
}
3432
3442
3433
3443
I915_WRITE(PLANE_SURF(pipe, 0),
3434
-
intel_fb_gtt_offset(fb, rotation) + surf_addr);
3444
+
intel_plane_ggtt_offset(plane_state) + surf_addr);
3435
3445
3436
3446
POSTING_READ(PLANE_SURF(pipe, 0));
3437
3447
}
···
11526
11536
flush_work(&work->mmio_work);
11527
11537
11528
11538
mutex_lock(&dev->struct_mutex);
11529
-
intel_unpin_fb_obj(work->old_fb, primary->state->rotation);
11539
+
intel_unpin_fb_vma(work->old_vma);
11530
11540
i915_gem_object_put(work->pending_flip_obj);
11531
11541
mutex_unlock(&dev->struct_mutex);
11532
11542
···
12236
12246
goto cleanup_pending;
12237
12247
}
12238
12248
12239
-
work->gtt_offset = intel_fb_gtt_offset(fb, primary->state->rotation);
12240
-
work->gtt_offset += intel_crtc->dspaddr_offset;
12249
+
work->old_vma = to_intel_plane_state(primary->state)->vma;
12250
+
to_intel_plane_state(primary->state)->vma = vma;
12251
+
12252
+
work->gtt_offset = i915_ggtt_offset(vma) + intel_crtc->dspaddr_offset;
12241
12253
work->rotation = crtc->primary->state->rotation;
12242
12254
12243
12255
/*
···
12293
12301
cleanup_request:
12294
12302
i915_add_request_no_flush(request);
12295
12303
cleanup_unpin:
12296
-
intel_unpin_fb_obj(fb, crtc->primary->state->rotation);
12304
+
to_intel_plane_state(primary->state)->vma = work->old_vma;
12305
+
intel_unpin_fb_vma(vma);
12297
12306
cleanup_pending:
12298
12307
atomic_dec(&intel_crtc->unpin_work_count);
12299
12308
unlock:
···
14787
14794
DRM_DEBUG_KMS("failed to pin object\n");
14788
14795
return PTR_ERR(vma);
14789
14796
}
14797
+
14798
+
to_intel_plane_state(new_state)->vma = vma;
14790
14799
}
14791
14800
14792
14801
return 0;
···
14807
14812
intel_cleanup_plane_fb(struct drm_plane *plane,
14808
14813
struct drm_plane_state *old_state)
14809
14814
{
14810
-
struct drm_i915_private *dev_priv = to_i915(plane->dev);
14811
-
struct intel_plane_state *old_intel_state;
14812
-
struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb);
14813
-
struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb);
14815
+
struct i915_vma *vma;
14814
14816
14815
-
old_intel_state = to_intel_plane_state(old_state);
14816
-
14817
-
if (!obj && !old_obj)
14818
-
return;
14819
-
14820
-
if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR ||
14821
-
!INTEL_INFO(dev_priv)->cursor_needs_physical))
14822
-
intel_unpin_fb_obj(old_state->fb, old_state->rotation);
14817
+
/* Should only be called after a successful intel_prepare_plane_fb()! */
14818
+
vma = fetch_and_zero(&to_intel_plane_state(old_state)->vma);
14819
+
if (vma)
14820
+
intel_unpin_fb_vma(vma);
14823
14821
}
14824
14822
14825
14823
int
···
15154
15166
if (!obj)
15155
15167
addr = 0;
15156
15168
else if (!INTEL_INFO(dev_priv)->cursor_needs_physical)
15157
-
addr = i915_gem_object_ggtt_offset(obj, NULL);
15169
+
addr = intel_plane_ggtt_offset(state);
15158
15170
else
15159
15171
addr = obj->phys_handle->busaddr;
15160
15172
···
17054
17066
void intel_modeset_gem_init(struct drm_device *dev)
17055
17067
{
17056
17068
struct drm_i915_private *dev_priv = to_i915(dev);
17057
-
struct drm_crtc *c;
17058
-
struct drm_i915_gem_object *obj;
17059
17069
17060
17070
intel_init_gt_powersave(dev_priv);
17061
17071
17062
17072
intel_modeset_init_hw(dev);
17063
17073
17064
17074
intel_setup_overlay(dev_priv);
17065
-
17066
-
/*
17067
-
* Make sure any fbs we allocated at startup are properly
17068
-
* pinned & fenced. When we do the allocation it's too early
17069
-
* for this.
17070
-
*/
17071
-
for_each_crtc(dev, c) {
17072
-
struct i915_vma *vma;
17073
-
17074
-
obj = intel_fb_obj(c->primary->fb);
17075
-
if (obj == NULL)
17076
-
continue;
17077
-
17078
-
mutex_lock(&dev->struct_mutex);
17079
-
vma = intel_pin_and_fence_fb_obj(c->primary->fb,
17080
-
c->primary->state->rotation);
17081
-
mutex_unlock(&dev->struct_mutex);
17082
-
if (IS_ERR(vma)) {
17083
-
DRM_ERROR("failed to pin boot fb on pipe %d\n",
17084
-
to_intel_crtc(c)->pipe);
17085
-
drm_framebuffer_unreference(c->primary->fb);
17086
-
c->primary->fb = NULL;
17087
-
c->primary->crtc = c->primary->state->crtc = NULL;
17088
-
update_state_fb(c->primary);
17089
-
c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
17090
-
}
17091
-
}
17092
17075
}
17093
17076
17094
17077
int intel_connector_register(struct drm_connector *connector)
+7
-2
drivers/gpu/drm/i915/intel_drv.h
+7
-2
drivers/gpu/drm/i915/intel_drv.h
···
377
377
struct intel_plane_state {
378
378
struct drm_plane_state base;
379
379
struct drm_rect clip;
380
+
struct i915_vma *vma;
380
381
381
382
struct {
382
383
u32 offset;
···
1047
1046
struct work_struct mmio_work;
1048
1047
1049
1048
struct drm_crtc *crtc;
1049
+
struct i915_vma *old_vma;
1050
1050
struct drm_framebuffer *old_fb;
1051
1051
struct drm_i915_gem_object *pending_flip_obj;
1052
1052
struct drm_pending_vblank_event *event;
···
1275
1273
struct drm_modeset_acquire_ctx *ctx);
1276
1274
struct i915_vma *
1277
1275
intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, unsigned int rotation);
1278
-
void intel_unpin_fb_obj(struct drm_framebuffer *fb, unsigned int rotation);
1276
+
void intel_unpin_fb_vma(struct i915_vma *vma);
1279
1277
struct drm_framebuffer *
1280
1278
__intel_framebuffer_create(struct drm_device *dev,
1281
1279
struct drm_mode_fb_cmd2 *mode_cmd,
···
1364
1362
int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
1365
1363
int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state);
1366
1364
1367
-
u32 intel_fb_gtt_offset(struct drm_framebuffer *fb, unsigned int rotation);
1365
+
static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state *state)
1366
+
{
1367
+
return i915_ggtt_offset(state->vma);
1368
+
}
1368
1369
1369
1370
u32 skl_plane_ctl_format(uint32_t pixel_format);
1370
1371
u32 skl_plane_ctl_tiling(uint64_t fb_modifier);
+20
-32
drivers/gpu/drm/i915/intel_fbc.c
+20
-32
drivers/gpu/drm/i915/intel_fbc.c
···
173
173
if (IS_I945GM(dev_priv))
174
174
fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
175
175
fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
176
-
fbc_ctl |= params->fb.fence_reg;
176
+
fbc_ctl |= params->vma->fence->id;
177
177
I915_WRITE(FBC_CONTROL, fbc_ctl);
178
178
}
179
179
···
193
193
else
194
194
dpfc_ctl |= DPFC_CTL_LIMIT_1X;
195
195
196
-
if (params->fb.fence_reg != I915_FENCE_REG_NONE) {
197
-
dpfc_ctl |= DPFC_CTL_FENCE_EN | params->fb.fence_reg;
196
+
if (params->vma->fence) {
197
+
dpfc_ctl |= DPFC_CTL_FENCE_EN | params->vma->fence->id;
198
198
I915_WRITE(DPFC_FENCE_YOFF, params->crtc.fence_y_offset);
199
199
} else {
200
200
I915_WRITE(DPFC_FENCE_YOFF, 0);
···
251
251
break;
252
252
}
253
253
254
-
if (params->fb.fence_reg != I915_FENCE_REG_NONE) {
254
+
if (params->vma->fence) {
255
255
dpfc_ctl |= DPFC_CTL_FENCE_EN;
256
256
if (IS_GEN5(dev_priv))
257
-
dpfc_ctl |= params->fb.fence_reg;
257
+
dpfc_ctl |= params->vma->fence->id;
258
258
if (IS_GEN6(dev_priv)) {
259
259
I915_WRITE(SNB_DPFC_CTL_SA,
260
-
SNB_CPU_FENCE_ENABLE | params->fb.fence_reg);
260
+
SNB_CPU_FENCE_ENABLE |
261
+
params->vma->fence->id);
261
262
I915_WRITE(DPFC_CPU_FENCE_OFFSET,
262
263
params->crtc.fence_y_offset);
263
264
}
···
270
269
}
271
270
272
271
I915_WRITE(ILK_DPFC_FENCE_YOFF, params->crtc.fence_y_offset);
273
-
I915_WRITE(ILK_FBC_RT_BASE, params->fb.ggtt_offset | ILK_FBC_RT_VALID);
272
+
I915_WRITE(ILK_FBC_RT_BASE,
273
+
i915_ggtt_offset(params->vma) | ILK_FBC_RT_VALID);
274
274
/* enable it... */
275
275
I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
276
276
···
321
319
break;
322
320
}
323
321
324
-
if (params->fb.fence_reg != I915_FENCE_REG_NONE) {
322
+
if (params->vma->fence) {
325
323
dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN;
326
324
I915_WRITE(SNB_DPFC_CTL_SA,
327
-
SNB_CPU_FENCE_ENABLE | params->fb.fence_reg);
325
+
SNB_CPU_FENCE_ENABLE |
326
+
params->vma->fence->id);
328
327
I915_WRITE(DPFC_CPU_FENCE_OFFSET, params->crtc.fence_y_offset);
329
328
} else {
330
329
I915_WRITE(SNB_DPFC_CTL_SA,0);
···
730
727
return effective_w <= max_w && effective_h <= max_h;
731
728
}
732
729
733
-
/* XXX replace me when we have VMA tracking for intel_plane_state */
734
-
static int get_fence_id(struct drm_framebuffer *fb)
735
-
{
736
-
struct i915_vma *vma = i915_gem_object_to_ggtt(intel_fb_obj(fb), NULL);
737
-
738
-
return vma && vma->fence ? vma->fence->id : I915_FENCE_REG_NONE;
739
-
}
740
-
741
730
static void intel_fbc_update_state_cache(struct intel_crtc *crtc,
742
731
struct intel_crtc_state *crtc_state,
743
732
struct intel_plane_state *plane_state)
···
738
743
struct intel_fbc *fbc = &dev_priv->fbc;
739
744
struct intel_fbc_state_cache *cache = &fbc->state_cache;
740
745
struct drm_framebuffer *fb = plane_state->base.fb;
741
-
struct drm_i915_gem_object *obj;
746
+
747
+
cache->vma = NULL;
742
748
743
749
cache->crtc.mode_flags = crtc_state->base.adjusted_mode.flags;
744
750
if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
···
754
758
if (!cache->plane.visible)
755
759
return;
756
760
757
-
obj = intel_fb_obj(fb);
758
-
759
-
/* FIXME: We lack the proper locking here, so only run this on the
760
-
* platforms that need. */
761
-
if (IS_GEN(dev_priv, 5, 6))
762
-
cache->fb.ilk_ggtt_offset = i915_gem_object_ggtt_offset(obj, NULL);
763
761
cache->fb.pixel_format = fb->pixel_format;
764
762
cache->fb.stride = fb->pitches[0];
765
-
cache->fb.fence_reg = get_fence_id(fb);
766
-
cache->fb.tiling_mode = i915_gem_object_get_tiling(obj);
763
+
764
+
cache->vma = plane_state->vma;
767
765
}
768
766
769
767
static bool intel_fbc_can_activate(struct intel_crtc *crtc)
···
774
784
return false;
775
785
}
776
786
777
-
if (!cache->plane.visible) {
787
+
if (!cache->vma) {
778
788
fbc->no_fbc_reason = "primary plane not visible";
779
789
return false;
780
790
}
···
797
807
* so have no fence associated with it) due to aperture constaints
798
808
* at the time of pinning.
799
809
*/
800
-
if (cache->fb.tiling_mode != I915_TILING_X ||
801
-
cache->fb.fence_reg == I915_FENCE_REG_NONE) {
810
+
if (!cache->vma->fence) {
802
811
fbc->no_fbc_reason = "framebuffer not tiled or fenced";
803
812
return false;
804
813
}
···
877
888
* zero. */
878
889
memset(params, 0, sizeof(*params));
879
890
891
+
params->vma = cache->vma;
892
+
880
893
params->crtc.pipe = crtc->pipe;
881
894
params->crtc.plane = crtc->plane;
882
895
params->crtc.fence_y_offset = get_crtc_fence_y_offset(crtc);
883
896
884
897
params->fb.pixel_format = cache->fb.pixel_format;
885
898
params->fb.stride = cache->fb.stride;
886
-
params->fb.fence_reg = cache->fb.fence_reg;
887
899
888
900
params->cfb_size = intel_fbc_calculate_cfb_size(dev_priv, cache);
889
-
890
-
params->fb.ggtt_offset = cache->fb.ilk_ggtt_offset;
891
901
}
892
902
893
903
static bool intel_fbc_reg_params_equal(struct intel_fbc_reg_params *params1,
+2
-2
drivers/gpu/drm/i915/intel_fbdev.c
+2
-2
drivers/gpu/drm/i915/intel_fbdev.c
···
284
284
out_destroy_fbi:
285
285
drm_fb_helper_release_fbi(helper);
286
286
out_unpin:
287
-
intel_unpin_fb_obj(&ifbdev->fb->base, DRM_ROTATE_0);
287
+
intel_unpin_fb_vma(vma);
288
288
out_unlock:
289
289
mutex_unlock(&dev->struct_mutex);
290
290
return ret;
···
549
549
550
550
if (ifbdev->fb) {
551
551
mutex_lock(&ifbdev->helper.dev->struct_mutex);
552
-
intel_unpin_fb_obj(&ifbdev->fb->base, DRM_ROTATE_0);
552
+
intel_unpin_fb_vma(ifbdev->vma);
553
553
mutex_unlock(&ifbdev->helper.dev->struct_mutex);
554
554
555
555
drm_framebuffer_remove(&ifbdev->fb->base);
+4
-4
drivers/gpu/drm/i915/intel_sprite.c
+4
-4
drivers/gpu/drm/i915/intel_sprite.c
···
273
273
274
274
I915_WRITE(PLANE_CTL(pipe, plane), plane_ctl);
275
275
I915_WRITE(PLANE_SURF(pipe, plane),
276
-
intel_fb_gtt_offset(fb, rotation) + surf_addr);
276
+
intel_plane_ggtt_offset(plane_state) + surf_addr);
277
277
POSTING_READ(PLANE_SURF(pipe, plane));
278
278
}
279
279
···
458
458
I915_WRITE(SPSIZE(pipe, plane), (crtc_h << 16) | crtc_w);
459
459
I915_WRITE(SPCNTR(pipe, plane), sprctl);
460
460
I915_WRITE(SPSURF(pipe, plane),
461
-
intel_fb_gtt_offset(fb, rotation) + sprsurf_offset);
461
+
intel_plane_ggtt_offset(plane_state) + sprsurf_offset);
462
462
POSTING_READ(SPSURF(pipe, plane));
463
463
}
464
464
···
594
594
I915_WRITE(SPRSCALE(pipe), sprscale);
595
595
I915_WRITE(SPRCTL(pipe), sprctl);
596
596
I915_WRITE(SPRSURF(pipe),
597
-
intel_fb_gtt_offset(fb, rotation) + sprsurf_offset);
597
+
intel_plane_ggtt_offset(plane_state) + sprsurf_offset);
598
598
POSTING_READ(SPRSURF(pipe));
599
599
}
600
600
···
721
721
I915_WRITE(DVSSCALE(pipe), dvsscale);
722
722
I915_WRITE(DVSCNTR(pipe), dvscntr);
723
723
I915_WRITE(DVSSURF(pipe),
724
-
intel_fb_gtt_offset(fb, rotation) + dvssurf_offset);
724
+
intel_plane_ggtt_offset(plane_state) + dvssurf_offset);
725
725
POSTING_READ(DVSSURF(pipe));
726
726
}
727
727
+2
-1
drivers/gpu/drm/nouveau/dispnv04/hw.c
+2
-1
drivers/gpu/drm/nouveau/dispnv04/hw.c
···
222
222
uint32_t mpllP;
223
223
224
224
pci_read_config_dword(pci_get_bus_and_slot(0, 3), 0x6c, &mpllP);
225
+
mpllP = (mpllP >> 8) & 0xf;
225
226
if (!mpllP)
226
227
mpllP = 4;
227
228
···
233
232
uint32_t clock;
234
233
235
234
pci_read_config_dword(pci_get_bus_and_slot(0, 5), 0x4c, &clock);
236
-
return clock;
235
+
return clock / 1000;
237
236
}
238
237
239
238
ret = nouveau_hw_get_pllvals(dev, plltype, &pllvals);
+1
drivers/gpu/drm/nouveau/nouveau_fence.h
+1
drivers/gpu/drm/nouveau/nouveau_fence.h
+1
-1
drivers/gpu/drm/nouveau/nouveau_led.h
+1
-1
drivers/gpu/drm/nouveau/nouveau_led.h
+2
-1
drivers/gpu/drm/nouveau/nouveau_usif.c
+2
-1
drivers/gpu/drm/nouveau/nouveau_usif.c
···
313
313
if (!(ret = nvif_unpack(-ENOSYS, &data, &size, argv->v0, 0, 0, true))) {
314
314
/* block access to objects not created via this interface */
315
315
owner = argv->v0.owner;
316
-
if (argv->v0.object == 0ULL)
316
+
if (argv->v0.object == 0ULL &&
317
+
argv->v0.type != NVIF_IOCTL_V0_DEL)
317
318
argv->v0.owner = NVDRM_OBJECT_ANY; /* except client */
318
319
else
319
320
argv->v0.owner = NVDRM_OBJECT_USIF;
+6
drivers/gpu/drm/nouveau/nv50_display.c
+6
drivers/gpu/drm/nouveau/nv50_display.c
···
4052
4052
}
4053
4053
}
4054
4054
4055
+
for_each_crtc_in_state(state, crtc, crtc_state, i) {
4056
+
if (crtc->state->event)
4057
+
drm_crtc_vblank_get(crtc);
4058
+
}
4059
+
4055
4060
/* Update plane(s). */
4056
4061
for_each_plane_in_state(state, plane, plane_state, i) {
4057
4062
struct nv50_wndw_atom *asyw = nv50_wndw_atom(plane->state);
···
4106
4101
drm_crtc_send_vblank_event(crtc, crtc->state->event);
4107
4102
spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
4108
4103
crtc->state->event = NULL;
4104
+
drm_crtc_vblank_put(crtc);
4109
4105
}
4110
4106
}
4111
4107
+6
drivers/gpu/drm/nouveau/nv84_fence.c
+6
drivers/gpu/drm/nouveau/nv84_fence.c
···
107
107
struct nv84_fence_chan *fctx = chan->fence;
108
108
109
109
nouveau_bo_wr32(priv->bo, chan->chid * 16 / 4, fctx->base.sequence);
110
+
mutex_lock(&priv->mutex);
110
111
nouveau_bo_vma_del(priv->bo, &fctx->vma_gart);
111
112
nouveau_bo_vma_del(priv->bo, &fctx->vma);
113
+
mutex_unlock(&priv->mutex);
112
114
nouveau_fence_context_del(&fctx->base);
113
115
chan->fence = NULL;
114
116
nouveau_fence_context_free(&fctx->base);
···
136
134
fctx->base.sync32 = nv84_fence_sync32;
137
135
fctx->base.sequence = nv84_fence_read(chan);
138
136
137
+
mutex_lock(&priv->mutex);
139
138
ret = nouveau_bo_vma_add(priv->bo, cli->vm, &fctx->vma);
140
139
if (ret == 0) {
141
140
ret = nouveau_bo_vma_add(priv->bo_gart, cli->vm,
142
141
&fctx->vma_gart);
143
142
}
143
+
mutex_unlock(&priv->mutex);
144
144
145
145
if (ret)
146
146
nv84_fence_context_del(chan);
···
215
211
priv->base.contexts = fifo->nr;
216
212
priv->base.context_base = dma_fence_context_alloc(priv->base.contexts);
217
213
priv->base.uevent = true;
214
+
215
+
mutex_init(&priv->mutex);
218
216
219
217
/* Use VRAM if there is any ; otherwise fallback to system memory */
220
218
domain = drm->device.info.ram_size != 0 ? TTM_PL_FLAG_VRAM :
+1
-1
drivers/gpu/drm/nouveau/nvkm/engine/disp/hdagt215.c
+1
-1
drivers/gpu/drm/nouveau/nvkm/engine/disp/hdagt215.c
···
59
59
);
60
60
}
61
61
for (i = 0; i < size; i++)
62
-
nvkm_wr32(device, 0x61c440 + soff, (i << 8) | args->v0.data[0]);
62
+
nvkm_wr32(device, 0x61c440 + soff, (i << 8) | args->v0.data[i]);
63
63
for (; i < 0x60; i++)
64
64
nvkm_wr32(device, 0x61c440 + soff, (i << 8));
65
65
nvkm_mask(device, 0x61c448 + soff, 0x80000003, 0x80000003);
-2
drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c
-2
drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c
+2
-1
drivers/gpu/drm/radeon/radeon_drv.c
+2
-1
drivers/gpu/drm/radeon/radeon_drv.c
···
97
97
* 2.46.0 - Add PFP_SYNC_ME support on evergreen
98
98
* 2.47.0 - Add UVD_NO_OP register support
99
99
* 2.48.0 - TA_CS_BC_BASE_ADDR allowed on SI
100
+
* 2.49.0 - DRM_RADEON_GEM_INFO ioctl returns correct vram_size/visible values
100
101
*/
101
102
#define KMS_DRIVER_MAJOR 2
102
-
#define KMS_DRIVER_MINOR 48
103
+
#define KMS_DRIVER_MINOR 49
103
104
#define KMS_DRIVER_PATCHLEVEL 0
104
105
int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags);
105
106
int radeon_driver_unload_kms(struct drm_device *dev);
+2
-2
drivers/gpu/drm/radeon/radeon_gem.c
+2
-2
drivers/gpu/drm/radeon/radeon_gem.c
···
220
220
221
221
man = &rdev->mman.bdev.man[TTM_PL_VRAM];
222
222
223
-
args->vram_size = rdev->mc.real_vram_size;
224
-
args->vram_visible = (u64)man->size << PAGE_SHIFT;
223
+
args->vram_size = (u64)man->size << PAGE_SHIFT;
224
+
args->vram_visible = rdev->mc.visible_vram_size;
225
225
args->vram_visible -= rdev->vram_pin_size;
226
226
args->gart_size = rdev->mc.gtt_size;
227
227
args->gart_size -= rdev->gart_pin_size;
+1
include/drm/drmP.h
+1
include/drm/drmP.h
···
517
517
struct drm_minor *control; /**< Control node */
518
518
struct drm_minor *primary; /**< Primary node */
519
519
struct drm_minor *render; /**< Render node */
520
+
bool registered;
520
521
521
522
/* currently active master for this device. Protected by master_mutex */
522
523
struct drm_master *master;
+15
-1
include/drm/drm_connector.h
+15
-1
include/drm/drm_connector.h
···
381
381
* core drm connector interfaces. Everything added from this callback
382
382
* should be unregistered in the early_unregister callback.
383
383
*
384
+
* This is called while holding drm_connector->mutex.
385
+
*
384
386
* Returns:
385
387
*
386
388
* 0 on success, or a negative error code on failure.
···
397
395
* late_register(). It is called from drm_connector_unregister(),
398
396
* early in the driver unload sequence to disable userspace access
399
397
* before data structures are torndown.
398
+
*
399
+
* This is called while holding drm_connector->mutex.
400
400
*/
401
401
void (*early_unregister)(struct drm_connector *connector);
402
402
···
563
559
* @interlace_allowed: can this connector handle interlaced modes?
564
560
* @doublescan_allowed: can this connector handle doublescan?
565
561
* @stereo_allowed: can this connector handle stereo modes?
566
-
* @registered: is this connector exposed (registered) with userspace?
567
562
* @modes: modes available on this connector (from fill_modes() + user)
568
563
* @status: one of the drm_connector_status enums (connected, not, or unknown)
569
564
* @probed_modes: list of modes derived directly from the display
···
611
608
char *name;
612
609
613
610
/**
611
+
* @mutex: Lock for general connector state, but currently only protects
612
+
* @registered. Most of the connector state is still protected by the
613
+
* mutex in &drm_mode_config.
614
+
*/
615
+
struct mutex mutex;
616
+
617
+
/**
614
618
* @index: Compacted connector index, which matches the position inside
615
619
* the mode_config.list for drivers not supporting hot-add/removing. Can
616
620
* be used as an array index. It is invariant over the lifetime of the
···
630
620
bool interlace_allowed;
631
621
bool doublescan_allowed;
632
622
bool stereo_allowed;
623
+
/**
624
+
* @registered: Is this connector exposed (registered) with userspace?
625
+
* Protected by @mutex.
626
+
*/
633
627
bool registered;
634
628
struct list_head modes; /* list of modes on this connector */
635
629