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drm/amd/pm: add read arg support to smu_cmn_update_table

Extend the smu_cmn_update_table function to support reading a 32-bit return
argument from the SMU firmware during table transfer operations.

- Rename the original function to smu_cmn_update_table_read_arg
- Add a uint32_t *read_arg output parameter to capture firmware response
- Pass the read_arg pointer to the SMU message command
- Keep full backward compatibility using a macro wrapper for the old API

This allows the driver to retrieve status codes, results, or configuration
feedback from the SMU firmware after table data transfer.

No functional changes for existing users of the original smu_cmn_update_table()
API.

Signed-off-by: Yang Wang <kevinyang.wang@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Yang Wang and committed by
Alex Deucher 79d47bc4 25fd8095

+35 -17
+1
drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
··· 584 584 /* Message flags for smu_msg_args */ 585 585 #define SMU_MSG_FLAG_ASYNC BIT(0) /* Async send - skip post-poll */ 586 586 #define SMU_MSG_FLAG_LOCK_HELD BIT(1) /* Caller holds ctl->lock */ 587 + #define SMU_MSG_FLAG_FORCE_READ_ARG BIT(2) /* force read smu arg from pmfw */ 587 588 588 589 /* smu_msg_ctl flags */ 589 590 #define SMU_MSG_CTL_DEBUG_MAILBOX BIT(0) /* Debug mailbox supported */
+25 -12
drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
··· 496 496 } 497 497 498 498 /* Read output args */ 499 - if (ret == 0 && args->num_out_args > 0) { 499 + if ((ret == 0 || (args->flags & SMU_MSG_FLAG_FORCE_READ_ARG)) && 500 + args->num_out_args > 0) { 500 501 __smu_msg_v1_read_out_args(ctl, args); 501 502 dev_dbg(adev->dev, "smu send message: %s(%d) resp : 0x%08x", 502 503 smu_get_message_name(smu, args->msg), index, reg); ··· 1061 1060 return 0; 1062 1061 } 1063 1062 1064 - int smu_cmn_update_table(struct smu_context *smu, 1065 - enum smu_table_id table_index, 1066 - int argument, 1067 - void *table_data, 1068 - bool drv2smu) 1063 + int smu_cmn_update_table_read_arg(struct smu_context *smu, 1064 + enum smu_table_id table_index, 1065 + int argument, 1066 + void *table_data, 1067 + uint32_t *read_arg, 1068 + bool drv2smu) 1069 1069 { 1070 - struct smu_table_context *smu_table = &smu->smu_table; 1071 1070 struct amdgpu_device *adev = smu->adev; 1071 + struct smu_table_context *smu_table = &smu->smu_table; 1072 1072 struct smu_table *table = &smu_table->driver_table; 1073 + struct smu_msg_ctl *ctl = &smu->msg_ctl; 1074 + struct smu_msg_args args; 1073 1075 int table_id = smu_cmn_to_asic_specific_index(smu, 1074 1076 CMN2ASIC_MAPPING_TABLE, 1075 1077 table_index); 1076 1078 uint32_t table_size; 1077 1079 int ret = 0; 1080 + 1078 1081 if (!table_data || table_index >= SMU_TABLE_COUNT || table_id < 0) 1079 1082 return -EINVAL; 1080 1083 ··· 1093 1088 amdgpu_hdp_flush(adev, NULL); 1094 1089 } 1095 1090 1096 - ret = smu_cmn_send_smc_msg_with_param(smu, drv2smu ? 1097 - SMU_MSG_TransferTableDram2Smu : 1098 - SMU_MSG_TransferTableSmu2Dram, 1099 - table_id | ((argument & 0xFFFF) << 16), 1100 - NULL); 1091 + args.msg = drv2smu ? SMU_MSG_TransferTableDram2Smu : SMU_MSG_TransferTableSmu2Dram; 1092 + args.args[0] = ((argument & 0xFFFF) << 16) | (table_id & 0xffff); 1093 + args.num_args = 1; 1094 + args.out_args[0] = 0; 1095 + args.num_out_args = read_arg ? 1 : 0; 1096 + args.flags = read_arg ? SMU_MSG_FLAG_FORCE_READ_ARG : 0; 1097 + args.timeout = 0; 1098 + 1099 + ret = ctl->ops->send_msg(ctl, &args); 1100 + 1101 + if (read_arg) 1102 + *read_arg = args.out_args[0]; 1103 + 1101 1104 if (ret) 1102 1105 return ret; 1103 1106
+9 -5
drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h
··· 102 102 #define SMU_DPM_PCIE_GEN_IDX(gen) smu_cmn_dpm_pcie_gen_idx((gen)) 103 103 #define SMU_DPM_PCIE_WIDTH_IDX(width) smu_cmn_dpm_pcie_width_idx((width)) 104 104 105 + #define smu_cmn_update_table(smu, table_index, argument, table_data, drv2smu) \ 106 + smu_cmn_update_table_read_arg((smu), (table_index), (argument), (table_data), NULL, (drv2smu)) 107 + 105 108 extern const int link_speed[]; 106 109 107 110 /* Helper to Convert from PCIE Gen 1/2/3/4/5/6 to 0.1 GT/s speed units */ ··· 171 168 uint32_t *if_version, 172 169 uint32_t *smu_version); 173 170 174 - int smu_cmn_update_table(struct smu_context *smu, 175 - enum smu_table_id table_index, 176 - int argument, 177 - void *table_data, 178 - bool drv2smu); 171 + int smu_cmn_update_table_read_arg(struct smu_context *smu, 172 + enum smu_table_id table_index, 173 + int argument, 174 + void *table_data, 175 + uint32_t *read_arg, 176 + bool drv2smu); 179 177 180 178 int smu_cmn_vram_cpy(struct smu_context *smu, void *dst, 181 179 const void *src, size_t len);