Merge tag 'phy-fix-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy

+21 -8

Documentation/devicetree/bindings/phy/marvell,comphy-cp110.yaml

··· 47 47 const: 0 48 48 49 49 clocks: 50 + minItems: 1 50 51 maxItems: 3 51 - description: Reference clocks for CP110; MG clock, MG Core clock, AXI clock 52 52 53 53 clock-names: 54 - items: 55 - - const: mg_clk 56 - - const: mg_core_clk 57 - - const: axi_clk 54 + minItems: 1 55 + maxItems: 3 58 56 59 57 marvell,system-controller: 60 58 description: Phandle to the Marvell system controller (CP110 only) 61 59 $ref: /schemas/types.yaml#/definitions/phandle 62 60 63 61 patternProperties: 64 - '^phy@[0-2]$': 62 + '^phy@[0-5]$': 65 63 description: A COMPHY lane child node 66 64 type: object 67 65 additionalProperties: false ··· 67 69 properties: 68 70 reg: 69 71 description: COMPHY lane number 72 + maximum: 5 70 73 71 74 '#phy-cells': 72 75 const: 1 76 + 77 + connector: 78 + type: object 73 79 74 80 required: 75 81 - reg ··· 93 91 94 92 then: 95 93 properties: 96 - clocks: false 97 - clock-names: false 94 + clocks: 95 + maxItems: 1 96 + clock-names: 97 + const: xtal 98 98 99 99 required: 100 100 - reg-names 101 101 102 102 else: 103 + properties: 104 + clocks: 105 + minItems: 3 106 + clock-names: 107 + items: 108 + - const: mg_clk 109 + - const: mg_core_clk 110 + - const: axi_clk 111 + 103 112 required: 104 113 - marvell,system-controller 105 114

+2 -2

Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml

··· 176 176 compatible: 177 177 contains: 178 178 enum: 179 + - qcom,sa8775p-qmp-gen4x2-pcie-phy 180 + - qcom,sa8775p-qmp-gen4x4-pcie-phy 179 181 - qcom,sc8280xp-qmp-gen3x1-pcie-phy 180 182 - qcom,sc8280xp-qmp-gen3x2-pcie-phy 181 183 - qcom,sc8280xp-qmp-gen3x4-pcie-phy ··· 199 197 contains: 200 198 enum: 201 199 - qcom,qcs8300-qmp-gen4x2-pcie-phy 202 - - qcom,sa8775p-qmp-gen4x2-pcie-phy 203 - - qcom,sa8775p-qmp-gen4x4-pcie-phy 204 200 then: 205 201 properties: 206 202 clocks:

+2 -2

drivers/phy/qualcomm/phy-qcom-eusb2-repeater.c

··· 127 127 rptr->cfg->init_tbl[i].value); 128 128 129 129 /* Override registers from devicetree values */ 130 - if (!of_property_read_u8(np, "qcom,tune-usb2-amplitude", &val)) 130 + if (!of_property_read_u8(np, "qcom,tune-usb2-preem", &val)) 131 131 regmap_write(regmap, base + EUSB2_TUNE_USB2_PREEM, val); 132 132 133 133 if (!of_property_read_u8(np, "qcom,tune-usb2-disc-thres", &val)) 134 134 regmap_write(regmap, base + EUSB2_TUNE_HSDISC, val); 135 135 136 - if (!of_property_read_u8(np, "qcom,tune-usb2-preem", &val)) 136 + if (!of_property_read_u8(np, "qcom,tune-usb2-amplitude", &val)) 137 137 regmap_write(regmap, base + EUSB2_TUNE_IUSB2, val); 138 138 139 139 /* Wait for status OK */

+19 -6

drivers/phy/qualcomm/phy-qcom-qmp-pcie.c

··· 3067 3067 struct clk_fixed_rate aux_clk_fixed; 3068 3068 }; 3069 3069 3070 + static bool qphy_checkbits(const void __iomem *base, u32 offset, u32 val) 3071 + { 3072 + u32 reg; 3073 + 3074 + reg = readl(base + offset); 3075 + return (reg & val) == val; 3076 + } 3077 + 3070 3078 static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val) 3071 3079 { 3072 3080 u32 reg; ··· 4347 4339 struct qmp_pcie *qmp = phy_get_drvdata(phy); 4348 4340 const struct qmp_phy_cfg *cfg = qmp->cfg; 4349 4341 void __iomem *pcs = qmp->pcs; 4350 - bool phy_initialized = !!(readl(pcs + cfg->regs[QPHY_START_CTRL])); 4351 4342 int ret; 4352 4343 4353 - qmp->skip_init = qmp->nocsr_reset && phy_initialized; 4354 4344 /* 4355 - * We need to check the existence of init sequences in two cases: 4356 - * 1. The PHY doesn't support no_csr reset. 4357 - * 2. The PHY supports no_csr reset but isn't initialized by bootloader. 4358 - * As we can't skip init in these two cases. 4345 + * We can skip PHY initialization if all of the following conditions 4346 + * are met: 4347 + * 1. The PHY supports the nocsr_reset that preserves the PHY config. 4348 + * 2. The PHY was started (and not powered down again) by the 4349 + * bootloader, with all of the expected bits set correctly. 4350 + * In this case, we can continue without having the init sequence 4351 + * defined in the driver. 4359 4352 */ 4353 + qmp->skip_init = qmp->nocsr_reset && 4354 + qphy_checkbits(pcs, cfg->regs[QPHY_START_CTRL], SERDES_START | PCS_START) && 4355 + qphy_checkbits(pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], cfg->pwrdn_ctrl); 4356 + 4360 4357 if (!qmp->skip_init && !cfg->tbls.serdes_num) { 4361 4358 dev_err(qmp->dev, "Init sequence not available\n"); 4362 4359 return -ENODATA;

+5 -1

drivers/phy/tegra/xusb-tegra210.c

··· 3164 3164 } 3165 3165 3166 3166 pdev = of_find_device_by_node(np); 3167 + of_node_put(np); 3167 3168 if (!pdev) { 3168 3169 dev_warn(dev, "PMC device is not available\n"); 3169 3170 goto out; 3170 3171 } 3171 3172 3172 - if (!platform_get_drvdata(pdev)) 3173 + if (!platform_get_drvdata(pdev)) { 3174 + put_device(&pdev->dev); 3173 3175 return ERR_PTR(-EPROBE_DEFER); 3176 + } 3174 3177 3175 3178 padctl->regmap = dev_get_regmap(&pdev->dev, "usb_sleepwalk"); 3176 3179 if (!padctl->regmap) 3177 3180 dev_info(dev, "failed to find PMC regmap\n"); 3178 3181 3182 + put_device(&pdev->dev); 3179 3183 out: 3180 3184 return &padctl->base; 3181 3185 }

+39 -8

drivers/phy/ti/phy-gmii-sel.c

··· 34 34 PHY_GMII_SEL_PORT_MODE = 0, 35 35 PHY_GMII_SEL_RGMII_ID_MODE, 36 36 PHY_GMII_SEL_RMII_IO_CLK_EN, 37 + PHY_GMII_SEL_FIXED_TX_DELAY, 37 38 PHY_GMII_SEL_LAST, 38 39 }; 39 40 ··· 128 127 goto unsupported; 129 128 } 130 129 130 + /* With a fixed delay, some modes are not supported at all. */ 131 + if (soc_data->features & BIT(PHY_GMII_SEL_FIXED_TX_DELAY) && 132 + rgmii_id != 0) 133 + return -EINVAL; 134 + 131 135 if_phy->phy_if_mode = submode; 132 136 133 137 dev_dbg(dev, "%s id:%u mode:%u rgmii_id:%d rmii_clk_ext:%d\n", ··· 216 210 217 211 static const 218 212 struct reg_field phy_gmii_sel_fields_am654[][PHY_GMII_SEL_LAST] = { 219 - { [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x0, 0, 2), }, 220 - { [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x4, 0, 2), }, 221 - { [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x8, 0, 2), }, 222 - { [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0xC, 0, 2), }, 223 - { [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x10, 0, 2), }, 224 - { [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x14, 0, 2), }, 225 - { [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x18, 0, 2), }, 226 - { [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x1C, 0, 2), }, 213 + { 214 + [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x0, 0, 2), 215 + [PHY_GMII_SEL_RGMII_ID_MODE] = REG_FIELD(0x0, 4, 4), 216 + }, { 217 + [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x4, 0, 2), 218 + [PHY_GMII_SEL_RGMII_ID_MODE] = REG_FIELD(0x4, 4, 4), 219 + }, { 220 + [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x8, 0, 2), 221 + [PHY_GMII_SEL_RGMII_ID_MODE] = REG_FIELD(0x8, 4, 4), 222 + }, { 223 + [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0xC, 0, 2), 224 + [PHY_GMII_SEL_RGMII_ID_MODE] = REG_FIELD(0xC, 4, 4), 225 + }, { 226 + [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x10, 0, 2), 227 + [PHY_GMII_SEL_RGMII_ID_MODE] = REG_FIELD(0x10, 4, 4), 228 + }, { 229 + [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x14, 0, 2), 230 + [PHY_GMII_SEL_RGMII_ID_MODE] = REG_FIELD(0x14, 4, 4), 231 + }, { 232 + [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x18, 0, 2), 233 + [PHY_GMII_SEL_RGMII_ID_MODE] = REG_FIELD(0x18, 4, 4), 234 + }, { 235 + [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x1C, 0, 2), 236 + [PHY_GMII_SEL_RGMII_ID_MODE] = REG_FIELD(0x1C, 4, 4), 237 + }, 227 238 }; 228 239 229 240 static const 230 241 struct phy_gmii_sel_soc_data phy_gmii_sel_soc_am654 = { 231 242 .use_of_data = true, 243 + .features = BIT(PHY_GMII_SEL_RGMII_ID_MODE) | 244 + BIT(PHY_GMII_SEL_FIXED_TX_DELAY), 232 245 .regfields = phy_gmii_sel_fields_am654, 233 246 }; 234 247 235 248 static const 236 249 struct phy_gmii_sel_soc_data phy_gmii_sel_cpsw5g_soc_j7200 = { 237 250 .use_of_data = true, 251 + .features = BIT(PHY_GMII_SEL_RGMII_ID_MODE) | 252 + BIT(PHY_GMII_SEL_FIXED_TX_DELAY), 238 253 .regfields = phy_gmii_sel_fields_am654, 239 254 .extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII) | BIT(PHY_INTERFACE_MODE_SGMII) | 240 255 BIT(PHY_INTERFACE_MODE_USXGMII), ··· 266 239 static const 267 240 struct phy_gmii_sel_soc_data phy_gmii_sel_cpsw9g_soc_j721e = { 268 241 .use_of_data = true, 242 + .features = BIT(PHY_GMII_SEL_RGMII_ID_MODE) | 243 + BIT(PHY_GMII_SEL_FIXED_TX_DELAY), 269 244 .regfields = phy_gmii_sel_fields_am654, 270 245 .extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII) | BIT(PHY_INTERFACE_MODE_SGMII), 271 246 .num_ports = 8, ··· 277 248 static const 278 249 struct phy_gmii_sel_soc_data phy_gmii_sel_cpsw9g_soc_j784s4 = { 279 250 .use_of_data = true, 251 + .features = BIT(PHY_GMII_SEL_RGMII_ID_MODE) | 252 + BIT(PHY_GMII_SEL_FIXED_TX_DELAY), 280 253 .regfields = phy_gmii_sel_fields_am654, 281 254 .extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII) | BIT(PHY_INTERFACE_MODE_SGMII) | 282 255 BIT(PHY_INTERFACE_MODE_USXGMII),

+13

drivers/phy/ti/phy-omap-usb2.c

··· 363 363 phy->flags |= OMAP_USB2_DISABLE_CHRG_DET; 364 364 } 365 365 366 + static void omap_usb2_put_device(void *_dev) 367 + { 368 + struct device *dev = _dev; 369 + 370 + put_device(dev); 371 + } 372 + 366 373 static int omap_usb2_probe(struct platform_device *pdev) 367 374 { 368 375 struct omap_usb *phy; ··· 380 373 struct device_node *control_node; 381 374 struct platform_device *control_pdev; 382 375 const struct usb_phy_data *phy_data; 376 + int ret; 383 377 384 378 phy_data = device_get_match_data(&pdev->dev); 385 379 if (!phy_data) ··· 431 423 return -EINVAL; 432 424 } 433 425 phy->control_dev = &control_pdev->dev; 426 + 427 + ret = devm_add_action_or_reset(&pdev->dev, omap_usb2_put_device, 428 + phy->control_dev); 429 + if (ret) 430 + return ret; 434 431 } else { 435 432 if (of_property_read_u32_index(node, 436 433 "syscon-phy-power", 1,

+13

drivers/phy/ti/phy-ti-pipe3.c

··· 667 667 return 0; 668 668 } 669 669 670 + static void ti_pipe3_put_device(void *_dev) 671 + { 672 + struct device *dev = _dev; 673 + 674 + put_device(dev); 675 + } 676 + 670 677 static int ti_pipe3_get_sysctrl(struct ti_pipe3 *phy) 671 678 { 672 679 struct device *dev = phy->dev; 673 680 struct device_node *node = dev->of_node; 674 681 struct device_node *control_node; 675 682 struct platform_device *control_pdev; 683 + int ret; 676 684 677 685 phy->phy_power_syscon = syscon_regmap_lookup_by_phandle(node, 678 686 "syscon-phy-power"); ··· 712 704 } 713 705 714 706 phy->control_dev = &control_pdev->dev; 707 + 708 + ret = devm_add_action_or_reset(dev, ti_pipe3_put_device, 709 + phy->control_dev); 710 + if (ret) 711 + return ret; 715 712 } 716 713 717 714 if (phy->mode == PIPE3_MODE_PCIE) {

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