Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'pci-v6.18-fixes-5' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci
Pull pci fixes from Bjorn Helgaas:
- Cache the ASPM L0s/L1 Supported bits early so quirks can override
them if necessary (Bjorn Helgaas)
- Add quirks for PA Semi and Freescale Root Ports and a HiSilicon Wi-Fi
device that are reported to have broken L0s and L1 (Shawn Lin, Bjorn
Helgaas)
* tag 'pci-v6.18-fixes-5' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci:
PCI/ASPM: Avoid L0s and L1 on Hi1105 [19e5:1105] Wi-Fi
PCI/ASPM: Avoid L0s and L1 on PA Semi [1959:a002] Root Ports
PCI/ASPM: Avoid L0s and L1 on Freescale [1957:0451] Root Ports
PCI/ASPM: Convert quirks to override advertised link states
PCI/ASPM: Add pcie_aspm_remove_cap() to override advertised link states
PCI/ASPM: Cache L0s/L1 Supported so advertised link states can be overridden
+49
-27
+2
drivers/pci/pci.h
+2
drivers/pci/pci.h
···
958
958
void pci_restore_aspm_l1ss_state(struct pci_dev *dev);
959
959
960
960
#ifdef CONFIG_PCIEASPM
961
+
void pcie_aspm_remove_cap(struct pci_dev *pdev, u32 lnkcap);
961
962
void pcie_aspm_init_link_state(struct pci_dev *pdev);
962
963
void pcie_aspm_exit_link_state(struct pci_dev *pdev);
963
964
void pcie_aspm_pm_state_change(struct pci_dev *pdev, bool locked);
···
966
965
void pci_configure_ltr(struct pci_dev *pdev);
967
966
void pci_bridge_reconfigure_ltr(struct pci_dev *pdev);
968
967
#else
968
+
static inline void pcie_aspm_remove_cap(struct pci_dev *pdev, u32 lnkcap) { }
969
969
static inline void pcie_aspm_init_link_state(struct pci_dev *pdev) { }
970
970
static inline void pcie_aspm_exit_link_state(struct pci_dev *pdev) { }
971
971
static inline void pcie_aspm_pm_state_change(struct pci_dev *pdev, bool locked) { }
+17
-8
drivers/pci/pcie/aspm.c
+17
-8
drivers/pci/pcie/aspm.c
···
814
814
static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist)
815
815
{
816
816
struct pci_dev *child = link->downstream, *parent = link->pdev;
817
-
u32 parent_lnkcap, child_lnkcap;
818
817
u16 parent_lnkctl, child_lnkctl;
819
818
struct pci_bus *linkbus = parent->subordinate;
820
819
···
828
829
* If ASPM not supported, don't mess with the clocks and link,
829
830
* bail out now.
830
831
*/
831
-
pcie_capability_read_dword(parent, PCI_EXP_LNKCAP, &parent_lnkcap);
832
-
pcie_capability_read_dword(child, PCI_EXP_LNKCAP, &child_lnkcap);
833
-
if (!(parent_lnkcap & child_lnkcap & PCI_EXP_LNKCAP_ASPMS))
832
+
if (!(parent->aspm_l0s_support && child->aspm_l0s_support) &&
833
+
!(parent->aspm_l1_support && child->aspm_l1_support))
834
834
return;
835
835
836
836
/* Configure common clock before checking latencies */
···
841
843
* read-only Link Capabilities may change depending on common clock
842
844
* configuration (PCIe r5.0, sec 7.5.3.6).
843
845
*/
844
-
pcie_capability_read_dword(parent, PCI_EXP_LNKCAP, &parent_lnkcap);
845
-
pcie_capability_read_dword(child, PCI_EXP_LNKCAP, &child_lnkcap);
846
846
pcie_capability_read_word(parent, PCI_EXP_LNKCTL, &parent_lnkctl);
847
847
pcie_capability_read_word(child, PCI_EXP_LNKCTL, &child_lnkctl);
848
848
···
860
864
* given link unless components on both sides of the link each
861
865
* support L0s.
862
866
*/
863
-
if (parent_lnkcap & child_lnkcap & PCI_EXP_LNKCAP_ASPM_L0S)
867
+
if (parent->aspm_l0s_support && child->aspm_l0s_support)
864
868
link->aspm_support |= PCIE_LINK_STATE_L0S;
865
869
866
870
if (child_lnkctl & PCI_EXP_LNKCTL_ASPM_L0S)
···
869
873
link->aspm_enabled |= PCIE_LINK_STATE_L0S_DW;
870
874
871
875
/* Setup L1 state */
872
-
if (parent_lnkcap & child_lnkcap & PCI_EXP_LNKCAP_ASPM_L1)
876
+
if (parent->aspm_l1_support && child->aspm_l1_support)
873
877
link->aspm_support |= PCIE_LINK_STATE_L1;
874
878
875
879
if (parent_lnkctl & child_lnkctl & PCI_EXP_LNKCTL_ASPM_L1)
···
1525
1529
return __pci_enable_link_state(pdev, state, true);
1526
1530
}
1527
1531
EXPORT_SYMBOL(pci_enable_link_state_locked);
1532
+
1533
+
void pcie_aspm_remove_cap(struct pci_dev *pdev, u32 lnkcap)
1534
+
{
1535
+
if (lnkcap & PCI_EXP_LNKCAP_ASPM_L0S)
1536
+
pdev->aspm_l0s_support = 0;
1537
+
if (lnkcap & PCI_EXP_LNKCAP_ASPM_L1)
1538
+
pdev->aspm_l1_support = 0;
1539
+
1540
+
pci_info(pdev, "ASPM: Link Capabilities%s%s treated as unsupported to avoid device defect\n",
1541
+
lnkcap & PCI_EXP_LNKCAP_ASPM_L0S ? " L0s" : "",
1542
+
lnkcap & PCI_EXP_LNKCAP_ASPM_L1 ? " L1" : "");
1543
+
1544
+
}
1528
1545
1529
1546
static int pcie_aspm_set_policy(const char *val,
1530
1547
const struct kernel_param *kp)
+7
drivers/pci/probe.c
+7
drivers/pci/probe.c
···
1656
1656
if (reg32 & PCI_EXP_LNKCAP_DLLLARC)
1657
1657
pdev->link_active_reporting = 1;
1658
1658
1659
+
#ifdef CONFIG_PCIEASPM
1660
+
if (reg32 & PCI_EXP_LNKCAP_ASPM_L0S)
1661
+
pdev->aspm_l0s_support = 1;
1662
+
if (reg32 & PCI_EXP_LNKCAP_ASPM_L1)
1663
+
pdev->aspm_l1_support = 1;
1664
+
#endif
1665
+
1659
1666
parent = pci_upstream_bridge(pdev);
1660
1667
if (!parent)
1661
1668
return;
+21
-19
drivers/pci/quirks.c
+21
-19
drivers/pci/quirks.c
···
2494
2494
*/
2495
2495
static void quirk_disable_aspm_l0s(struct pci_dev *dev)
2496
2496
{
2497
-
pci_info(dev, "Disabling L0s\n");
2498
-
pci_disable_link_state(dev, PCIE_LINK_STATE_L0S);
2497
+
pcie_aspm_remove_cap(dev, PCI_EXP_LNKCAP_ASPM_L0S);
2499
2498
}
2500
-
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a7, quirk_disable_aspm_l0s);
2501
-
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a9, quirk_disable_aspm_l0s);
2502
-
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10b6, quirk_disable_aspm_l0s);
2503
-
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c6, quirk_disable_aspm_l0s);
2504
-
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c7, quirk_disable_aspm_l0s);
2505
-
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c8, quirk_disable_aspm_l0s);
2506
-
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10d6, quirk_disable_aspm_l0s);
2507
-
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10db, quirk_disable_aspm_l0s);
2508
-
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10dd, quirk_disable_aspm_l0s);
2509
-
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10e1, quirk_disable_aspm_l0s);
2510
-
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10ec, quirk_disable_aspm_l0s);
2511
-
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f1, quirk_disable_aspm_l0s);
2512
-
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f4, quirk_disable_aspm_l0s);
2513
-
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1508, quirk_disable_aspm_l0s);
2499
+
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10a7, quirk_disable_aspm_l0s);
2500
+
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10a9, quirk_disable_aspm_l0s);
2501
+
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10b6, quirk_disable_aspm_l0s);
2502
+
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10c6, quirk_disable_aspm_l0s);
2503
+
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10c7, quirk_disable_aspm_l0s);
2504
+
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10c8, quirk_disable_aspm_l0s);
2505
+
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10d6, quirk_disable_aspm_l0s);
2506
+
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10db, quirk_disable_aspm_l0s);
2507
+
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10dd, quirk_disable_aspm_l0s);
2508
+
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10e1, quirk_disable_aspm_l0s);
2509
+
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10ec, quirk_disable_aspm_l0s);
2510
+
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10f1, quirk_disable_aspm_l0s);
2511
+
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10f4, quirk_disable_aspm_l0s);
2512
+
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1508, quirk_disable_aspm_l0s);
2514
2513
2515
2514
static void quirk_disable_aspm_l0s_l1(struct pci_dev *dev)
2516
2515
{
2517
-
pci_info(dev, "Disabling ASPM L0s/L1\n");
2518
-
pci_disable_link_state(dev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1);
2516
+
pcie_aspm_remove_cap(dev,
2517
+
PCI_EXP_LNKCAP_ASPM_L0S | PCI_EXP_LNKCAP_ASPM_L1);
2519
2518
}
2520
2519
2521
2520
/*
···
2522
2523
* upstream PCIe root port when ASPM is enabled. At least L0s mode is affected;
2523
2524
* disable both L0s and L1 for now to be safe.
2524
2525
*/
2525
-
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ASMEDIA, 0x1080, quirk_disable_aspm_l0s_l1);
2526
+
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ASMEDIA, 0x1080, quirk_disable_aspm_l0s_l1);
2527
+
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, 0x0451, quirk_disable_aspm_l0s_l1);
2528
+
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PASEMI, 0xa002, quirk_disable_aspm_l0s_l1);
2529
+
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HUAWEI, 0x1105, quirk_disable_aspm_l0s_l1);
2526
2530
2527
2531
/*
2528
2532
* Some Pericom PCIe-to-PCI bridges in reverse mode need the PCIe Retrain
+2
include/linux/pci.h
+2
include/linux/pci.h
···
412
412
u16 l1ss; /* L1SS Capability pointer */
413
413
#ifdef CONFIG_PCIEASPM
414
414
struct pcie_link_state *link_state; /* ASPM link state */
415
+
unsigned int aspm_l0s_support:1; /* ASPM L0s support */
416
+
unsigned int aspm_l1_support:1; /* ASPM L1 support */
415
417
unsigned int ltr_path:1; /* Latency Tolerance Reporting
416
418
supported from root to here */
417
419
#endif