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crypto: caam - determine whether CAAM supports blob encap/decap

Depending on SoC variant, a CAAM may be available, but with some futures
fused out. The LS1028A (non-E) SoC is one such SoC and while it
indicates BLOB support, BLOB operations will ultimately fail, because
there is no AES support. Add a new blob_present member to reflect
whether both BLOB support and the AES support it depends on is
available.

These will be used in a follow-up commit to allow blob driver
initialization to error out on SoCs without the necessary hardware
support instead of failing at runtime with a cryptic

caam_jr 8020000.jr: 20000b0f: CCB: desc idx 11: : Invalid CHA selected.

Co-developed-by: Michael Walle <michael@walle.cc>
Signed-off-by: Michael Walle <michael@walle.cc>
Tested-by: Michael Walle <michael@walle.cc> # on ls1028a (non-E and E)
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Reviewed-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Signed-off-by: Jarkko Sakkinen <jarkko@kernel.org>

authored by

Ahmad Fatoum and committed by
Jarkko Sakkinen 7a0e7d52 fcd7c269

+19 -3
+15 -2
drivers/crypto/caam/ctrl.c
··· 820 820 return -ENOMEM; 821 821 } 822 822 823 - if (ctrlpriv->era < 10) 823 + comp_params = rd_reg32(&ctrl->perfmon.comp_parms_ls); 824 + ctrlpriv->blob_present = !!(comp_params & CTPR_LS_BLOB); 825 + 826 + /* 827 + * Some SoCs like the LS1028A (non-E) indicate CTPR_LS_BLOB support, 828 + * but fail when actually using it due to missing AES support, so 829 + * check both here. 830 + */ 831 + if (ctrlpriv->era < 10) { 824 832 rng_vid = (rd_reg32(&ctrl->perfmon.cha_id_ls) & 825 833 CHA_ID_LS_RNG_MASK) >> CHA_ID_LS_RNG_SHIFT; 826 - else 834 + ctrlpriv->blob_present = ctrlpriv->blob_present && 835 + (rd_reg32(&ctrl->perfmon.cha_num_ls) & CHA_ID_LS_AES_MASK); 836 + } else { 827 837 rng_vid = (rd_reg32(&ctrl->vreg.rng) & CHA_VER_VID_MASK) >> 828 838 CHA_VER_VID_SHIFT; 839 + ctrlpriv->blob_present = ctrlpriv->blob_present && 840 + (rd_reg32(&ctrl->vreg.aesa) & CHA_VER_MISC_AES_NUM_MASK); 841 + } 829 842 830 843 /* 831 844 * If SEC has RNG version >= 4 and RNG state handle has not been
+1
drivers/crypto/caam/intern.h
··· 92 92 */ 93 93 u8 total_jobrs; /* Total Job Rings in device */ 94 94 u8 qi_present; /* Nonzero if QI present in device */ 95 + u8 blob_present; /* Nonzero if BLOB support present in device */ 95 96 u8 mc_en; /* Nonzero if MC f/w is active */ 96 97 int secvio_irq; /* Security violation interrupt number */ 97 98 int virt_en; /* Virtualization enabled in CAAM */
+3 -1
drivers/crypto/caam/regs.h
··· 320 320 #define CHA_VER_VID_MASK (0xffull << CHA_VER_VID_SHIFT) 321 321 322 322 /* CHA Miscellaneous Information - AESA_MISC specific */ 323 - #define CHA_VER_MISC_AES_GCM BIT(1 + CHA_VER_MISC_SHIFT) 323 + #define CHA_VER_MISC_AES_NUM_MASK GENMASK(7, 0) 324 + #define CHA_VER_MISC_AES_GCM BIT(1 + CHA_VER_MISC_SHIFT) 324 325 325 326 /* CHA Miscellaneous Information - PKHA_MISC specific */ 326 327 #define CHA_VER_MISC_PKHA_NO_CRYPT BIT(7 + CHA_VER_MISC_SHIFT) ··· 415 414 #define CTPR_MS_PG_SZ_MASK 0x10 416 415 #define CTPR_MS_PG_SZ_SHIFT 4 417 416 u32 comp_parms_ms; /* CTPR - Compile Parameters Register */ 417 + #define CTPR_LS_BLOB BIT(1) 418 418 u32 comp_parms_ls; /* CTPR - Compile Parameters Register */ 419 419 u64 rsvd1[2]; 420 420