Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge git://git.kernel.org/pub/scm/linux/kernel/git/cmetcalf/linux-tile
* git://git.kernel.org/pub/scm/linux/kernel/git/cmetcalf/linux-tile:
arch/tile: don't validate CROSS_COMPILE needlessly
arch/tile: export only COMMAND_LINE_SIZE to userspace.
arch/tile: rename ARCH_KMALLOC_MINALIGN to ARCH_DMA_MINALIGN
arch/tile: Rename the hweight() implementations to __arch_hweight()
arch/tile: extend syscall ABI to set r1 on return as well.
arch/tile: Various cleanups.
arch/tile: support backtracing on TILE-Gx
arch/tile: Fix a couple of issues with the COMPAT code for TILE-Gx.
arch/tile: Use separate, better minsec values for clocksource and sched_clock.
arch/tile: correct a bug in freeing bootmem by VA for the optional second initrd.
arch: tile: mm: pgtable.c: Removed duplicated #include
arch: tile: kernel/proc.c Removed duplicated #include
Add fanotify syscalls to <asm-generic/unistd.h>.
arch/tile: support new kunmap_atomic() naming convention.
tile: remove unused ISA_DMA_THRESHOLD define
Conflicts in arch/tile/configs/tile_defconfig (pick the mainline version
with the reduced defconfig).
+218
-206
+11
-9
arch/tile/Makefile
+11
-9
arch/tile/Makefile
···
8
8
# for "archclean" and "archdep" for cleaning up and making dependencies for
9
9
# this architecture
10
10
11
-
ifeq ($(CROSS_COMPILE),)
12
11
# If building with TILERA_ROOT set (i.e. using the Tilera Multicore
13
12
# Development Environment) we can set CROSS_COMPILE based on that.
14
-
ifdef TILERA_ROOT
15
-
CROSS_COMPILE = $(TILERA_ROOT)/bin/tile-
16
-
endif
17
-
endif
18
-
19
13
# If we're not cross-compiling, make sure we're on the right architecture.
14
+
# Only bother to test for a few common targets, to avoid useless errors.
20
15
ifeq ($(CROSS_COMPILE),)
21
-
HOST_ARCH = $(shell uname -m)
22
-
ifneq ($(HOST_ARCH),$(ARCH))
16
+
ifdef TILERA_ROOT
17
+
CROSS_COMPILE := $(TILERA_ROOT)/bin/tile-
18
+
else
19
+
goals := $(if $(MAKECMDGOALS), $(MAKECMDGOALS), all)
20
+
ifneq ($(strip $(filter vmlinux modules all,$(goals))),)
21
+
HOST_ARCH := $(shell uname -m)
22
+
ifneq ($(HOST_ARCH),$(ARCH))
23
23
$(error Set TILERA_ROOT or CROSS_COMPILE when building $(ARCH) on $(HOST_ARCH))
24
-
endif
24
+
endif
25
+
endif
26
+
endif
25
27
endif
26
28
27
29
+1
-3
arch/tile/include/arch/abi.h
+1
-3
arch/tile/include/arch/abi.h
···
59
59
* The ABI requires callers to allocate a caller state save area of
60
60
* this many bytes at the bottom of each stack frame.
61
61
*/
62
-
#ifdef __tile__
63
-
#define C_ABI_SAVE_AREA_SIZE (2 * __SIZEOF_POINTER__)
64
-
#endif
62
+
#define C_ABI_SAVE_AREA_SIZE (2 * (CHIP_WORD_SIZE() / 8))
65
63
66
64
/**
67
65
* The operand to an 'info' opcode directing the backtracer to not
-37
arch/tile/include/asm/atomic_32.h
-37
arch/tile/include/asm/atomic_32.h
···
255
255
#define smp_mb__after_atomic_dec() do { } while (0)
256
256
#define smp_mb__after_atomic_inc() do { } while (0)
257
257
258
-
259
-
/*
260
-
* Support "tns" atomic integers. These are atomic integers that can
261
-
* hold any value but "1". They are more efficient than regular atomic
262
-
* operations because the "lock" (aka acquire) step is a single "tns"
263
-
* in the uncontended case, and the "unlock" (aka release) step is a
264
-
* single "store" without an mf. (However, note that on tilepro the
265
-
* "tns" will evict the local cache line, so it's not all upside.)
266
-
*
267
-
* Note that you can ONLY observe the value stored in the pointer
268
-
* using these operations; a direct read of the value may confusingly
269
-
* return the special value "1".
270
-
*/
271
-
272
-
int __tns_atomic_acquire(atomic_t *);
273
-
void __tns_atomic_release(atomic_t *p, int v);
274
-
275
-
static inline void tns_atomic_set(atomic_t *v, int i)
276
-
{
277
-
__tns_atomic_acquire(v);
278
-
__tns_atomic_release(v, i);
279
-
}
280
-
281
-
static inline int tns_atomic_cmpxchg(atomic_t *v, int o, int n)
282
-
{
283
-
int ret = __tns_atomic_acquire(v);
284
-
__tns_atomic_release(v, (ret == o) ? n : ret);
285
-
return ret;
286
-
}
287
-
288
-
static inline int tns_atomic_xchg(atomic_t *v, int n)
289
-
{
290
-
int ret = __tns_atomic_acquire(v);
291
-
__tns_atomic_release(v, n);
292
-
return ret;
293
-
}
294
-
295
258
#endif /* !__ASSEMBLY__ */
296
259
297
260
/*
+3
-1
arch/tile/include/asm/backtrace.h
+3
-1
arch/tile/include/asm/backtrace.h
+5
-4
arch/tile/include/asm/bitops.h
+5
-4
arch/tile/include/asm/bitops.h
···
98
98
return (sizeof(__u64) * 8) - __builtin_clzll(w);
99
99
}
100
100
101
-
static inline unsigned int hweight32(unsigned int w)
101
+
static inline unsigned int __arch_hweight32(unsigned int w)
102
102
{
103
103
return __builtin_popcount(w);
104
104
}
105
105
106
-
static inline unsigned int hweight16(unsigned int w)
106
+
static inline unsigned int __arch_hweight16(unsigned int w)
107
107
{
108
108
return __builtin_popcount(w & 0xffff);
109
109
}
110
110
111
-
static inline unsigned int hweight8(unsigned int w)
111
+
static inline unsigned int __arch_hweight8(unsigned int w)
112
112
{
113
113
return __builtin_popcount(w & 0xff);
114
114
}
115
115
116
-
static inline unsigned long hweight64(__u64 w)
116
+
static inline unsigned long __arch_hweight64(__u64 w)
117
117
{
118
118
return __builtin_popcountll(w);
119
119
}
120
120
121
+
#include <asm-generic/bitops/const_hweight.h>
121
122
#include <asm-generic/bitops/lock.h>
122
123
#include <asm-generic/bitops/sched.h>
123
124
#include <asm-generic/bitops/ext2-non-atomic.h>
+2
-3
arch/tile/include/asm/cache.h
+2
-3
arch/tile/include/asm/cache.h
···
27
27
#define L2_CACHE_ALIGN(x) (((x)+(L2_CACHE_BYTES-1)) & -L2_CACHE_BYTES)
28
28
29
29
/*
30
-
* TILE-Gx is fully coherents so we don't need to define
31
-
* ARCH_KMALLOC_MINALIGN.
30
+
* TILE-Gx is fully coherent so we don't need to define ARCH_DMA_MINALIGN.
32
31
*/
33
32
#ifndef __tilegx__
34
-
#define ARCH_KMALLOC_MINALIGN L2_CACHE_BYTES
33
+
#define ARCH_DMA_MINALIGN L2_CACHE_BYTES
35
34
#endif
36
35
37
36
/* use the cache line size for the L2, which is where it counts */
+1
-1
arch/tile/include/asm/highmem.h
+1
-1
arch/tile/include/asm/highmem.h
···
60
60
/* This macro is used only in map_new_virtual() to map "page". */
61
61
#define kmap_prot page_to_kpgprot(page)
62
62
63
-
void kunmap_atomic(void *kvaddr, enum km_type type);
63
+
void kunmap_atomic_notypecheck(void *kvaddr, enum km_type type);
64
64
void *kmap_atomic_pfn(unsigned long pfn, enum km_type type);
65
65
void *kmap_atomic_prot_pfn(unsigned long pfn, enum km_type type, pgprot_t prot);
66
66
struct page *kmap_atomic_to_page(void *ptr);
+5
-1
arch/tile/include/asm/page.h
+5
-1
arch/tile/include/asm/page.h
···
129
129
130
130
#endif
131
131
132
+
static inline __attribute_const__ int get_order(unsigned long size)
133
+
{
134
+
return BITS_PER_LONG - __builtin_clzl((size - 1) >> PAGE_SHIFT);
135
+
}
136
+
132
137
#endif /* !__ASSEMBLY__ */
133
138
134
139
#define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT)
···
337
332
(VM_READ | VM_WRITE | VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
338
333
339
334
#include <asm-generic/memory_model.h>
340
-
#include <asm-generic/getorder.h>
341
335
342
336
#endif /* __KERNEL__ */
343
337
-21
arch/tile/include/asm/scatterlist.h
-21
arch/tile/include/asm/scatterlist.h
···
1
-
/*
2
-
* Copyright 2010 Tilera Corporation. All Rights Reserved.
3
-
*
4
-
* This program is free software; you can redistribute it and/or
5
-
* modify it under the terms of the GNU General Public License
6
-
* as published by the Free Software Foundation, version 2.
7
-
*
8
-
* This program is distributed in the hope that it will be useful, but
9
-
* WITHOUT ANY WARRANTY; without even the implied warranty of
10
-
* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11
-
* NON INFRINGEMENT. See the GNU General Public License for
12
-
* more details.
13
-
*/
14
-
15
-
#ifndef _ASM_TILE_SCATTERLIST_H
16
-
#define _ASM_TILE_SCATTERLIST_H
17
-
18
-
#define ISA_DMA_THRESHOLD (~0UL)
19
-
20
1
#include <asm-generic/scatterlist.h>
21
-
22
-
#endif /* _ASM_TILE_SCATTERLIST_H */
+6
-2
arch/tile/include/asm/setup.h
+6
-2
arch/tile/include/asm/setup.h
···
15
15
#ifndef _ASM_TILE_SETUP_H
16
16
#define _ASM_TILE_SETUP_H
17
17
18
+
#define COMMAND_LINE_SIZE 2048
19
+
20
+
#ifdef __KERNEL__
21
+
18
22
#include <linux/pfn.h>
19
23
#include <linux/init.h>
20
24
···
27
23
*/
28
24
#define MAXMEM_PFN PFN_DOWN(MAXMEM)
29
25
30
-
#define COMMAND_LINE_SIZE 2048
31
-
32
26
void early_panic(const char *fmt, ...);
33
27
void warn_early_printk(void);
34
28
void __init disable_early_printk(void);
29
+
30
+
#endif /* __KERNEL__ */
35
31
36
32
#endif /* _ASM_TILE_SETUP_H */
+4
arch/tile/include/asm/siginfo.h
+4
arch/tile/include/asm/siginfo.h
+2
-2
arch/tile/include/asm/uaccess.h
+2
-2
arch/tile/include/asm/uaccess.h
···
389
389
* Returns number of bytes that could not be copied.
390
390
* On success, this will be zero.
391
391
*/
392
-
extern unsigned long __copy_in_user_asm(
392
+
extern unsigned long __copy_in_user_inatomic(
393
393
void __user *to, const void __user *from, unsigned long n);
394
394
395
395
static inline unsigned long __must_check
396
396
__copy_in_user(void __user *to, const void __user *from, unsigned long n)
397
397
{
398
398
might_sleep();
399
-
return __copy_in_user_asm(to, from, n);
399
+
return __copy_in_user_inatomic(to, from, n);
400
400
}
401
401
402
402
static inline unsigned long __must_check
+4
-4
arch/tile/include/hv/hypervisor.h
+4
-4
arch/tile/include/hv/hypervisor.h
···
532
532
*/
533
533
void hv_clear_intr(HV_IntrMask clear_mask);
534
534
535
-
/** Assert a set of device interrupts.
535
+
/** Raise a set of device interrupts.
536
536
*
537
-
* @param assert_mask Bitmap of interrupts to clear.
537
+
* @param raise_mask Bitmap of interrupts to raise.
538
538
*/
539
-
void hv_assert_intr(HV_IntrMask assert_mask);
539
+
void hv_raise_intr(HV_IntrMask raise_mask);
540
540
541
541
/** Trigger a one-shot interrupt on some tile
542
542
*
···
1712
1712
* @param cache_control This argument allows you to specify a length of
1713
1713
* physical address space to flush (maximum HV_FLUSH_MAX_CACHE_LEN).
1714
1714
* You can "or" in HV_FLUSH_EVICT_L2 to flush the whole L2 cache.
1715
-
* You can "or" in HV_FLUSH_EVICT_LI1 to flush the whole LII cache.
1715
+
* You can "or" in HV_FLUSH_EVICT_L1I to flush the whole L1I cache.
1716
1716
* HV_FLUSH_ALL flushes all caches.
1717
1717
* @param cache_cpumask Bitmask (in row-major order, supervisor-relative) of
1718
1718
* tile indices to perform cache flush on. The low bit of the first
+99
-38
arch/tile/kernel/backtrace.c
+99
-38
arch/tile/kernel/backtrace.c
···
19
19
20
20
#include <arch/chip.h>
21
21
22
-
#if TILE_CHIP < 10
23
-
24
-
25
22
#include <asm/opcode-tile.h>
26
23
27
24
28
25
#define TREG_SP 54
29
26
#define TREG_LR 55
30
27
28
+
29
+
#if TILE_CHIP >= 10
30
+
#define tile_bundle_bits tilegx_bundle_bits
31
+
#define TILE_MAX_INSTRUCTIONS_PER_BUNDLE TILEGX_MAX_INSTRUCTIONS_PER_BUNDLE
32
+
#define TILE_BUNDLE_ALIGNMENT_IN_BYTES TILEGX_BUNDLE_ALIGNMENT_IN_BYTES
33
+
#define tile_decoded_instruction tilegx_decoded_instruction
34
+
#define tile_mnemonic tilegx_mnemonic
35
+
#define parse_insn_tile parse_insn_tilegx
36
+
#define TILE_OPC_IRET TILEGX_OPC_IRET
37
+
#define TILE_OPC_ADDI TILEGX_OPC_ADDI
38
+
#define TILE_OPC_ADDLI TILEGX_OPC_ADDLI
39
+
#define TILE_OPC_INFO TILEGX_OPC_INFO
40
+
#define TILE_OPC_INFOL TILEGX_OPC_INFOL
41
+
#define TILE_OPC_JRP TILEGX_OPC_JRP
42
+
#define TILE_OPC_MOVE TILEGX_OPC_MOVE
43
+
#define OPCODE_STORE TILEGX_OPC_ST
44
+
typedef long long bt_int_reg_t;
45
+
#else
46
+
#define OPCODE_STORE TILE_OPC_SW
47
+
typedef int bt_int_reg_t;
48
+
#endif
31
49
32
50
/** A decoded bundle used for backtracer analysis. */
33
51
struct BacktraceBundle {
···
59
41
/* This implementation only makes sense for native tools. */
60
42
/** Default function to read memory. */
61
43
static bool bt_read_memory(void *result, VirtualAddress addr,
62
-
size_t size, void *extra)
44
+
unsigned int size, void *extra)
63
45
{
64
46
/* FIXME: this should do some horrible signal stuff to catch
65
47
* SEGV cleanly and fail.
···
124
106
find_matching_insn(bundle, TILE_OPC_ADDI, vals, 2);
125
107
if (insn == NULL)
126
108
insn = find_matching_insn(bundle, TILE_OPC_ADDLI, vals, 2);
109
+
#if TILE_CHIP >= 10
110
+
if (insn == NULL)
111
+
insn = find_matching_insn(bundle, TILEGX_OPC_ADDXLI, vals, 2);
112
+
if (insn == NULL)
113
+
insn = find_matching_insn(bundle, TILEGX_OPC_ADDXI, vals, 2);
114
+
#endif
127
115
if (insn == NULL)
128
116
return false;
129
117
···
214
190
return find_matching_insn(bundle, TILE_OPC_MOVE, vals, 2) != NULL;
215
191
}
216
192
217
-
/** Does this bundle contain the instruction 'sw sp, lr'? */
193
+
/** Does this bundle contain a store of lr to sp? */
218
194
static inline bool bt_has_sw_sp_lr(const struct BacktraceBundle *bundle)
219
195
{
220
196
static const int vals[2] = { TREG_SP, TREG_LR };
221
-
return find_matching_insn(bundle, TILE_OPC_SW, vals, 2) != NULL;
197
+
return find_matching_insn(bundle, OPCODE_STORE, vals, 2) != NULL;
222
198
}
199
+
200
+
#if TILE_CHIP >= 10
201
+
/** Track moveli values placed into registers. */
202
+
static inline void bt_update_moveli(const struct BacktraceBundle *bundle,
203
+
int moveli_args[])
204
+
{
205
+
int i;
206
+
for (i = 0; i < bundle->num_insns; i++) {
207
+
const struct tile_decoded_instruction *insn =
208
+
&bundle->insns[i];
209
+
210
+
if (insn->opcode->mnemonic == TILEGX_OPC_MOVELI) {
211
+
int reg = insn->operand_values[0];
212
+
moveli_args[reg] = insn->operand_values[1];
213
+
}
214
+
}
215
+
}
216
+
217
+
/** Does this bundle contain an 'add sp, sp, reg' instruction
218
+
* from a register that we saw a moveli into, and if so, what
219
+
* is the value in the register?
220
+
*/
221
+
static bool bt_has_add_sp(const struct BacktraceBundle *bundle, int *adjust,
222
+
int moveli_args[])
223
+
{
224
+
static const int vals[2] = { TREG_SP, TREG_SP };
225
+
226
+
const struct tile_decoded_instruction *insn =
227
+
find_matching_insn(bundle, TILEGX_OPC_ADDX, vals, 2);
228
+
if (insn) {
229
+
int reg = insn->operand_values[2];
230
+
if (moveli_args[reg]) {
231
+
*adjust = moveli_args[reg];
232
+
return true;
233
+
}
234
+
}
235
+
return false;
236
+
}
237
+
#endif
223
238
224
239
/** Locates the caller's PC and SP for a program starting at the
225
240
* given address.
···
289
226
int num_bundles_prefetched = 0;
290
227
int next_bundle = 0;
291
228
VirtualAddress pc;
229
+
230
+
#if TILE_CHIP >= 10
231
+
/* Naively try to track moveli values to support addx for -m32. */
232
+
int moveli_args[TILEGX_NUM_REGISTERS] = { 0 };
233
+
#endif
292
234
293
235
/* Default to assuming that the caller's sp is the current sp.
294
236
* This is necessary to handle the case where we start backtracing
···
448
380
449
381
if (!sp_determined) {
450
382
int adjust;
451
-
if (bt_has_addi_sp(&bundle, &adjust)) {
383
+
if (bt_has_addi_sp(&bundle, &adjust)
384
+
#if TILE_CHIP >= 10
385
+
|| bt_has_add_sp(&bundle, &adjust, moveli_args)
386
+
#endif
387
+
) {
452
388
location->sp_location = SP_LOC_OFFSET;
453
389
454
390
if (adjust <= 0) {
···
499
427
sp_determined = true;
500
428
}
501
429
}
430
+
431
+
#if TILE_CHIP >= 10
432
+
/* Track moveli arguments for -m32 mode. */
433
+
bt_update_moveli(&bundle, moveli_args);
434
+
#endif
502
435
}
503
436
504
437
if (bt_has_iret(&bundle)) {
···
579
502
break;
580
503
}
581
504
582
-
/* The frame pointer should theoretically be aligned mod 8. If
583
-
* it's not even aligned mod 4 then something terrible happened
584
-
* and we should mark it as invalid.
505
+
/* If the frame pointer is not aligned to the basic word size
506
+
* something terrible happened and we should mark it as invalid.
585
507
*/
586
-
if (fp % 4 != 0)
508
+
if (fp % sizeof(bt_int_reg_t) != 0)
587
509
fp = -1;
588
510
589
511
/* -1 means "don't know initial_frame_caller_pc". */
···
623
547
state->read_memory_func_extra = read_memory_func_extra;
624
548
}
625
549
550
+
/* Handle the case where the register holds more bits than the VA. */
551
+
static bool valid_addr_reg(bt_int_reg_t reg)
552
+
{
553
+
return ((VirtualAddress)reg == reg);
554
+
}
555
+
626
556
bool backtrace_next(BacktraceIterator *state)
627
557
{
628
-
VirtualAddress next_fp, next_pc, next_frame[2];
558
+
VirtualAddress next_fp, next_pc;
559
+
bt_int_reg_t next_frame[2];
629
560
630
561
if (state->fp == -1) {
631
562
/* No parent frame. */
···
646
563
}
647
564
648
565
next_fp = next_frame[1];
649
-
if (next_fp % 4 != 0) {
650
-
/* Caller's frame pointer is suspect, so give up.
651
-
* Technically it should be aligned mod 8, but we will
652
-
* be forgiving here.
653
-
*/
566
+
if (!valid_addr_reg(next_frame[1]) ||
567
+
next_fp % sizeof(bt_int_reg_t) != 0) {
568
+
/* Caller's frame pointer is suspect, so give up. */
654
569
return false;
655
570
}
656
571
···
666
585
} else {
667
586
/* Get the caller PC from the frame linkage area. */
668
587
next_pc = next_frame[0];
669
-
if (next_pc == 0 ||
588
+
if (!valid_addr_reg(next_frame[0]) || next_pc == 0 ||
670
589
next_pc % TILE_BUNDLE_ALIGNMENT_IN_BYTES != 0) {
671
590
/* The PC is suspect, so give up. */
672
591
return false;
···
680
599
681
600
return true;
682
601
}
683
-
684
-
#else /* TILE_CHIP < 10 */
685
-
686
-
void backtrace_init(BacktraceIterator *state,
687
-
BacktraceMemoryReader read_memory_func,
688
-
void *read_memory_func_extra,
689
-
VirtualAddress pc, VirtualAddress lr,
690
-
VirtualAddress sp, VirtualAddress r52)
691
-
{
692
-
state->pc = pc;
693
-
state->sp = sp;
694
-
state->fp = -1;
695
-
state->initial_frame_caller_pc = -1;
696
-
state->read_memory_func = read_memory_func;
697
-
state->read_memory_func_extra = read_memory_func_extra;
698
-
}
699
-
700
-
bool backtrace_next(BacktraceIterator *state) { return false; }
701
-
702
-
#endif /* TILE_CHIP < 10 */
+3
-1
arch/tile/kernel/compat_signal.c
+3
-1
arch/tile/kernel/compat_signal.c
···
56
56
sigset_t uc_sigmask; /* mask last for extensibility */
57
57
};
58
58
59
+
#define COMPAT_SI_PAD_SIZE ((SI_MAX_SIZE - 3 * sizeof(int)) / sizeof(int))
60
+
59
61
struct compat_siginfo {
60
62
int si_signo;
61
63
int si_errno;
62
64
int si_code;
63
65
64
66
union {
65
-
int _pad[SI_PAD_SIZE];
67
+
int _pad[COMPAT_SI_PAD_SIZE];
66
68
67
69
/* kill() */
68
70
struct {
+12
-2
arch/tile/kernel/intvec_32.S
+12
-2
arch/tile/kernel/intvec_32.S
···
952
952
* able to safely read all the remaining words on those cache
953
953
* lines without waiting for the memory subsystem.
954
954
*/
955
-
pop_reg_zero r0, r1, sp, PTREGS_OFFSET_REG(30) - PTREGS_OFFSET_REG(0)
955
+
pop_reg_zero r0, r28, sp, PTREGS_OFFSET_REG(30) - PTREGS_OFFSET_REG(0)
956
956
pop_reg_zero r30, r2, sp, PTREGS_OFFSET_PC - PTREGS_OFFSET_REG(30)
957
957
pop_reg_zero r21, r3, sp, PTREGS_OFFSET_EX1 - PTREGS_OFFSET_PC
958
958
pop_reg_zero lr, r4, sp, PTREGS_OFFSET_REG(52) - PTREGS_OFFSET_EX1
···
1017
1017
{ move r22, zero; move r23, zero }
1018
1018
{ move r24, zero; move r25, zero }
1019
1019
{ move r26, zero; move r27, zero }
1020
-
{ move r28, zero; move r29, zero }
1020
+
1021
+
/* Set r1 to errno if we are returning an error, otherwise zero. */
1022
+
{
1023
+
moveli r29, 1024
1024
+
sub r1, zero, r0
1025
+
}
1026
+
slt_u r29, r1, r29
1027
+
{
1028
+
mnz r1, r29, r1
1029
+
move r29, zero
1030
+
}
1021
1031
iret
1022
1032
1023
1033
/*
-1
arch/tile/kernel/proc.c
-1
arch/tile/kernel/proc.c
+2
-2
arch/tile/kernel/setup.c
+2
-2
arch/tile/kernel/setup.c
···
953
953
if (rc != stat.size) {
954
954
pr_err("Error reading %d bytes from hvfs file '%s': %d\n",
955
955
stat.size, initramfs_file, rc);
956
-
free_bootmem((unsigned long) initrd, stat.size);
956
+
free_initrd_mem((unsigned long) initrd, stat.size);
957
957
return;
958
958
}
959
959
initrd_start = (unsigned long) initrd;
···
962
962
963
963
void __init free_initrd_mem(unsigned long begin, unsigned long end)
964
964
{
965
-
free_bootmem(begin, end - begin);
965
+
free_bootmem(__pa(begin), end - begin);
966
966
}
967
967
968
968
static void __init validate_hv(void)
-8
arch/tile/kernel/stack.c
-8
arch/tile/kernel/stack.c
···
108
108
/* Return a pt_regs pointer for a valid fault handler frame */
109
109
static struct pt_regs *valid_fault_handler(struct KBacktraceIterator* kbt)
110
110
{
111
-
#ifndef __tilegx__
112
111
const char *fault = NULL; /* happy compiler */
113
112
char fault_buf[64];
114
113
VirtualAddress sp = kbt->it.sp;
···
145
146
}
146
147
if (!kbt->profile || (INT_MASK(p->faultnum) & QUEUED_INTERRUPTS) == 0)
147
148
return p;
148
-
#endif
149
149
return NULL;
150
150
}
151
151
···
349
351
kbt->task->pid, kbt->task->tgid, kbt->task->comm,
350
352
smp_processor_id(), get_cycles());
351
353
}
352
-
#ifdef __tilegx__
353
-
if (kbt->is_current) {
354
-
__insn_mtspr(SPR_SIM_CONTROL,
355
-
SIM_DUMP_SPR_ARG(SIM_DUMP_BACKTRACE));
356
-
}
357
-
#endif
358
354
kbt->verbose = 1;
359
355
i = 0;
360
356
for (; !KBacktraceIterator_end(kbt); KBacktraceIterator_next(kbt)) {
+19
-14
arch/tile/kernel/time.c
+19
-14
arch/tile/kernel/time.c
···
36
36
/* How many cycles per second we are running at. */
37
37
static cycles_t cycles_per_sec __write_once;
38
38
39
-
/*
40
-
* We set up shift and multiply values with a minsec of five seconds,
41
-
* since our timer counter counts down 31 bits at a frequency of
42
-
* no less than 500 MHz. See @minsec for clocks_calc_mult_shift().
43
-
* We could use a different value for the 64-bit free-running
44
-
* cycle counter, but we use the same one for consistency, and since
45
-
* we will be reasonably precise with this value anyway.
46
-
*/
47
-
#define TILE_MINSEC 5
48
-
49
39
cycles_t get_clock_rate(void)
50
40
{
51
41
return cycles_per_sec;
···
58
68
}
59
69
#endif
60
70
71
+
/*
72
+
* We use a relatively small shift value so that sched_clock()
73
+
* won't wrap around very often.
74
+
*/
75
+
#define SCHED_CLOCK_SHIFT 10
76
+
77
+
static unsigned long sched_clock_mult __write_once;
78
+
61
79
static cycles_t clocksource_get_cycles(struct clocksource *cs)
62
80
{
63
81
return get_cycles();
···
76
78
.rating = 300,
77
79
.read = clocksource_get_cycles,
78
80
.mask = CLOCKSOURCE_MASK(64),
81
+
.shift = 22, /* typical value, e.g. x86 tsc uses this */
79
82
.flags = CLOCK_SOURCE_IS_CONTINUOUS,
80
83
};
81
84
···
87
88
void __init setup_clock(void)
88
89
{
89
90
cycles_per_sec = hv_sysconf(HV_SYSCONF_CPU_SPEED);
90
-
clocksource_calc_mult_shift(&cycle_counter_cs, cycles_per_sec,
91
-
TILE_MINSEC);
91
+
sched_clock_mult =
92
+
clocksource_hz2mult(cycles_per_sec, SCHED_CLOCK_SHIFT);
93
+
cycle_counter_cs.mult =
94
+
clocksource_hz2mult(cycles_per_sec, cycle_counter_cs.shift);
92
95
}
93
96
94
97
void __init calibrate_delay(void)
···
118
117
* counter, plus bit 31, which signifies that the counter has wrapped
119
118
* from zero to (2**31) - 1. The INT_TILE_TIMER interrupt will be
120
119
* raised as long as bit 31 is set.
120
+
*
121
+
* The TILE_MINSEC value represents the largest range of real-time
122
+
* we can possibly cover with the timer, based on MAX_TICK combined
123
+
* with the slowest reasonable clock rate we might run at.
121
124
*/
122
125
123
126
#define MAX_TICK 0x7fffffff /* we have 31 bits of countdown timer */
127
+
#define TILE_MINSEC 5 /* timer covers no more than 5 seconds */
124
128
125
129
static int tile_timer_set_next_event(unsigned long ticks,
126
130
struct clock_event_device *evt)
···
217
211
unsigned long long sched_clock(void)
218
212
{
219
213
return clocksource_cyc2ns(get_cycles(),
220
-
cycle_counter_cs.mult,
221
-
cycle_counter_cs.shift);
214
+
sched_clock_mult, SCHED_CLOCK_SHIFT);
222
215
}
223
216
224
217
int setup_profiling_timer(unsigned int multiplier)
+3
-1
arch/tile/kernel/traps.c
+3
-1
arch/tile/kernel/traps.c
···
128
128
#ifdef __tilegx__
129
129
if ((bundle & TILEGX_BUNDLE_MODE_MASK) != 0)
130
130
return 0;
131
-
if (get_Opcode_X1(bundle) != UNARY_OPCODE_X1)
131
+
if (get_Opcode_X1(bundle) != RRR_0_OPCODE_X1)
132
+
return 0;
133
+
if (get_RRROpcodeExtension_X1(bundle) != UNARY_RRR_0_OPCODE_X1)
132
134
return 0;
133
135
if (get_UnaryOpcodeExtension_X1(bundle) != ILL_UNARY_OPCODE_X1)
134
136
return 0;
+3
-1
arch/tile/lib/Makefile
+3
-1
arch/tile/lib/Makefile
···
7
7
memcpy_$(BITS).o memchr_$(BITS).o memmove_$(BITS).o memset_$(BITS).o \
8
8
strchr_$(BITS).o strlen_$(BITS).o
9
9
10
-
ifneq ($(CONFIG_TILEGX),y)
10
+
ifeq ($(CONFIG_TILEGX),y)
11
+
lib-y += memcpy_user_64.o
12
+
else
11
13
lib-y += atomic_32.o atomic_asm_32.o memcpy_tile64.o
12
14
endif
13
15
+11
-5
arch/tile/lib/exports.c
+11
-5
arch/tile/lib/exports.c
···
36
36
EXPORT_SYMBOL(current_text_addr);
37
37
EXPORT_SYMBOL(dump_stack);
38
38
39
-
/* arch/tile/lib/__memcpy.S */
40
-
/* NOTE: on TILE64, these symbols appear in arch/tile/lib/memcpy_tile64.c */
39
+
/* arch/tile/lib/, various memcpy files */
41
40
EXPORT_SYMBOL(memcpy);
42
41
EXPORT_SYMBOL(__copy_to_user_inatomic);
43
42
EXPORT_SYMBOL(__copy_from_user_inatomic);
44
43
EXPORT_SYMBOL(__copy_from_user_zeroing);
44
+
#ifdef __tilegx__
45
+
EXPORT_SYMBOL(__copy_in_user_inatomic);
46
+
#endif
45
47
46
48
/* hypervisor glue */
47
49
#include <hv/hypervisor.h>
48
50
EXPORT_SYMBOL(hv_dev_open);
49
51
EXPORT_SYMBOL(hv_dev_pread);
50
52
EXPORT_SYMBOL(hv_dev_pwrite);
53
+
EXPORT_SYMBOL(hv_dev_preada);
54
+
EXPORT_SYMBOL(hv_dev_pwritea);
55
+
EXPORT_SYMBOL(hv_dev_poll);
56
+
EXPORT_SYMBOL(hv_dev_poll_cancel);
51
57
EXPORT_SYMBOL(hv_dev_close);
58
+
EXPORT_SYMBOL(hv_sysconf);
59
+
EXPORT_SYMBOL(hv_confstr);
52
60
53
-
/* -ltile-cc */
61
+
/* libgcc.a */
54
62
uint32_t __udivsi3(uint32_t dividend, uint32_t divisor);
55
63
EXPORT_SYMBOL(__udivsi3);
56
64
int32_t __divsi3(int32_t dividend, int32_t divisor);
···
78
70
#ifndef __tilegx__
79
71
uint64_t __ll_mul(uint64_t n0, uint64_t n1);
80
72
EXPORT_SYMBOL(__ll_mul);
81
-
#endif
82
-
#ifndef __tilegx__
83
73
int64_t __muldi3(int64_t, int64_t);
84
74
EXPORT_SYMBOL(__muldi3);
85
75
uint64_t __lshrdi3(uint64_t, unsigned int);
+4
-16
arch/tile/lib/memcpy_32.S
+4
-16
arch/tile/lib/memcpy_32.S
···
17
17
18
18
#include <arch/chip.h>
19
19
20
-
#if CHIP_HAS_WH64() || defined(MEMCPY_TEST_WH64)
21
-
#define MEMCPY_USE_WH64
22
-
#endif
23
-
24
20
25
21
#include <linux/linkage.h>
26
22
···
156
160
157
161
{ addi r3, r1, 60; andi r9, r9, -64 }
158
162
159
-
#ifdef MEMCPY_USE_WH64
163
+
#if CHIP_HAS_WH64()
160
164
/* No need to prefetch dst, we'll just do the wh64
161
165
* right before we copy a line.
162
166
*/
···
169
173
/* Intentionally stall for a few cycles to leave L2 cache alone. */
170
174
{ bnzt zero, . }
171
175
EX: { lw r7, r3; addi r3, r3, 64 }
172
-
#ifndef MEMCPY_USE_WH64
176
+
#if !CHIP_HAS_WH64()
173
177
/* Prefetch the dest */
174
178
/* Intentionally stall for a few cycles to leave L2 cache alone. */
175
179
{ bnzt zero, . }
···
284
288
/* Fill second L1D line. */
285
289
EX: { lw r17, r17; addi r1, r1, 48; mvz r3, r13, r1 } /* r17 = WORD_4 */
286
290
287
-
#ifdef MEMCPY_TEST_WH64
288
-
/* Issue a fake wh64 that clobbers the destination words
289
-
* with random garbage, for testing.
290
-
*/
291
-
{ movei r19, 64; crc32_32 r10, r2, r9 }
292
-
.Lwh64_test_loop:
293
-
EX: { sw r9, r10; addi r9, r9, 4; addi r19, r19, -4 }
294
-
{ bnzt r19, .Lwh64_test_loop; crc32_32 r10, r10, r19 }
295
-
#elif CHIP_HAS_WH64()
291
+
#if CHIP_HAS_WH64()
296
292
/* Prepare destination line for writing. */
297
293
EX: { wh64 r9; addi r9, r9, 64 }
298
294
#else
···
328
340
EX: { sw r0, r16; addi r0, r0, 4; add r16, r0, r2 } /* store(WORD_0) */
329
341
EX: { sw r0, r13; addi r0, r0, 4; andi r16, r16, -64 } /* store(WORD_1) */
330
342
EX: { sw r0, r14; addi r0, r0, 4; slt_u r16, r9, r16 } /* store(WORD_2) */
331
-
#ifdef MEMCPY_USE_WH64
343
+
#if CHIP_HAS_WH64()
332
344
EX: { sw r0, r15; addi r0, r0, 4; addi r13, sp, -64 } /* store(WORD_3) */
333
345
#else
334
346
/* Back up the r9 to a cache line we are already storing to
-25
arch/tile/lib/memset_32.c
-25
arch/tile/lib/memset_32.c
···
141
141
*/
142
142
__insn_prefetch(&out32[ahead32]);
143
143
144
-
#if 1
145
144
#if CACHE_LINE_SIZE_IN_WORDS % 4 != 0
146
145
#error "Unhandled CACHE_LINE_SIZE_IN_WORDS"
147
146
#endif
···
156
157
*out32++ = v32;
157
158
*out32++ = v32;
158
159
}
159
-
#else
160
-
/* Unfortunately, due to a code generator flaw this
161
-
* allocates a separate register for each of these
162
-
* stores, which requires a large number of spills,
163
-
* which makes this procedure enormously bigger
164
-
* (something like 70%)
165
-
*/
166
-
*out32++ = v32;
167
-
*out32++ = v32;
168
-
*out32++ = v32;
169
-
*out32++ = v32;
170
-
*out32++ = v32;
171
-
*out32++ = v32;
172
-
*out32++ = v32;
173
-
*out32++ = v32;
174
-
*out32++ = v32;
175
-
*out32++ = v32;
176
-
*out32++ = v32;
177
-
*out32++ = v32;
178
-
*out32++ = v32;
179
-
*out32++ = v32;
180
-
*out32++ = v32;
181
-
n32 -= 16;
182
-
#endif
183
160
184
161
/* To save compiled code size, reuse this loop even
185
162
* when we run out of prefetching to do by dropping
+8
arch/tile/mm/fault.c
+8
arch/tile/mm/fault.c
···
567
567
* since that might indicate we have not yet squirreled the SPR
568
568
* contents away and can thus safely take a recursive interrupt.
569
569
* Accordingly, the hypervisor passes us the PC via SYSTEM_SAVE_1_2.
570
+
*
571
+
* Note that this routine is called before homecache_tlb_defer_enter(),
572
+
* which means that we can properly unlock any atomics that might
573
+
* be used there (good), but also means we must be very sensitive
574
+
* to not touch any data structures that might be located in memory
575
+
* that could migrate, as we could be entering the kernel on a dataplane
576
+
* cpu that has been deferring kernel TLB updates. This means, for
577
+
* example, that we can't migrate init_mm or its pgd.
570
578
*/
571
579
struct intvec_state do_page_fault_ics(struct pt_regs *regs, int fault_num,
572
580
unsigned long address,
+2
-2
arch/tile/mm/highmem.c
+2
-2
arch/tile/mm/highmem.c
···
276
276
}
277
277
EXPORT_SYMBOL(kmap_atomic);
278
278
279
-
void kunmap_atomic(void *kvaddr, enum km_type type)
279
+
void kunmap_atomic_notypecheck(void *kvaddr, enum km_type type)
280
280
{
281
281
unsigned long vaddr = (unsigned long) kvaddr & PAGE_MASK;
282
282
enum fixed_addresses idx = type + KM_TYPE_NR*smp_processor_id();
···
300
300
arch_flush_lazy_mmu_mode();
301
301
pagefault_enable();
302
302
}
303
-
EXPORT_SYMBOL(kunmap_atomic);
303
+
EXPORT_SYMBOL(kunmap_atomic_notypecheck);
304
304
305
305
/*
306
306
* This API is supposed to allow us to map memory without a "struct page".
+3
arch/tile/mm/homecache.c
+3
arch/tile/mm/homecache.c
···
29
29
#include <linux/timex.h>
30
30
#include <linux/cache.h>
31
31
#include <linux/smp.h>
32
+
#include <linux/module.h>
32
33
33
34
#include <asm/page.h>
34
35
#include <asm/sections.h>
···
349
348
350
349
return pte;
351
350
}
351
+
EXPORT_SYMBOL(pte_set_home);
352
352
353
353
/*
354
354
* The routines in this section are the "static" versions of the normal
···
405
403
homecache_change_page_home(page, order, home);
406
404
return page;
407
405
}
406
+
EXPORT_SYMBOL(homecache_alloc_pages);
408
407
409
408
struct page *homecache_alloc_pages_node(int nid, gfp_t gfp_mask,
410
409
unsigned int order, int home)
-1
arch/tile/mm/pgtable.c
-1
arch/tile/mm/pgtable.c
+5
-1
include/asm-generic/unistd.h
+5
-1
include/asm-generic/unistd.h
···
642
642
__SYSCALL(__NR_wait4, sys_wait4)
643
643
#define __NR_prlimit64 261
644
644
__SYSCALL(__NR_prlimit64, sys_prlimit64)
645
+
#define __NR_fanotify_init 262
646
+
__SYSCALL(__NR_fanotify_init, sys_fanotify_init)
647
+
#define __NR_fanotify_mark 263
648
+
__SYSCALL(__NR_fanotify_mark, sys_fanotify_mark)
645
649
646
650
#undef __NR_syscalls
647
-
#define __NR_syscalls 262
651
+
#define __NR_syscalls 264
648
652
649
653
/*
650
654
* All syscalls below here should go away really,