Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
clk: qcom: clk-alpha-pll: Do not use random stack value for recalc rate
If regmap_read() fails, random stack value was used in calculating new
frequency in recalc_rate() callbacks. Such failure is really not
expected as these are all MMIO reads, however code should be here
correct and bail out. This also avoids possible warning on
uninitialized value.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250212-b4-clk-qcom-clean-v3-1-499f37444f5d@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
authored by
Krzysztof Kozlowski
and committed by
Bjorn Andersson
7a243e1b
b489235b
+36
-16
+36
-16
drivers/clk/qcom/clk-alpha-pll.c
+36
-16
drivers/clk/qcom/clk-alpha-pll.c
···
709
709
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
710
710
u32 alpha_width = pll_alpha_width(pll);
711
711
712
-
regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l);
712
+
if (regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l))
713
+
return 0;
713
714
714
-
regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl);
715
+
if (regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl))
716
+
return 0;
717
+
715
718
if (ctl & PLL_ALPHA_EN) {
716
-
regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &low);
719
+
if (regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &low))
720
+
return 0;
717
721
if (alpha_width > 32) {
718
-
regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll),
719
-
&high);
722
+
if (regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll),
723
+
&high))
724
+
return 0;
720
725
a = (u64)high << 32 | low;
721
726
} else {
722
727
a = low & GENMASK(alpha_width - 1, 0);
···
947
942
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
948
943
u32 l, alpha = 0, ctl, alpha_m, alpha_n;
949
944
950
-
regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l);
951
-
regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl);
945
+
if (regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l))
946
+
return 0;
947
+
948
+
if (regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl))
949
+
return 0;
952
950
953
951
if (ctl & PLL_ALPHA_EN) {
954
952
regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &alpha);
···
1145
1137
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1146
1138
u32 l, frac, alpha_width = pll_alpha_width(pll);
1147
1139
1148
-
regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l);
1149
-
regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &frac);
1140
+
if (regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l))
1141
+
return 0;
1142
+
1143
+
if (regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &frac))
1144
+
return 0;
1150
1145
1151
1146
return alpha_pll_calc_rate(parent_rate, l, frac, alpha_width);
1152
1147
}
···
1207
1196
struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1208
1197
u32 ctl;
1209
1198
1210
-
regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl);
1199
+
if (regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl))
1200
+
return 0;
1211
1201
1212
1202
ctl >>= PLL_POST_DIV_SHIFT;
1213
1203
ctl &= PLL_POST_DIV_MASK(pll);
···
1424
1412
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1425
1413
u32 l, frac, alpha_width = pll_alpha_width(pll);
1426
1414
1427
-
regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l);
1428
-
regmap_read(pll->clkr.regmap, PLL_FRAC(pll), &frac);
1415
+
if (regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l))
1416
+
return 0;
1417
+
1418
+
if (regmap_read(pll->clkr.regmap, PLL_FRAC(pll), &frac))
1419
+
return 0;
1429
1420
1430
1421
return alpha_pll_calc_rate(parent_rate, l, frac, alpha_width);
1431
1422
}
···
1578
1563
struct regmap *regmap = pll->clkr.regmap;
1579
1564
u32 i, div = 1, val;
1580
1565
1581
-
regmap_read(regmap, PLL_USER_CTL(pll), &val);
1566
+
if (regmap_read(regmap, PLL_USER_CTL(pll), &val))
1567
+
return 0;
1582
1568
1583
1569
val >>= pll->post_div_shift;
1584
1570
val &= PLL_POST_DIV_MASK(pll);
···
2500
2484
struct regmap *regmap = pll->clkr.regmap;
2501
2485
u32 l, frac;
2502
2486
2503
-
regmap_read(regmap, PLL_L_VAL(pll), &l);
2487
+
if (regmap_read(regmap, PLL_L_VAL(pll), &l))
2488
+
return 0;
2504
2489
l &= LUCID_EVO_PLL_L_VAL_MASK;
2505
-
regmap_read(regmap, PLL_ALPHA_VAL(pll), &frac);
2490
+
2491
+
if (regmap_read(regmap, PLL_ALPHA_VAL(pll), &frac))
2492
+
return 0;
2506
2493
2507
2494
return alpha_pll_calc_rate(parent_rate, l, frac, pll_alpha_width(pll));
2508
2495
}
···
2718
2699
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
2719
2700
u32 l;
2720
2701
2721
-
regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l);
2702
+
if (regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l))
2703
+
return 0;
2722
2704
2723
2705
return parent_rate * l;
2724
2706
}