spi: airoha: do not keep {tx,rx} dma buffer always mapped

DMA map txrx_buf on demand in airoha_snand_dirmap_read and
airoha_snand_dirmap_write routines and do not keep it always mapped.
This patch is not fixing any bug or introducing any functional change
to the driver, it just simplifies the code and improve code readability
without introducing any performance degradation according to the results
obtained from the mtd_speedtest kernel module test.

root@OpenWrt:# insmod mtd_test.ko
root@OpenWrt:# insmod mtd_speedtest.ko dev=5
[ 49.849869] =================================================
[ 49.855659] mtd_speedtest: MTD device: 5
[ 49.859583] mtd_speedtest: MTD device size 8388608, eraseblock size 131072, page size 2048, count of eraseblocks 64, pages per eraseblock 64, OOB size 128
[ 49.874622] mtd_test: scanning for bad eraseblocks
[ 49.879433] mtd_test: scanned 64 eraseblocks, 0 are bad
[ 50.106372] mtd_speedtest: testing eraseblock write speed
[ 53.083380] mtd_speedtest: eraseblock write speed is 2756 KiB/s
[ 53.089322] mtd_speedtest: testing eraseblock read speed
[ 54.143360] mtd_speedtest: eraseblock read speed is 7811 KiB/s
[ 54.370365] mtd_speedtest: testing page write speed
[ 57.349480] mtd_speedtest: page write speed is 2754 KiB/s
[ 57.354895] mtd_speedtest: testing page read speed
[ 58.410431] mtd_speedtest: page read speed is 7796 KiB/s
[ 58.636805] mtd_speedtest: testing 2 page write speed
[ 61.612427] mtd_speedtest: 2 page write speed is 2757 KiB/s
[ 61.618021] mtd_speedtest: testing 2 page read speed
[ 62.672653] mtd_speedtest: 2 page read speed is 7804 KiB/s
[ 62.678159] mtd_speedtest: Testing erase speed
[ 62.903617] mtd_speedtest: erase speed is 37063 KiB/s
[ 62.908678] mtd_speedtest: Testing 2x multi-block erase speed
[ 63.134083] mtd_speedtest: 2x multi-block erase speed is 37292 KiB/s
[ 63.140442] mtd_speedtest: Testing 4x multi-block erase speed
[ 63.364262] mtd_speedtest: 4x multi-block erase speed is 37566 KiB/s
[ 63.370632] mtd_speedtest: Testing 8x multi-block erase speed
[ 63.595740] mtd_speedtest: 8x multi-block erase speed is 37344 KiB/s
[ 63.602089] mtd_speedtest: Testing 16x multi-block erase speed
[ 63.827426] mtd_speedtest: 16x multi-block erase speed is 37320 KiB/s
[ 63.833860] mtd_speedtest: Testing 32x multi-block erase speed
[ 64.059389] mtd_speedtest: 32x multi-block erase speed is 37288 KiB/s
[ 64.065833] mtd_speedtest: Testing 64x multi-block erase speed
[ 64.290609] mtd_speedtest: 64x multi-block erase speed is 37415 KiB/s
[ 64.297063] mtd_speedtest: finished
[ 64.300555] =================================================

Tested-by: Christian Marangi <ansuelsmth@gmail.com>
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
Link: https://patch.msgid.link/20240922-airoha-spi-fixes-v3-1-f958802b3d68@kernel.org
Signed-off-by: Mark Brown <broonie@kernel.org>

authored by

Lorenzo Bianconi and committed by

Mark Brown 2 years ago 7a4b3ebf 759541d7

+71 -83

1 changed file

expand all

drivers

spi

spi-airoha-snfi.c

+71 -83

drivers/spi/spi-airoha-snfi.c

··· 206 206 SPI_CHIP_SEL_LOW, 207 207 }; 208 208 209 - struct airoha_snand_dev { 210 - size_t buf_len; 211 - 212 - u8 *txrx_buf; 213 - dma_addr_t dma_addr; 214 - }; 215 - 216 209 struct airoha_snand_ctrl { 217 210 struct device *dev; 218 211 struct regmap *regmap_ctrl; ··· 610 617 611 618 static int airoha_snand_dirmap_create(struct spi_mem_dirmap_desc *desc) 612 619 { 613 - struct airoha_snand_dev *as_dev = spi_get_ctldata(desc->mem->spi); 620 + u8 *txrx_buf = spi_get_ctldata(desc->mem->spi); 614 621 615 - if (!as_dev->txrx_buf) 622 + if (!txrx_buf) 616 623 return -EINVAL; 617 624 618 625 if (desc->info.offset + desc->info.length > U32_MAX) ··· 627 634 static ssize_t airoha_snand_dirmap_read(struct spi_mem_dirmap_desc *desc, 628 635 u64 offs, size_t len, void *buf) 629 636 { 630 - struct spi_device *spi = desc->mem->spi; 631 - struct airoha_snand_dev *as_dev = spi_get_ctldata(spi); 632 637 struct spi_mem_op *op = &desc->info.op_tmpl; 638 + struct spi_device *spi = desc->mem->spi; 633 639 struct airoha_snand_ctrl *as_ctrl; 640 + u8 *txrx_buf = spi_get_ctldata(spi); 641 + dma_addr_t dma_addr; 634 642 u32 val, rd_mode; 635 643 int err; 636 644 ··· 656 662 if (err) 657 663 return err; 658 664 659 - dma_sync_single_for_device(as_ctrl->dev, as_dev->dma_addr, 660 - as_dev->buf_len, DMA_BIDIRECTIONAL); 665 + dma_addr = dma_map_single(as_ctrl->dev, txrx_buf, SPI_NAND_CACHE_SIZE, 666 + DMA_FROM_DEVICE); 667 + err = dma_mapping_error(as_ctrl->dev, dma_addr); 668 + if (err) 669 + return err; 661 670 662 671 /* set dma addr */ 663 672 err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_STRADDR, 664 - as_dev->dma_addr); 673 + dma_addr); 665 674 if (err) 666 - return err; 675 + goto error_dma_unmap; 667 676 668 677 /* set cust sec size */ 669 678 val = as_ctrl->nfi_cfg.sec_size * as_ctrl->nfi_cfg.sec_num; ··· 675 678 REG_SPI_NFI_SNF_MISC_CTL2, 676 679 SPI_NFI_READ_DATA_BYTE_NUM, val); 677 680 if (err) 678 - return err; 681 + goto error_dma_unmap; 679 682 680 683 /* set read command */ 681 684 err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_RD_CTL2, 682 685 op->cmd.opcode); 683 686 if (err) 684 - return err; 687 + goto error_dma_unmap; 685 688 686 689 /* set read mode */ 687 690 err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_SNF_MISC_CTL, 688 691 FIELD_PREP(SPI_NFI_DATA_READ_WR_MODE, rd_mode)); 689 692 if (err) 690 - return err; 693 + goto error_dma_unmap; 691 694 692 695 /* set read addr */ 693 696 err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_RD_CTL3, 0x0); 694 697 if (err) 695 - return err; 698 + goto error_dma_unmap; 696 699 697 700 /* set nfi read */ 698 701 err = regmap_update_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CNFG, 699 702 SPI_NFI_OPMODE, 700 703 FIELD_PREP(SPI_NFI_OPMODE, 6)); 701 704 if (err) 702 - return err; 705 + goto error_dma_unmap; 703 706 704 707 err = regmap_set_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CNFG, 705 708 SPI_NFI_READ_MODE | SPI_NFI_DMA_MODE); 706 709 if (err) 707 - return err; 710 + goto error_dma_unmap; 708 711 709 712 err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_CMD, 0x0); 710 713 if (err) 711 - return err; 714 + goto error_dma_unmap; 712 715 713 716 /* trigger dma start read */ 714 717 err = regmap_clear_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CON, 715 718 SPI_NFI_RD_TRIG); 716 719 if (err) 717 - return err; 720 + goto error_dma_unmap; 718 721 719 722 err = regmap_set_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CON, 720 723 SPI_NFI_RD_TRIG); 721 724 if (err) 722 - return err; 725 + goto error_dma_unmap; 723 726 724 727 err = regmap_read_poll_timeout(as_ctrl->regmap_nfi, 725 728 REG_SPI_NFI_SNF_STA_CTL1, val, 726 729 (val & SPI_NFI_READ_FROM_CACHE_DONE), 727 730 0, 1 * USEC_PER_SEC); 728 731 if (err) 729 - return err; 732 + goto error_dma_unmap; 730 733 731 734 /* 732 735 * SPI_NFI_READ_FROM_CACHE_DONE bit must be written at the end ··· 736 739 SPI_NFI_READ_FROM_CACHE_DONE, 737 740 SPI_NFI_READ_FROM_CACHE_DONE); 738 741 if (err) 739 - return err; 742 + goto error_dma_unmap; 740 743 741 744 err = regmap_read_poll_timeout(as_ctrl->regmap_nfi, REG_SPI_NFI_INTR, 742 745 val, (val & SPI_NFI_AHB_DONE), 0, 743 746 1 * USEC_PER_SEC); 744 747 if (err) 745 - return err; 748 + goto error_dma_unmap; 746 749 747 750 /* DMA read need delay for data ready from controller to DRAM */ 748 751 udelay(1); 749 752 750 - dma_sync_single_for_cpu(as_ctrl->dev, as_dev->dma_addr, 751 - as_dev->buf_len, DMA_BIDIRECTIONAL); 753 + dma_unmap_single(as_ctrl->dev, dma_addr, SPI_NAND_CACHE_SIZE, 754 + DMA_FROM_DEVICE); 752 755 err = airoha_snand_set_mode(as_ctrl, SPI_MODE_MANUAL); 753 756 if (err < 0) 754 757 return err; 755 758 756 - memcpy(buf, as_dev->txrx_buf + offs, len); 759 + memcpy(buf, txrx_buf + offs, len); 757 760 758 761 return len; 762 + 763 + error_dma_unmap: 764 + dma_unmap_single(as_ctrl->dev, dma_addr, SPI_NAND_CACHE_SIZE, 765 + DMA_FROM_DEVICE); 766 + return err; 759 767 } 760 768 761 769 static ssize_t airoha_snand_dirmap_write(struct spi_mem_dirmap_desc *desc, 762 770 u64 offs, size_t len, const void *buf) 763 771 { 764 - struct spi_device *spi = desc->mem->spi; 765 - struct airoha_snand_dev *as_dev = spi_get_ctldata(spi); 766 772 struct spi_mem_op *op = &desc->info.op_tmpl; 773 + struct spi_device *spi = desc->mem->spi; 774 + u8 *txrx_buf = spi_get_ctldata(spi); 767 775 struct airoha_snand_ctrl *as_ctrl; 776 + dma_addr_t dma_addr; 768 777 u32 wr_mode, val; 769 778 int err; 770 779 ··· 779 776 if (err < 0) 780 777 return err; 781 778 782 - dma_sync_single_for_cpu(as_ctrl->dev, as_dev->dma_addr, 783 - as_dev->buf_len, DMA_BIDIRECTIONAL); 784 - memcpy(as_dev->txrx_buf + offs, buf, len); 785 - dma_sync_single_for_device(as_ctrl->dev, as_dev->dma_addr, 786 - as_dev->buf_len, DMA_BIDIRECTIONAL); 779 + memcpy(txrx_buf + offs, buf, len); 780 + dma_addr = dma_map_single(as_ctrl->dev, txrx_buf, SPI_NAND_CACHE_SIZE, 781 + DMA_TO_DEVICE); 782 + err = dma_mapping_error(as_ctrl->dev, dma_addr); 783 + if (err) 784 + return err; 787 785 788 786 err = airoha_snand_set_mode(as_ctrl, SPI_MODE_DMA); 789 787 if (err < 0) 790 - return err; 788 + goto error_dma_unmap; 791 789 792 790 err = airoha_snand_nfi_config(as_ctrl); 793 791 if (err) 794 - return err; 792 + goto error_dma_unmap; 795 793 796 794 if (op->cmd.opcode == SPI_NAND_OP_PROGRAM_LOAD_QUAD || 797 795 op->cmd.opcode == SPI_NAND_OP_PROGRAM_LOAD_RAMDON_QUAD) ··· 801 797 wr_mode = 0; 802 798 803 799 err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_STRADDR, 804 - as_dev->dma_addr); 800 + dma_addr); 805 801 if (err) 806 - return err; 802 + goto error_dma_unmap; 807 803 808 804 val = FIELD_PREP(SPI_NFI_PROG_LOAD_BYTE_NUM, 809 805 as_ctrl->nfi_cfg.sec_size * as_ctrl->nfi_cfg.sec_num); ··· 811 807 REG_SPI_NFI_SNF_MISC_CTL2, 812 808 SPI_NFI_PROG_LOAD_BYTE_NUM, val); 813 809 if (err) 814 - return err; 810 + goto error_dma_unmap; 815 811 816 812 err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_PG_CTL1, 817 813 FIELD_PREP(SPI_NFI_PG_LOAD_CMD, 818 814 op->cmd.opcode)); 819 815 if (err) 820 - return err; 816 + goto error_dma_unmap; 821 817 822 818 err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_SNF_MISC_CTL, 823 819 FIELD_PREP(SPI_NFI_DATA_READ_WR_MODE, wr_mode)); 824 820 if (err) 825 - return err; 821 + goto error_dma_unmap; 826 822 827 823 err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_PG_CTL2, 0x0); 828 824 if (err) 829 - return err; 825 + goto error_dma_unmap; 830 826 831 827 err = regmap_clear_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CNFG, 832 828 SPI_NFI_READ_MODE); 833 829 if (err) 834 - return err; 830 + goto error_dma_unmap; 835 831 836 832 err = regmap_update_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CNFG, 837 833 SPI_NFI_OPMODE, 838 834 FIELD_PREP(SPI_NFI_OPMODE, 3)); 839 835 if (err) 840 - return err; 836 + goto error_dma_unmap; 841 837 842 838 err = regmap_set_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CNFG, 843 839 SPI_NFI_DMA_MODE); 844 840 if (err) 845 - return err; 841 + goto error_dma_unmap; 846 842 847 843 err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_CMD, 0x80); 848 844 if (err) 849 - return err; 845 + goto error_dma_unmap; 850 846 851 847 err = regmap_clear_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CON, 852 848 SPI_NFI_WR_TRIG); 853 849 if (err) 854 - return err; 850 + goto error_dma_unmap; 855 851 856 852 err = regmap_set_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CON, 857 853 SPI_NFI_WR_TRIG); 858 854 if (err) 859 - return err; 855 + goto error_dma_unmap; 860 856 861 857 err = regmap_read_poll_timeout(as_ctrl->regmap_nfi, REG_SPI_NFI_INTR, 862 858 val, (val & SPI_NFI_AHB_DONE), 0, 863 859 1 * USEC_PER_SEC); 864 860 if (err) 865 - return err; 861 + goto error_dma_unmap; 866 862 867 863 err = regmap_read_poll_timeout(as_ctrl->regmap_nfi, 868 864 REG_SPI_NFI_SNF_STA_CTL1, val, 869 865 (val & SPI_NFI_LOAD_TO_CACHE_DONE), 870 866 0, 1 * USEC_PER_SEC); 871 867 if (err) 872 - return err; 868 + goto error_dma_unmap; 873 869 874 870 /* 875 871 * SPI_NFI_LOAD_TO_CACHE_DONE bit must be written at the end ··· 879 875 SPI_NFI_LOAD_TO_CACHE_DONE, 880 876 SPI_NFI_LOAD_TO_CACHE_DONE); 881 877 if (err) 882 - return err; 878 + goto error_dma_unmap; 883 879 880 + dma_unmap_single(as_ctrl->dev, dma_addr, SPI_NAND_CACHE_SIZE, 881 + DMA_TO_DEVICE); 884 882 err = airoha_snand_set_mode(as_ctrl, SPI_MODE_MANUAL); 885 883 if (err < 0) 886 884 return err; 887 885 888 886 return len; 887 + 888 + error_dma_unmap: 889 + dma_unmap_single(as_ctrl->dev, dma_addr, SPI_NAND_CACHE_SIZE, 890 + DMA_TO_DEVICE); 891 + return err; 889 892 } 890 893 891 894 static int airoha_snand_exec_op(struct spi_mem *mem, ··· 967 956 static int airoha_snand_setup(struct spi_device *spi) 968 957 { 969 958 struct airoha_snand_ctrl *as_ctrl; 970 - struct airoha_snand_dev *as_dev; 971 - 972 - as_ctrl = spi_controller_get_devdata(spi->controller); 973 - 974 - as_dev = devm_kzalloc(as_ctrl->dev, sizeof(*as_dev), GFP_KERNEL); 975 - if (!as_dev) 976 - return -ENOMEM; 959 + u8 *txrx_buf; 977 960 978 961 /* prepare device buffer */ 979 - as_dev->buf_len = SPI_NAND_CACHE_SIZE; 980 - as_dev->txrx_buf = devm_kzalloc(as_ctrl->dev, as_dev->buf_len, 981 - GFP_KERNEL); 982 - if (!as_dev->txrx_buf) 962 + as_ctrl = spi_controller_get_devdata(spi->controller); 963 + txrx_buf = devm_kzalloc(as_ctrl->dev, SPI_NAND_CACHE_SIZE, 964 + GFP_KERNEL); 965 + if (!txrx_buf) 983 966 return -ENOMEM; 984 967 985 - as_dev->dma_addr = dma_map_single(as_ctrl->dev, as_dev->txrx_buf, 986 - as_dev->buf_len, DMA_BIDIRECTIONAL); 987 - if (dma_mapping_error(as_ctrl->dev, as_dev->dma_addr)) 988 - return -ENOMEM; 989 - 990 - spi_set_ctldata(spi, as_dev); 968 + spi_set_ctldata(spi, txrx_buf); 991 969 992 970 return 0; 993 - } 994 - 995 - static void airoha_snand_cleanup(struct spi_device *spi) 996 - { 997 - struct airoha_snand_dev *as_dev = spi_get_ctldata(spi); 998 - struct airoha_snand_ctrl *as_ctrl; 999 - 1000 - as_ctrl = spi_controller_get_devdata(spi->controller); 1001 - dma_unmap_single(as_ctrl->dev, as_dev->dma_addr, 1002 - as_dev->buf_len, DMA_BIDIRECTIONAL); 1003 - spi_set_ctldata(spi, NULL); 1004 971 } 1005 972 1006 973 static int airoha_snand_nfi_setup(struct airoha_snand_ctrl *as_ctrl) ··· 1082 1093 ctrl->bits_per_word_mask = SPI_BPW_MASK(8); 1083 1094 ctrl->mode_bits = SPI_RX_DUAL; 1084 1095 ctrl->setup = airoha_snand_setup; 1085 - ctrl->cleanup = airoha_snand_cleanup; 1086 1096 device_set_node(&ctrl->dev, dev_fwnode(dev)); 1087 1097 1088 1098 err = airoha_snand_nfi_setup(as_ctrl);

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