Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'gpio-fixes-for-v5.19-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux
Pull gpio fixes from Bartosz Golaszewski:
"A set of fixes. Most address the new warning we emit at build time
when irq chips are not immutable with some additional tweaks to
gpio-crystalcove from Andy and a small tweak to gpio-dwapd.
- make irq_chip structs immutable in several Diolan and intel drivers
to get rid of the new warning we emit when fiddling with irq chips
- don't print error messages on probe deferral in gpio-dwapb"
* tag 'gpio-fixes-for-v5.19-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux:
gpio: dwapb: Don't print error on -EPROBE_DEFER
gpio: dln2: make irq_chip immutable
gpio: sch: make irq_chip immutable
gpio: merrifield: make irq_chip immutable
gpio: wcove: make irq_chip immutable
gpio: crystalcove: Join function declarations and long lines
gpio: crystalcove: Use specific type and API for IRQ number
gpio: crystalcove: make irq_chip immutable
+99
-68
+37
-33
drivers/gpio/gpio-crystalcove.c
+37
-33
drivers/gpio/gpio-crystalcove.c
···
15
15
#include <linux/platform_device.h>
16
16
#include <linux/regmap.h>
17
17
#include <linux/seq_file.h>
18
+
#include <linux/types.h>
18
19
19
20
#define CRYSTALCOVE_GPIO_NUM 16
20
21
#define CRYSTALCOVE_VGPIO_NUM 95
···
111
110
return reg + gpio % 8;
112
111
}
113
112
114
-
static void crystalcove_update_irq_mask(struct crystalcove_gpio *cg,
115
-
int gpio)
113
+
static void crystalcove_update_irq_mask(struct crystalcove_gpio *cg, int gpio)
116
114
{
117
115
u8 mirqs0 = gpio < 8 ? MGPIO0IRQS0 : MGPIO1IRQS0;
118
116
int mask = BIT(gpio % 8);
···
140
140
return regmap_write(cg->regmap, reg, CTLO_INPUT_SET);
141
141
}
142
142
143
-
static int crystalcove_gpio_dir_out(struct gpio_chip *chip, unsigned int gpio,
144
-
int value)
143
+
static int crystalcove_gpio_dir_out(struct gpio_chip *chip, unsigned int gpio, int value)
145
144
{
146
145
struct crystalcove_gpio *cg = gpiochip_get_data(chip);
147
146
int reg = to_reg(gpio, CTRL_OUT);
···
167
168
return val & 0x1;
168
169
}
169
170
170
-
static void crystalcove_gpio_set(struct gpio_chip *chip,
171
-
unsigned int gpio, int value)
171
+
static void crystalcove_gpio_set(struct gpio_chip *chip, unsigned int gpio, int value)
172
172
{
173
173
struct crystalcove_gpio *cg = gpiochip_get_data(chip);
174
174
int reg = to_reg(gpio, CTRL_OUT);
···
183
185
184
186
static int crystalcove_irq_type(struct irq_data *data, unsigned int type)
185
187
{
186
-
struct crystalcove_gpio *cg =
187
-
gpiochip_get_data(irq_data_get_irq_chip_data(data));
188
+
struct crystalcove_gpio *cg = gpiochip_get_data(irq_data_get_irq_chip_data(data));
189
+
irq_hw_number_t hwirq = irqd_to_hwirq(data);
188
190
189
-
if (data->hwirq >= CRYSTALCOVE_GPIO_NUM)
191
+
if (hwirq >= CRYSTALCOVE_GPIO_NUM)
190
192
return 0;
191
193
192
194
switch (type) {
···
213
215
214
216
static void crystalcove_bus_lock(struct irq_data *data)
215
217
{
216
-
struct crystalcove_gpio *cg =
217
-
gpiochip_get_data(irq_data_get_irq_chip_data(data));
218
+
struct crystalcove_gpio *cg = gpiochip_get_data(irq_data_get_irq_chip_data(data));
218
219
219
220
mutex_lock(&cg->buslock);
220
221
}
221
222
222
223
static void crystalcove_bus_sync_unlock(struct irq_data *data)
223
224
{
224
-
struct crystalcove_gpio *cg =
225
-
gpiochip_get_data(irq_data_get_irq_chip_data(data));
226
-
int gpio = data->hwirq;
225
+
struct crystalcove_gpio *cg = gpiochip_get_data(irq_data_get_irq_chip_data(data));
226
+
irq_hw_number_t hwirq = irqd_to_hwirq(data);
227
227
228
228
if (cg->update & UPDATE_IRQ_TYPE)
229
-
crystalcove_update_irq_ctrl(cg, gpio);
229
+
crystalcove_update_irq_ctrl(cg, hwirq);
230
230
if (cg->update & UPDATE_IRQ_MASK)
231
-
crystalcove_update_irq_mask(cg, gpio);
231
+
crystalcove_update_irq_mask(cg, hwirq);
232
232
cg->update = 0;
233
233
234
234
mutex_unlock(&cg->buslock);
···
234
238
235
239
static void crystalcove_irq_unmask(struct irq_data *data)
236
240
{
237
-
struct crystalcove_gpio *cg =
238
-
gpiochip_get_data(irq_data_get_irq_chip_data(data));
241
+
struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
242
+
struct crystalcove_gpio *cg = gpiochip_get_data(gc);
243
+
irq_hw_number_t hwirq = irqd_to_hwirq(data);
239
244
240
-
if (data->hwirq < CRYSTALCOVE_GPIO_NUM) {
241
-
cg->set_irq_mask = false;
242
-
cg->update |= UPDATE_IRQ_MASK;
243
-
}
245
+
if (hwirq >= CRYSTALCOVE_GPIO_NUM)
246
+
return;
247
+
248
+
gpiochip_enable_irq(gc, hwirq);
249
+
250
+
cg->set_irq_mask = false;
251
+
cg->update |= UPDATE_IRQ_MASK;
244
252
}
245
253
246
254
static void crystalcove_irq_mask(struct irq_data *data)
247
255
{
248
-
struct crystalcove_gpio *cg =
249
-
gpiochip_get_data(irq_data_get_irq_chip_data(data));
256
+
struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
257
+
struct crystalcove_gpio *cg = gpiochip_get_data(gc);
258
+
irq_hw_number_t hwirq = irqd_to_hwirq(data);
250
259
251
-
if (data->hwirq < CRYSTALCOVE_GPIO_NUM) {
252
-
cg->set_irq_mask = true;
253
-
cg->update |= UPDATE_IRQ_MASK;
254
-
}
260
+
if (hwirq >= CRYSTALCOVE_GPIO_NUM)
261
+
return;
262
+
263
+
cg->set_irq_mask = true;
264
+
cg->update |= UPDATE_IRQ_MASK;
265
+
266
+
gpiochip_disable_irq(gc, hwirq);
255
267
}
256
268
257
-
static struct irq_chip crystalcove_irqchip = {
269
+
static const struct irq_chip crystalcove_irqchip = {
258
270
.name = "Crystal Cove",
259
271
.irq_mask = crystalcove_irq_mask,
260
272
.irq_unmask = crystalcove_irq_unmask,
261
273
.irq_set_type = crystalcove_irq_type,
262
274
.irq_bus_lock = crystalcove_bus_lock,
263
275
.irq_bus_sync_unlock = crystalcove_bus_sync_unlock,
264
-
.flags = IRQCHIP_SKIP_SET_WAKE,
276
+
.flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_IMMUTABLE,
277
+
GPIOCHIP_IRQ_RESOURCE_HELPERS,
265
278
};
266
279
267
280
static irqreturn_t crystalcove_gpio_irq_handler(int irq, void *data)
···
298
293
return IRQ_HANDLED;
299
294
}
300
295
301
-
static void crystalcove_gpio_dbg_show(struct seq_file *s,
302
-
struct gpio_chip *chip)
296
+
static void crystalcove_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
303
297
{
304
298
struct crystalcove_gpio *cg = gpiochip_get_data(chip);
305
299
int gpio, offset;
···
357
353
cg->regmap = pmic->regmap;
358
354
359
355
girq = &cg->chip.irq;
360
-
girq->chip = &crystalcove_irqchip;
356
+
gpio_irq_chip_set_chip(girq, &crystalcove_irqchip);
361
357
/* This will let us handle the parent IRQ in the driver */
362
358
girq->parent_handler = NULL;
363
359
girq->num_parents = 0;
+14
-9
drivers/gpio/gpio-dln2.c
+14
-9
drivers/gpio/gpio-dln2.c
···
46
46
struct dln2_gpio {
47
47
struct platform_device *pdev;
48
48
struct gpio_chip gpio;
49
-
struct irq_chip irqchip;
50
49
51
50
/*
52
51
* Cache pin direction to save us one transfer, since the hardware has
···
305
306
struct dln2_gpio *dln2 = gpiochip_get_data(gc);
306
307
int pin = irqd_to_hwirq(irqd);
307
308
309
+
gpiochip_enable_irq(gc, pin);
308
310
set_bit(pin, dln2->unmasked_irqs);
309
311
}
310
312
···
316
316
int pin = irqd_to_hwirq(irqd);
317
317
318
318
clear_bit(pin, dln2->unmasked_irqs);
319
+
gpiochip_disable_irq(gc, pin);
319
320
}
320
321
321
322
static int dln2_irq_set_type(struct irq_data *irqd, unsigned type)
···
384
383
385
384
mutex_unlock(&dln2->irq_lock);
386
385
}
386
+
387
+
static const struct irq_chip dln2_irqchip = {
388
+
.name = "dln2-irq",
389
+
.irq_mask = dln2_irq_mask,
390
+
.irq_unmask = dln2_irq_unmask,
391
+
.irq_set_type = dln2_irq_set_type,
392
+
.irq_bus_lock = dln2_irq_bus_lock,
393
+
.irq_bus_sync_unlock = dln2_irq_bus_unlock,
394
+
.flags = IRQCHIP_IMMUTABLE,
395
+
GPIOCHIP_IRQ_RESOURCE_HELPERS,
396
+
};
387
397
388
398
static void dln2_gpio_event(struct platform_device *pdev, u16 echo,
389
399
const void *data, int len)
···
477
465
dln2->gpio.direction_output = dln2_gpio_direction_output;
478
466
dln2->gpio.set_config = dln2_gpio_set_config;
479
467
480
-
dln2->irqchip.name = "dln2-irq",
481
-
dln2->irqchip.irq_mask = dln2_irq_mask,
482
-
dln2->irqchip.irq_unmask = dln2_irq_unmask,
483
-
dln2->irqchip.irq_set_type = dln2_irq_set_type,
484
-
dln2->irqchip.irq_bus_lock = dln2_irq_bus_lock,
485
-
dln2->irqchip.irq_bus_sync_unlock = dln2_irq_bus_unlock,
486
-
487
468
girq = &dln2->gpio.irq;
488
-
girq->chip = &dln2->irqchip;
469
+
gpio_irq_chip_set_chip(girq, &dln2_irqchip);
489
470
/* The event comes from the outside so no parent handler */
490
471
girq->parent_handler = NULL;
491
472
girq->num_parents = 0;
+3
-4
drivers/gpio/gpio-dwapb.c
+3
-4
drivers/gpio/gpio-dwapb.c
···
662
662
gpio->clks[1].id = "db";
663
663
err = devm_clk_bulk_get_optional(gpio->dev, DWAPB_NR_CLOCKS,
664
664
gpio->clks);
665
-
if (err) {
666
-
dev_err(gpio->dev, "Cannot get APB/Debounce clocks\n");
667
-
return err;
668
-
}
665
+
if (err)
666
+
return dev_err_probe(gpio->dev, err,
667
+
"Cannot get APB/Debounce clocks\n");
669
668
670
669
err = clk_bulk_prepare_enable(DWAPB_NR_CLOCKS, gpio->clks);
671
670
if (err) {
+15
-7
drivers/gpio/gpio-merrifield.c
+15
-7
drivers/gpio/gpio-merrifield.c
···
220
220
raw_spin_unlock_irqrestore(&priv->lock, flags);
221
221
}
222
222
223
-
static void mrfld_irq_unmask_mask(struct irq_data *d, bool unmask)
223
+
static void mrfld_irq_unmask_mask(struct mrfld_gpio *priv, u32 gpio, bool unmask)
224
224
{
225
-
struct mrfld_gpio *priv = irq_data_get_irq_chip_data(d);
226
-
u32 gpio = irqd_to_hwirq(d);
227
225
void __iomem *gimr = gpio_reg(&priv->chip, gpio, GIMR);
228
226
unsigned long flags;
229
227
u32 value;
···
239
241
240
242
static void mrfld_irq_mask(struct irq_data *d)
241
243
{
242
-
mrfld_irq_unmask_mask(d, false);
244
+
struct mrfld_gpio *priv = irq_data_get_irq_chip_data(d);
245
+
u32 gpio = irqd_to_hwirq(d);
246
+
247
+
mrfld_irq_unmask_mask(priv, gpio, false);
248
+
gpiochip_disable_irq(&priv->chip, gpio);
243
249
}
244
250
245
251
static void mrfld_irq_unmask(struct irq_data *d)
246
252
{
247
-
mrfld_irq_unmask_mask(d, true);
253
+
struct mrfld_gpio *priv = irq_data_get_irq_chip_data(d);
254
+
u32 gpio = irqd_to_hwirq(d);
255
+
256
+
gpiochip_enable_irq(&priv->chip, gpio);
257
+
mrfld_irq_unmask_mask(priv, gpio, true);
248
258
}
249
259
250
260
static int mrfld_irq_set_type(struct irq_data *d, unsigned int type)
···
335
329
return 0;
336
330
}
337
331
338
-
static struct irq_chip mrfld_irqchip = {
332
+
static const struct irq_chip mrfld_irqchip = {
339
333
.name = "gpio-merrifield",
340
334
.irq_ack = mrfld_irq_ack,
341
335
.irq_mask = mrfld_irq_mask,
342
336
.irq_unmask = mrfld_irq_unmask,
343
337
.irq_set_type = mrfld_irq_set_type,
344
338
.irq_set_wake = mrfld_irq_set_wake,
339
+
.flags = IRQCHIP_IMMUTABLE,
340
+
GPIOCHIP_IRQ_RESOURCE_HELPERS,
345
341
};
346
342
347
343
static void mrfld_irq_handler(struct irq_desc *desc)
···
490
482
return retval;
491
483
492
484
girq = &priv->chip.irq;
493
-
girq->chip = &mrfld_irqchip;
485
+
gpio_irq_chip_set_chip(girq, &mrfld_irqchip);
494
486
girq->init_hw = mrfld_irq_init_hw;
495
487
girq->parent_handler = mrfld_irq_handler;
496
488
girq->num_parents = 1;
+22
-13
drivers/gpio/gpio-sch.c
+22
-13
drivers/gpio/gpio-sch.c
···
38
38
39
39
struct sch_gpio {
40
40
struct gpio_chip chip;
41
-
struct irq_chip irqchip;
42
41
spinlock_t lock;
43
42
unsigned short iobase;
44
43
unsigned short resume_base;
···
217
218
spin_unlock_irqrestore(&sch->lock, flags);
218
219
}
219
220
220
-
static void sch_irq_mask_unmask(struct irq_data *d, int val)
221
+
static void sch_irq_mask_unmask(struct gpio_chip *gc, irq_hw_number_t gpio_num, int val)
221
222
{
222
-
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
223
223
struct sch_gpio *sch = gpiochip_get_data(gc);
224
-
irq_hw_number_t gpio_num = irqd_to_hwirq(d);
225
224
unsigned long flags;
226
225
227
226
spin_lock_irqsave(&sch->lock, flags);
···
229
232
230
233
static void sch_irq_mask(struct irq_data *d)
231
234
{
232
-
sch_irq_mask_unmask(d, 0);
235
+
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
236
+
irq_hw_number_t gpio_num = irqd_to_hwirq(d);
237
+
238
+
sch_irq_mask_unmask(gc, gpio_num, 0);
239
+
gpiochip_disable_irq(gc, gpio_num);
233
240
}
234
241
235
242
static void sch_irq_unmask(struct irq_data *d)
236
243
{
237
-
sch_irq_mask_unmask(d, 1);
244
+
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
245
+
irq_hw_number_t gpio_num = irqd_to_hwirq(d);
246
+
247
+
gpiochip_enable_irq(gc, gpio_num);
248
+
sch_irq_mask_unmask(gc, gpio_num, 1);
238
249
}
250
+
251
+
static const struct irq_chip sch_irqchip = {
252
+
.name = "sch_gpio",
253
+
.irq_ack = sch_irq_ack,
254
+
.irq_mask = sch_irq_mask,
255
+
.irq_unmask = sch_irq_unmask,
256
+
.irq_set_type = sch_irq_type,
257
+
.flags = IRQCHIP_IMMUTABLE,
258
+
GPIOCHIP_IRQ_RESOURCE_HELPERS,
259
+
};
239
260
240
261
static u32 sch_gpio_gpe_handler(acpi_handle gpe_device, u32 gpe, void *context)
241
262
{
···
382
367
383
368
platform_set_drvdata(pdev, sch);
384
369
385
-
sch->irqchip.name = "sch_gpio";
386
-
sch->irqchip.irq_ack = sch_irq_ack;
387
-
sch->irqchip.irq_mask = sch_irq_mask;
388
-
sch->irqchip.irq_unmask = sch_irq_unmask;
389
-
sch->irqchip.irq_set_type = sch_irq_type;
390
-
391
370
girq = &sch->chip.irq;
392
-
girq->chip = &sch->irqchip;
371
+
gpio_irq_chip_set_chip(girq, &sch_irqchip);
393
372
girq->num_parents = 0;
394
373
girq->parents = NULL;
395
374
girq->parent_handler = NULL;
+8
-2
drivers/gpio/gpio-wcove.c
+8
-2
drivers/gpio/gpio-wcove.c
···
299
299
if (gpio >= WCOVE_GPIO_NUM)
300
300
return;
301
301
302
+
gpiochip_enable_irq(chip, gpio);
303
+
302
304
wg->set_irq_mask = false;
303
305
wg->update |= UPDATE_IRQ_MASK;
304
306
}
···
316
314
317
315
wg->set_irq_mask = true;
318
316
wg->update |= UPDATE_IRQ_MASK;
317
+
318
+
gpiochip_disable_irq(chip, gpio);
319
319
}
320
320
321
-
static struct irq_chip wcove_irqchip = {
321
+
static const struct irq_chip wcove_irqchip = {
322
322
.name = "Whiskey Cove",
323
323
.irq_mask = wcove_irq_mask,
324
324
.irq_unmask = wcove_irq_unmask,
325
325
.irq_set_type = wcove_irq_type,
326
326
.irq_bus_lock = wcove_bus_lock,
327
327
.irq_bus_sync_unlock = wcove_bus_sync_unlock,
328
+
.flags = IRQCHIP_IMMUTABLE,
329
+
GPIOCHIP_IRQ_RESOURCE_HELPERS,
328
330
};
329
331
330
332
static irqreturn_t wcove_gpio_irq_handler(int irq, void *data)
···
458
452
}
459
453
460
454
girq = &wg->chip.irq;
461
-
girq->chip = &wcove_irqchip;
455
+
gpio_irq_chip_set_chip(girq, &wcove_irqchip);
462
456
/* This will let us handle the parent IRQ in the driver */
463
457
girq->parent_handler = NULL;
464
458
girq->num_parents = 0;