tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
1
fork

Configure Feed

Select the types of activity you want to include in your feed.

Merge tag 'pwm/for-6.2-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/thierry.reding/linux-pwm

Pull pwm updates from Thierry Reding:
"Various changes across the board, mostly improvements and cleanups"

* tag 'pwm/for-6.2-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/thierry.reding/linux-pwm: (42 commits)
pwm: pca9685: Convert to i2c's .probe_new()
pwm: sun4i: Propagate errors in .get_state() to the caller
pwm: Handle .get_state() failures
pwm: sprd: Propagate errors in .get_state() to the caller
pwm: rockchip: Propagate errors in .get_state() to the caller
pwm: mtk-disp: Propagate errors in .get_state() to the caller
pwm: imx27: Propagate errors in .get_state() to the caller
pwm: cros-ec: Propagate errors in .get_state() to the caller
pwm: crc: Propagate errors in .get_state() to the caller
leds: qcom-lpg: Propagate errors in .get_state() to the caller
drm/bridge: ti-sn65dsi86: Propagate errors in .get_state() to the caller
pwm/tracing: Also record trace events for failed API calls
pwm: Make .get_state() callback return an error code
pwm: pxa: Enable for MMP platform
pwm: pxa: Add reference manual link and limitations
pwm: pxa: Use abrupt shutdown mode
pwm: pxa: Remove clk enable/disable from pxa_pwm_config
pwm: pxa: Set duty cycle to 0 when disabling PWM
pwm: pxa: Remove pxa_pwm_enable/disable
pwm: mediatek: Add support for MT7986
...

Linus Torvalds 7a693ea7 9cf5b508

+300 -230
+1
Documentation/devicetree/bindings/pwm/renesas,pwm-rcar.yaml
··· 35 35 - renesas,pwm-r8a77980 # R-Car V3H 36 36 - renesas,pwm-r8a77990 # R-Car E3 37 37 - renesas,pwm-r8a77995 # R-Car D3 38 + - renesas,pwm-r8a779g0 # R-Car V4H 38 39 - const: renesas,pwm-rcar 39 40 40 41 reg:
+1
Documentation/devicetree/bindings/pwm/renesas,tpu-pwm.yaml
··· 40 40 - renesas,tpu-r8a77970 # R-Car V3M 41 41 - renesas,tpu-r8a77980 # R-Car V3H 42 42 - renesas,tpu-r8a779a0 # R-Car V3U 43 + - renesas,tpu-r8a779g0 # R-Car V4H 43 44 - const: renesas,tpu 44 45 45 46 reg:
+6 -3
drivers/gpio/gpio-mvebu.c
··· 657 657 spin_unlock_irqrestore(&mvpwm->lock, flags); 658 658 } 659 659 660 - static void mvebu_pwm_get_state(struct pwm_chip *chip, 661 - struct pwm_device *pwm, 662 - struct pwm_state *state) { 660 + static int mvebu_pwm_get_state(struct pwm_chip *chip, 661 + struct pwm_device *pwm, 662 + struct pwm_state *state) 663 + { 663 664 664 665 struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip); 665 666 struct mvebu_gpio_chip *mvchip = mvpwm->mvchip; ··· 694 693 state->enabled = false; 695 694 696 695 spin_unlock_irqrestore(&mvpwm->lock, flags); 696 + 697 + return 0; 697 698 } 698 699 699 700 static int mvebu_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
+8 -6
drivers/gpu/drm/bridge/ti-sn65dsi86.c
··· 1500 1500 return ret; 1501 1501 } 1502 1502 1503 - static void ti_sn_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, 1504 - struct pwm_state *state) 1503 + static int ti_sn_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, 1504 + struct pwm_state *state) 1505 1505 { 1506 1506 struct ti_sn65dsi86 *pdata = pwm_chip_to_ti_sn_bridge(chip); 1507 1507 unsigned int pwm_en_inv; ··· 1512 1512 1513 1513 ret = regmap_read(pdata->regmap, SN_PWM_EN_INV_REG, &pwm_en_inv); 1514 1514 if (ret) 1515 - return; 1515 + return ret; 1516 1516 1517 1517 ret = ti_sn65dsi86_read_u16(pdata, SN_BACKLIGHT_SCALE_REG, &scale); 1518 1518 if (ret) 1519 - return; 1519 + return ret; 1520 1520 1521 1521 ret = ti_sn65dsi86_read_u16(pdata, SN_BACKLIGHT_REG, &backlight); 1522 1522 if (ret) 1523 - return; 1523 + return ret; 1524 1524 1525 1525 ret = regmap_read(pdata->regmap, SN_PWM_PRE_DIV_REG, &pre_div); 1526 1526 if (ret) 1527 - return; 1527 + return ret; 1528 1528 1529 1529 state->enabled = FIELD_GET(SN_PWM_EN_MASK, pwm_en_inv); 1530 1530 if (FIELD_GET(SN_PWM_INV_MASK, pwm_en_inv)) ··· 1539 1539 1540 1540 if (state->duty_cycle > state->period) 1541 1541 state->duty_cycle = state->period; 1542 + 1543 + return 0; 1542 1544 } 1543 1545 1544 1546 static const struct pwm_ops ti_sn_pwm_ops = {
+8 -6
drivers/leds/rgb/leds-qcom-lpg.c
··· 972 972 return ret; 973 973 } 974 974 975 - static void lpg_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, 976 - struct pwm_state *state) 975 + static int lpg_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, 976 + struct pwm_state *state) 977 977 { 978 978 struct lpg *lpg = container_of(chip, struct lpg, pwm); 979 979 struct lpg_channel *chan = &lpg->channels[pwm->hwpwm]; ··· 986 986 987 987 ret = regmap_read(lpg->map, chan->base + LPG_SIZE_CLK_REG, &val); 988 988 if (ret) 989 - return; 989 + return ret; 990 990 991 991 refclk = lpg_clk_rates[val & PWM_CLK_SELECT_MASK]; 992 992 if (refclk) { 993 993 ret = regmap_read(lpg->map, chan->base + LPG_PREDIV_CLK_REG, &val); 994 994 if (ret) 995 - return; 995 + return ret; 996 996 997 997 pre_div = lpg_pre_divs[FIELD_GET(PWM_FREQ_PRE_DIV_MASK, val)]; 998 998 m = FIELD_GET(PWM_FREQ_EXP_MASK, val); 999 999 1000 1000 ret = regmap_bulk_read(lpg->map, chan->base + PWM_VALUE_REG, &pwm_value, sizeof(pwm_value)); 1001 1001 if (ret) 1002 - return; 1002 + return ret; 1003 1003 1004 1004 state->period = DIV_ROUND_UP_ULL((u64)NSEC_PER_SEC * LPG_RESOLUTION * pre_div * (1 << m), refclk); 1005 1005 state->duty_cycle = DIV_ROUND_UP_ULL((u64)NSEC_PER_SEC * pwm_value * pre_div * (1 << m), refclk); ··· 1010 1010 1011 1011 ret = regmap_read(lpg->map, chan->base + PWM_ENABLE_CONTROL_REG, &val); 1012 1012 if (ret) 1013 - return; 1013 + return ret; 1014 1014 1015 1015 state->enabled = FIELD_GET(LPG_ENABLE_CONTROL_OUTPUT, val); 1016 1016 state->polarity = PWM_POLARITY_NORMAL; 1017 1017 1018 1018 if (state->duty_cycle > state->period) 1019 1019 state->duty_cycle = state->period; 1020 + 1021 + return 0; 1020 1022 } 1021 1023 1022 1024 static const struct pwm_ops lpg_pwm_ops = {
+3 -3
drivers/pwm/Kconfig
··· 282 282 283 283 config PWM_JZ4740 284 284 tristate "Ingenic JZ47xx PWM support" 285 - depends on MIPS || COMPILE_TEST 286 - depends on COMMON_CLK 285 + depends on MACH_INGENIC || COMPILE_TEST 286 + depends on COMMON_CLK && OF 287 287 select MFD_SYSCON 288 288 help 289 289 Generic PWM framework driver for Ingenic JZ47xx based ··· 434 434 435 435 config PWM_PXA 436 436 tristate "PXA PWM support" 437 - depends on ARCH_PXA || COMPILE_TEST 437 + depends on ARCH_PXA || ARCH_MMP || COMPILE_TEST 438 438 depends on HAS_IOMEM 439 439 help 440 440 Generic PWM framework driver for PXA.
+38 -30
drivers/pwm/core.c
··· 27 27 28 28 static DEFINE_MUTEX(pwm_lookup_lock); 29 29 static LIST_HEAD(pwm_lookup_list); 30 + 31 + /* protects access to pwm_chips, allocated_pwms, and pwm_tree */ 30 32 static DEFINE_MUTEX(pwm_lock); 33 + 31 34 static LIST_HEAD(pwm_chips); 32 35 static DECLARE_BITMAP(allocated_pwms, MAX_PWMS); 33 36 static RADIX_TREE(pwm_tree, GFP_KERNEL); ··· 40 37 return radix_tree_lookup(&pwm_tree, pwm); 41 38 } 42 39 40 + /* Called with pwm_lock held */ 43 41 static int alloc_pwms(unsigned int count) 44 42 { 45 43 unsigned int start; ··· 51 47 if (start + count > MAX_PWMS) 52 48 return -ENOSPC; 53 49 50 + bitmap_set(allocated_pwms, start, count); 51 + 54 52 return start; 55 53 } 56 54 55 + /* Called with pwm_lock held */ 57 56 static void free_pwms(struct pwm_chip *chip) 58 57 { 59 58 unsigned int i; ··· 115 108 } 116 109 117 110 if (pwm->chip->ops->get_state) { 118 - pwm->chip->ops->get_state(pwm->chip, pwm, &pwm->state); 119 - trace_pwm_get(pwm, &pwm->state); 111 + struct pwm_state state; 112 + 113 + err = pwm->chip->ops->get_state(pwm->chip, pwm, &state); 114 + trace_pwm_get(pwm, &state, err); 115 + 116 + if (!err) 117 + pwm->state = state; 120 118 121 119 if (IS_ENABLED(CONFIG_PWM_DEBUG)) 122 120 pwm->last = pwm->state; ··· 279 267 if (!pwm_ops_check(chip)) 280 268 return -EINVAL; 281 269 270 + chip->pwms = kcalloc(chip->npwm, sizeof(*pwm), GFP_KERNEL); 271 + if (!chip->pwms) 272 + return -ENOMEM; 273 + 282 274 mutex_lock(&pwm_lock); 283 275 284 276 ret = alloc_pwms(chip->npwm); 285 - if (ret < 0) 286 - goto out; 277 + if (ret < 0) { 278 + mutex_unlock(&pwm_lock); 279 + kfree(chip->pwms); 280 + return ret; 281 + } 287 282 288 283 chip->base = ret; 289 - 290 - chip->pwms = kcalloc(chip->npwm, sizeof(*pwm), GFP_KERNEL); 291 - if (!chip->pwms) { 292 - ret = -ENOMEM; 293 - goto out; 294 - } 295 284 296 285 for (i = 0; i < chip->npwm; i++) { 297 286 pwm = &chip->pwms[i]; ··· 304 291 radix_tree_insert(&pwm_tree, pwm->pwm, pwm); 305 292 } 306 293 307 - bitmap_set(allocated_pwms, chip->base, chip->npwm); 308 - 309 - INIT_LIST_HEAD(&chip->list); 310 294 list_add(&chip->list, &pwm_chips); 311 295 312 - ret = 0; 296 + mutex_unlock(&pwm_lock); 313 297 314 298 if (IS_ENABLED(CONFIG_OF)) 315 299 of_pwmchip_add(chip); 316 300 317 - out: 318 - mutex_unlock(&pwm_lock); 301 + pwmchip_sysfs_export(chip); 319 302 320 - if (!ret) 321 - pwmchip_sysfs_export(chip); 322 - 323 - return ret; 303 + return 0; 324 304 } 325 305 EXPORT_SYMBOL_GPL(pwmchip_add); 326 306 ··· 463 457 * checks. 464 458 */ 465 459 466 - chip->ops->get_state(chip, pwm, &s1); 467 - trace_pwm_get(pwm, &s1); 460 + err = chip->ops->get_state(chip, pwm, &s1); 461 + trace_pwm_get(pwm, &s1, err); 462 + if (err) 463 + /* If that failed there isn't much to debug */ 464 + return; 468 465 469 466 /* 470 467 * The lowlevel driver either ignored .polarity (which is a bug) or as ··· 523 514 524 515 /* reapply the state that the driver reported being configured. */ 525 516 err = chip->ops->apply(chip, pwm, &s1); 517 + trace_pwm_apply(pwm, &s1, err); 526 518 if (err) { 527 519 *last = s1; 528 520 dev_err(chip->dev, "failed to reapply current setting\n"); 529 521 return; 530 522 } 531 523 532 - trace_pwm_apply(pwm, &s1); 533 - 534 - chip->ops->get_state(chip, pwm, last); 535 - trace_pwm_get(pwm, last); 524 + err = chip->ops->get_state(chip, pwm, last); 525 + trace_pwm_get(pwm, last, err); 526 + if (err) 527 + return; 536 528 537 529 /* reapplication of the current state should give an exact match */ 538 530 if (s1.enabled != last->enabled || ··· 581 571 return 0; 582 572 583 573 err = chip->ops->apply(chip, pwm, state); 574 + trace_pwm_apply(pwm, state, err); 584 575 if (err) 585 576 return err; 586 - 587 - trace_pwm_apply(pwm, state); 588 577 589 578 pwm->state = *state; 590 579 ··· 1188 1179 1189 1180 static int __init pwm_debugfs_init(void) 1190 1181 { 1191 - debugfs_create_file("pwm", S_IFREG | 0444, NULL, NULL, 1192 - &pwm_debugfs_fops); 1182 + debugfs_create_file("pwm", 0444, NULL, NULL, &pwm_debugfs_fops); 1193 1183 1194 1184 return 0; 1195 1185 }
+4 -2
drivers/pwm/pwm-atmel.c
··· 356 356 return 0; 357 357 } 358 358 359 - static void atmel_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, 360 - struct pwm_state *state) 359 + static int atmel_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, 360 + struct pwm_state *state) 361 361 { 362 362 struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip); 363 363 u32 sr, cmr; ··· 396 396 state->polarity = PWM_POLARITY_INVERSED; 397 397 else 398 398 state->polarity = PWM_POLARITY_NORMAL; 399 + 400 + return 0; 399 401 } 400 402 401 403 static const struct pwm_ops atmel_pwm_ops = {
+5 -3
drivers/pwm/pwm-bcm-iproc.c
··· 68 68 ndelay(400); 69 69 } 70 70 71 - static void iproc_pwmc_get_state(struct pwm_chip *chip, struct pwm_device *pwm, 72 - struct pwm_state *state) 71 + static int iproc_pwmc_get_state(struct pwm_chip *chip, struct pwm_device *pwm, 72 + struct pwm_state *state) 73 73 { 74 74 struct iproc_pwmc *ip = to_iproc_pwmc(chip); 75 75 u64 tmp, multi, rate; ··· 91 91 if (rate == 0) { 92 92 state->period = 0; 93 93 state->duty_cycle = 0; 94 - return; 94 + return 0; 95 95 } 96 96 97 97 value = readl(ip->base + IPROC_PWM_PRESCALE_OFFSET); ··· 107 107 value = readl(ip->base + IPROC_PWM_DUTY_CYCLE_OFFSET(pwm->hwpwm)); 108 108 tmp = (value & IPROC_PWM_PERIOD_MAX) * multi; 109 109 state->duty_cycle = div64_u64(tmp, rate); 110 + 111 + return 0; 110 112 } 111 113 112 114 static int iproc_pwmc_apply(struct pwm_chip *chip, struct pwm_device *pwm,
+6 -4
drivers/pwm/pwm-crc.c
··· 121 121 return 0; 122 122 } 123 123 124 - static void crc_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, 125 - struct pwm_state *state) 124 + static int crc_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, 125 + struct pwm_state *state) 126 126 { 127 127 struct crystalcove_pwm *crc_pwm = to_crc_pwm(chip); 128 128 struct device *dev = crc_pwm->chip.dev; ··· 132 132 error = regmap_read(crc_pwm->regmap, PWM0_CLK_DIV, &clk_div_reg); 133 133 if (error) { 134 134 dev_err(dev, "Error reading PWM0_CLK_DIV %d\n", error); 135 - return; 135 + return error; 136 136 } 137 137 138 138 error = regmap_read(crc_pwm->regmap, PWM0_DUTY_CYCLE, &duty_cycle_reg); 139 139 if (error) { 140 140 dev_err(dev, "Error reading PWM0_DUTY_CYCLE %d\n", error); 141 - return; 141 + return error; 142 142 } 143 143 144 144 clk_div = (clk_div_reg & ~PWM_OUTPUT_ENABLE) + 1; ··· 149 149 DIV_ROUND_UP_ULL(duty_cycle_reg * state->period, PWM_MAX_LEVEL); 150 150 state->polarity = PWM_POLARITY_NORMAL; 151 151 state->enabled = !!(clk_div_reg & PWM_OUTPUT_ENABLE); 152 + 153 + return 0; 152 154 } 153 155 154 156 static const struct pwm_ops crc_pwm_ops = {
+5 -3
drivers/pwm/pwm-cros-ec.c
··· 183 183 return 0; 184 184 } 185 185 186 - static void cros_ec_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, 187 - struct pwm_state *state) 186 + static int cros_ec_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, 187 + struct pwm_state *state) 188 188 { 189 189 struct cros_ec_pwm_device *ec_pwm = pwm_to_cros_ec_pwm(chip); 190 190 struct cros_ec_pwm *channel = pwm_get_chip_data(pwm); ··· 193 193 ret = cros_ec_pwm_get_duty(ec_pwm, pwm->hwpwm); 194 194 if (ret < 0) { 195 195 dev_err(chip->dev, "error getting initial duty: %d\n", ret); 196 - return; 196 + return ret; 197 197 } 198 198 199 199 state->enabled = (ret > 0); ··· 212 212 state->duty_cycle = channel->duty_cycle; 213 213 else 214 214 state->duty_cycle = ret; 215 + 216 + return 0; 215 217 } 216 218 217 219 static struct pwm_device *
+4 -2
drivers/pwm/pwm-dwc.c
··· 163 163 return 0; 164 164 } 165 165 166 - static void dwc_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, 167 - struct pwm_state *state) 166 + static int dwc_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, 167 + struct pwm_state *state) 168 168 { 169 169 struct dwc_pwm *dwc = to_dwc_pwm(chip); 170 170 u64 duty, period; ··· 188 188 state->polarity = PWM_POLARITY_INVERSED; 189 189 190 190 pm_runtime_put_sync(chip->dev); 191 + 192 + return 0; 191 193 } 192 194 193 195 static const struct pwm_ops dwc_pwm_ops = {
+7 -11
drivers/pwm/pwm-fsl-ftm.c
··· 65 65 66 66 regmap_read(fpc->regmap, FTM_FMS, &val); 67 67 if (val & FTM_FMS_WPEN) 68 - regmap_update_bits(fpc->regmap, FTM_MODE, FTM_MODE_WPDIS, 69 - FTM_MODE_WPDIS); 68 + regmap_set_bits(fpc->regmap, FTM_MODE, FTM_MODE_WPDIS); 70 69 } 71 70 72 71 static void ftm_set_write_protection(struct fsl_pwm_chip *fpc) 73 72 { 74 - regmap_update_bits(fpc->regmap, FTM_FMS, FTM_FMS_WPEN, FTM_FMS_WPEN); 73 + regmap_set_bits(fpc->regmap, FTM_FMS, FTM_FMS_WPEN); 75 74 } 76 75 77 76 static bool fsl_pwm_periodcfg_are_equal(const struct fsl_pwm_periodcfg *a, ··· 93 94 ret = clk_prepare_enable(fpc->ipg_clk); 94 95 if (!ret && fpc->soc->has_enable_bits) { 95 96 mutex_lock(&fpc->lock); 96 - regmap_update_bits(fpc->regmap, FTM_SC, BIT(pwm->hwpwm + 16), 97 - BIT(pwm->hwpwm + 16)); 97 + regmap_set_bits(fpc->regmap, FTM_SC, BIT(pwm->hwpwm + 16)); 98 98 mutex_unlock(&fpc->lock); 99 99 } 100 100 ··· 106 108 107 109 if (fpc->soc->has_enable_bits) { 108 110 mutex_lock(&fpc->lock); 109 - regmap_update_bits(fpc->regmap, FTM_SC, BIT(pwm->hwpwm + 16), 110 - 0); 111 + regmap_clear_bits(fpc->regmap, FTM_SC, BIT(pwm->hwpwm + 16)); 111 112 mutex_unlock(&fpc->lock); 112 113 } 113 114 ··· 314 317 315 318 if (!newstate->enabled) { 316 319 if (oldstate->enabled) { 317 - regmap_update_bits(fpc->regmap, FTM_OUTMASK, 318 - BIT(pwm->hwpwm), BIT(pwm->hwpwm)); 320 + regmap_set_bits(fpc->regmap, FTM_OUTMASK, 321 + BIT(pwm->hwpwm)); 319 322 clk_disable_unprepare(fpc->clk[FSL_PWM_CLK_CNTEN]); 320 323 clk_disable_unprepare(fpc->clk[fpc->period.clk_select]); 321 324 } ··· 339 342 goto end_mutex; 340 343 } 341 344 342 - regmap_update_bits(fpc->regmap, FTM_OUTMASK, BIT(pwm->hwpwm), 343 - 0); 345 + regmap_clear_bits(fpc->regmap, FTM_OUTMASK, BIT(pwm->hwpwm)); 344 346 } 345 347 346 348 end_mutex:
+4 -2
drivers/pwm/pwm-hibvt.c
··· 128 128 PWM_POLARITY_MASK, (0x0 << PWM_POLARITY_SHIFT)); 129 129 } 130 130 131 - static void hibvt_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, 132 - struct pwm_state *state) 131 + static int hibvt_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, 132 + struct pwm_state *state) 133 133 { 134 134 struct hibvt_pwm_chip *hi_pwm_chip = to_hibvt_pwm_chip(chip); 135 135 void __iomem *base; ··· 146 146 147 147 value = readl(base + PWM_CTRL_ADDR(pwm->hwpwm)); 148 148 state->enabled = (PWM_ENABLE_MASK & value); 149 + 150 + return 0; 149 151 } 150 152 151 153 static int hibvt_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
+7 -8
drivers/pwm/pwm-img.c
··· 161 161 val |= BIT(pwm->hwpwm); 162 162 img_pwm_writel(imgchip, PWM_CTRL_CFG, val); 163 163 164 - regmap_update_bits(imgchip->periph_regs, PERIP_PWM_PDM_CONTROL, 165 - PERIP_PWM_PDM_CONTROL_CH_MASK << 166 - PERIP_PWM_PDM_CONTROL_CH_SHIFT(pwm->hwpwm), 0); 164 + regmap_clear_bits(imgchip->periph_regs, PERIP_PWM_PDM_CONTROL, 165 + PERIP_PWM_PDM_CONTROL_CH_MASK << 166 + PERIP_PWM_PDM_CONTROL_CH_SHIFT(pwm->hwpwm)); 167 167 168 168 return 0; 169 169 } ··· 397 397 398 398 for (i = 0; i < imgchip->chip.npwm; i++) 399 399 if (imgchip->suspend_ctrl_cfg & BIT(i)) 400 - regmap_update_bits(imgchip->periph_regs, 401 - PERIP_PWM_PDM_CONTROL, 402 - PERIP_PWM_PDM_CONTROL_CH_MASK << 403 - PERIP_PWM_PDM_CONTROL_CH_SHIFT(i), 404 - 0); 400 + regmap_clear_bits(imgchip->periph_regs, 401 + PERIP_PWM_PDM_CONTROL, 402 + PERIP_PWM_PDM_CONTROL_CH_MASK << 403 + PERIP_PWM_PDM_CONTROL_CH_SHIFT(i)); 405 404 406 405 if (pm_runtime_status_suspended(dev)) 407 406 img_pwm_runtime_suspend(dev);
+5 -3
drivers/pwm/pwm-imx-tpm.c
··· 132 132 return 0; 133 133 } 134 134 135 - static void pwm_imx_tpm_get_state(struct pwm_chip *chip, 136 - struct pwm_device *pwm, 137 - struct pwm_state *state) 135 + static int pwm_imx_tpm_get_state(struct pwm_chip *chip, 136 + struct pwm_device *pwm, 137 + struct pwm_state *state) 138 138 { 139 139 struct imx_tpm_pwm_chip *tpm = to_imx_tpm_pwm_chip(chip); 140 140 u32 rate, val, prescale; ··· 164 164 165 165 /* get channel status */ 166 166 state->enabled = FIELD_GET(PWM_IMX_TPM_CnSC_ELS, val) ? true : false; 167 + 168 + return 0; 167 169 } 168 170 169 171 /* this function is supposed to be called with mutex hold */
+5 -3
drivers/pwm/pwm-imx27.c
··· 118 118 clk_disable_unprepare(imx->clk_ipg); 119 119 } 120 120 121 - static void pwm_imx27_get_state(struct pwm_chip *chip, 122 - struct pwm_device *pwm, struct pwm_state *state) 121 + static int pwm_imx27_get_state(struct pwm_chip *chip, 122 + struct pwm_device *pwm, struct pwm_state *state) 123 123 { 124 124 struct pwm_imx27_chip *imx = to_pwm_imx27_chip(chip); 125 125 u32 period, prescaler, pwm_clk, val; ··· 128 128 129 129 ret = pwm_imx27_clk_prepare_enable(imx); 130 130 if (ret < 0) 131 - return; 131 + return ret; 132 132 133 133 val = readl(imx->mmio_base + MX3_PWMCR); 134 134 ··· 170 170 state->duty_cycle = DIV_ROUND_UP_ULL(tmp, pwm_clk); 171 171 172 172 pwm_imx27_clk_disable_unprepare(imx); 173 + 174 + return 0; 173 175 } 174 176 175 177 static void pwm_imx27_sw_reset(struct pwm_chip *chip)
+4 -2
drivers/pwm/pwm-intel-lgm.c
··· 86 86 return lgm_pwm_enable(chip, 1); 87 87 } 88 88 89 - static void lgm_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, 90 - struct pwm_state *state) 89 + static int lgm_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, 90 + struct pwm_state *state) 91 91 { 92 92 struct lgm_pwm_chip *pc = to_lgm_pwm_chip(chip); 93 93 u32 duty, val; ··· 100 100 regmap_read(pc->regmap, LGM_PWM_FAN_CON0, &val); 101 101 duty = FIELD_GET(LGM_PWM_FAN_DC_MSK, val); 102 102 state->duty_cycle = DIV_ROUND_UP(duty * pc->period, LGM_PWM_MAX_DUTY_CYCLE); 103 + 104 + return 0; 103 105 } 104 106 105 107 static const struct pwm_ops lgm_pwm_ops = {
+6 -4
drivers/pwm/pwm-iqs620a.c
··· 47 47 int ret; 48 48 49 49 if (!duty_scale) 50 - return regmap_update_bits(iqs62x->regmap, IQS620_PWR_SETTINGS, 51 - IQS620_PWR_SETTINGS_PWM_OUT, 0); 50 + return regmap_clear_bits(iqs62x->regmap, IQS620_PWR_SETTINGS, 51 + IQS620_PWR_SETTINGS_PWM_OUT); 52 52 53 53 ret = regmap_write(iqs62x->regmap, IQS620_PWM_DUTY_CYCLE, 54 54 duty_scale - 1); ··· 104 104 return ret; 105 105 } 106 106 107 - static void iqs620_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, 108 - struct pwm_state *state) 107 + static int iqs620_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, 108 + struct pwm_state *state) 109 109 { 110 110 struct iqs620_pwm_private *iqs620_pwm; 111 111 ··· 126 126 mutex_unlock(&iqs620_pwm->lock); 127 127 128 128 state->period = IQS620_PWM_PERIOD_NS; 129 + 130 + return 0; 129 131 } 130 132 131 133 static int iqs620_pwm_notifier(struct notifier_block *notifier,
+8 -12
drivers/pwm/pwm-jz4740.c
··· 88 88 struct jz4740_pwm_chip *jz = to_jz4740(chip); 89 89 90 90 /* Enable PWM output */ 91 - regmap_update_bits(jz->map, TCU_REG_TCSRc(pwm->hwpwm), 92 - TCU_TCSR_PWM_EN, TCU_TCSR_PWM_EN); 91 + regmap_set_bits(jz->map, TCU_REG_TCSRc(pwm->hwpwm), TCU_TCSR_PWM_EN); 93 92 94 93 /* Start counter */ 95 94 regmap_write(jz->map, TCU_REG_TESR, BIT(pwm->hwpwm)); ··· 112 113 * In TCU2 mode (channel 1/2 on JZ4750+), this must be done before the 113 114 * counter is stopped, while in TCU1 mode the order does not matter. 114 115 */ 115 - regmap_update_bits(jz->map, TCU_REG_TCSRc(pwm->hwpwm), 116 - TCU_TCSR_PWM_EN, 0); 116 + regmap_clear_bits(jz->map, TCU_REG_TCSRc(pwm->hwpwm), TCU_TCSR_PWM_EN); 117 117 118 118 /* Stop counter */ 119 119 regmap_write(jz->map, TCU_REG_TECR, BIT(pwm->hwpwm)); ··· 182 184 regmap_write(jz4740->map, TCU_REG_TDFRc(pwm->hwpwm), period); 183 185 184 186 /* Set abrupt shutdown */ 185 - regmap_update_bits(jz4740->map, TCU_REG_TCSRc(pwm->hwpwm), 186 - TCU_TCSR_PWM_SD, TCU_TCSR_PWM_SD); 187 + regmap_set_bits(jz4740->map, TCU_REG_TCSRc(pwm->hwpwm), 188 + TCU_TCSR_PWM_SD); 187 189 188 190 /* 189 191 * Set polarity. ··· 246 248 return devm_pwmchip_add(dev, &jz4740->chip); 247 249 } 248 250 249 - static const struct soc_info __maybe_unused jz4740_soc_info = { 251 + static const struct soc_info jz4740_soc_info = { 250 252 .num_pwms = 8, 251 253 }; 252 254 253 - static const struct soc_info __maybe_unused jz4725b_soc_info = { 255 + static const struct soc_info jz4725b_soc_info = { 254 256 .num_pwms = 6, 255 257 }; 256 258 257 - static const struct soc_info __maybe_unused x1000_soc_info = { 259 + static const struct soc_info x1000_soc_info = { 258 260 .num_pwms = 5, 259 261 }; 260 262 261 - #ifdef CONFIG_OF 262 263 static const struct of_device_id jz4740_pwm_dt_ids[] = { 263 264 { .compatible = "ingenic,jz4740-pwm", .data = &jz4740_soc_info }, 264 265 { .compatible = "ingenic,jz4725b-pwm", .data = &jz4725b_soc_info }, ··· 265 268 {}, 266 269 }; 267 270 MODULE_DEVICE_TABLE(of, jz4740_pwm_dt_ids); 268 - #endif 269 271 270 272 static struct platform_driver jz4740_pwm_driver = { 271 273 .driver = { 272 274 .name = "jz4740-pwm", 273 - .of_match_table = of_match_ptr(jz4740_pwm_dt_ids), 275 + .of_match_table = jz4740_pwm_dt_ids, 274 276 }, 275 277 .probe = jz4740_pwm_probe, 276 278 };
+4 -2
drivers/pwm/pwm-keembay.c
··· 89 89 KMB_PWM_LEADIN_OFFSET(ch)); 90 90 } 91 91 92 - static void keembay_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, 93 - struct pwm_state *state) 92 + static int keembay_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, 93 + struct pwm_state *state) 94 94 { 95 95 struct keembay_pwm *priv = to_keembay_pwm_dev(chip); 96 96 unsigned long long high, low; ··· 113 113 state->duty_cycle = DIV_ROUND_UP_ULL(high, clk_rate); 114 114 state->period = DIV_ROUND_UP_ULL(high + low, clk_rate); 115 115 state->polarity = PWM_POLARITY_NORMAL; 116 + 117 + return 0; 116 118 } 117 119 118 120 static int keembay_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
+1 -1
drivers/pwm/pwm-lpc18xx-sct.c
··· 175 175 u32 val; 176 176 177 177 /* 178 - * With clk_rate < NSEC_PER_SEC this cannot overflow. 178 + * With clk_rate <= NSEC_PER_SEC this cannot overflow. 179 179 * With duty_ns <= period_ns < max_period_ns this also fits into an u32. 180 180 */ 181 181 val = mul_u64_u64_div_u64(duty_ns, lpc18xx_pwm->clk_rate, NSEC_PER_SEC);
+4 -2
drivers/pwm/pwm-lpss.c
··· 205 205 return ret; 206 206 } 207 207 208 - static void pwm_lpss_get_state(struct pwm_chip *chip, struct pwm_device *pwm, 209 - struct pwm_state *state) 208 + static int pwm_lpss_get_state(struct pwm_chip *chip, struct pwm_device *pwm, 209 + struct pwm_state *state) 210 210 { 211 211 struct pwm_lpss_chip *lpwm = to_lpwm(chip); 212 212 unsigned long base_unit_range; ··· 236 236 state->enabled = !!(ctrl & PWM_ENABLE); 237 237 238 238 pm_runtime_put(chip->dev); 239 + 240 + return 0; 239 241 } 240 242 241 243 static const struct pwm_ops pwm_lpss_ops = {
+8 -1
drivers/pwm/pwm-mediatek.c
··· 296 296 static const struct pwm_mediatek_of_data mt7622_pwm_data = { 297 297 .num_pwms = 6, 298 298 .pwm45_fixup = false, 299 - .has_ck_26m_sel = false, 299 + .has_ck_26m_sel = true, 300 300 }; 301 301 302 302 static const struct pwm_mediatek_of_data mt7623_pwm_data = { ··· 329 329 .has_ck_26m_sel = true, 330 330 }; 331 331 332 + static const struct pwm_mediatek_of_data mt7986_pwm_data = { 333 + .num_pwms = 2, 334 + .pwm45_fixup = false, 335 + .has_ck_26m_sel = true, 336 + }; 337 + 332 338 static const struct pwm_mediatek_of_data mt8516_pwm_data = { 333 339 .num_pwms = 5, 334 340 .pwm45_fixup = false, ··· 348 342 { .compatible = "mediatek,mt7623-pwm", .data = &mt7623_pwm_data }, 349 343 { .compatible = "mediatek,mt7628-pwm", .data = &mt7628_pwm_data }, 350 344 { .compatible = "mediatek,mt7629-pwm", .data = &mt7629_pwm_data }, 345 + { .compatible = "mediatek,mt7986-pwm", .data = &mt7986_pwm_data }, 351 346 { .compatible = "mediatek,mt8183-pwm", .data = &mt8183_pwm_data }, 352 347 { .compatible = "mediatek,mt8365-pwm", .data = &mt8365_pwm_data }, 353 348 { .compatible = "mediatek,mt8516-pwm", .data = &mt8516_pwm_data },
+5 -3
drivers/pwm/pwm-meson.c
··· 318 318 return cnt * fin_ns * (channel->pre_div + 1); 319 319 } 320 320 321 - static void meson_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, 322 - struct pwm_state *state) 321 + static int meson_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, 322 + struct pwm_state *state) 323 323 { 324 324 struct meson_pwm *meson = to_meson_pwm(chip); 325 325 struct meson_pwm_channel_data *channel_data; ··· 327 327 u32 value, tmp; 328 328 329 329 if (!state) 330 - return; 330 + return 0; 331 331 332 332 channel = &meson->channels[pwm->hwpwm]; 333 333 channel_data = &meson_pwm_per_channel_data[pwm->hwpwm]; ··· 357 357 state->period = 0; 358 358 state->duty_cycle = 0; 359 359 } 360 + 361 + return 0; 360 362 } 361 363 362 364 static const struct pwm_ops meson_pwm_ops = {
+10 -7
drivers/pwm/pwm-mtk-disp.c
··· 172 172 return 0; 173 173 } 174 174 175 - static void mtk_disp_pwm_get_state(struct pwm_chip *chip, 176 - struct pwm_device *pwm, 177 - struct pwm_state *state) 175 + static int mtk_disp_pwm_get_state(struct pwm_chip *chip, 176 + struct pwm_device *pwm, 177 + struct pwm_state *state) 178 178 { 179 179 struct mtk_disp_pwm *mdp = to_mtk_disp_pwm(chip); 180 180 u64 rate, period, high_width; 181 - u32 clk_div, con0, con1; 181 + u32 clk_div, pwm_en, con0, con1; 182 182 int err; 183 183 184 184 err = clk_prepare_enable(mdp->clk_main); 185 185 if (err < 0) { 186 186 dev_err(chip->dev, "Can't enable mdp->clk_main: %pe\n", ERR_PTR(err)); 187 - return; 187 + return err; 188 188 } 189 189 190 190 err = clk_prepare_enable(mdp->clk_mm); 191 191 if (err < 0) { 192 192 dev_err(chip->dev, "Can't enable mdp->clk_mm: %pe\n", ERR_PTR(err)); 193 193 clk_disable_unprepare(mdp->clk_main); 194 - return; 194 + return err; 195 195 } 196 196 197 197 rate = clk_get_rate(mdp->clk_main); 198 198 con0 = readl(mdp->base + mdp->data->con0); 199 199 con1 = readl(mdp->base + mdp->data->con1); 200 - state->enabled = !!(con0 & BIT(0)); 200 + pwm_en = readl(mdp->base + DISP_PWM_EN); 201 + state->enabled = !!(pwm_en & mdp->data->enable_mask); 201 202 clk_div = FIELD_GET(PWM_CLKDIV_MASK, con0); 202 203 period = FIELD_GET(PWM_PERIOD_MASK, con1); 203 204 /* ··· 212 211 state->polarity = PWM_POLARITY_NORMAL; 213 212 clk_disable_unprepare(mdp->clk_mm); 214 213 clk_disable_unprepare(mdp->clk_main); 214 + 215 + return 0; 215 216 } 216 217 217 218 static const struct pwm_ops mtk_disp_pwm_ops = {
+7 -6
drivers/pwm/pwm-pca9685.c
··· 431 431 return ret; 432 432 } 433 433 434 - static void pca9685_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, 435 - struct pwm_state *state) 434 + static int pca9685_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, 435 + struct pwm_state *state) 436 436 { 437 437 struct pca9685 *pca = to_pca(chip); 438 438 unsigned long long duty; ··· 458 458 */ 459 459 state->duty_cycle = 0; 460 460 state->enabled = false; 461 - return; 461 + return 0; 462 462 } 463 463 464 464 state->enabled = true; 465 465 duty = pca9685_pwm_get_duty(pca, pwm->hwpwm); 466 466 state->duty_cycle = DIV_ROUND_DOWN_ULL(duty * state->period, PCA9685_COUNTER_RANGE); 467 + 468 + return 0; 467 469 } 468 470 469 471 static int pca9685_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm) ··· 515 513 .cache_type = REGCACHE_NONE, 516 514 }; 517 515 518 - static int pca9685_pwm_probe(struct i2c_client *client, 519 - const struct i2c_device_id *id) 516 + static int pca9685_pwm_probe(struct i2c_client *client) 520 517 { 521 518 struct pca9685 *pca; 522 519 unsigned int reg; ··· 665 664 .of_match_table = of_match_ptr(pca9685_dt_ids), 666 665 .pm = &pca9685_pwm_pm, 667 666 }, 668 - .probe = pca9685_pwm_probe, 667 + .probe_new = pca9685_pwm_probe, 669 668 .remove = pca9685_pwm_remove, 670 669 .id_table = pca9685_id, 671 670 };
+26 -34
drivers/pwm/pwm-pxa.c
··· 6 6 * 7 7 * 2008-02-13 initial version 8 8 * eric miao <eric.miao@marvell.com> 9 + * 10 + * Links to reference manuals for some of the supported PWM chips can be found 11 + * in Documentation/arm/marvell.rst. 12 + * 13 + * Limitations: 14 + * - When PWM is stopped, the current PWM period stops abruptly at the next 15 + * input clock (PWMCR_SD is set) and the output is driven to inactive. 9 16 */ 10 17 11 18 #include <linux/module.h> ··· 71 64 unsigned long long c; 72 65 unsigned long period_cycles, prescale, pv, dc; 73 66 unsigned long offset; 74 - int rc; 75 67 76 68 offset = pwm->hwpwm ? 0x10 : 0; 77 69 ··· 92 86 else 93 87 dc = mul_u64_u64_div_u64(pv + 1, duty_ns, period_ns); 94 88 95 - /* NOTE: the clock to PWM has to be enabled first 96 - * before writing to the registers 97 - */ 98 - rc = clk_prepare_enable(pc->clk); 99 - if (rc < 0) 100 - return rc; 101 - 102 - writel(prescale, pc->mmio_base + offset + PWMCR); 89 + writel(prescale | PWMCR_SD, pc->mmio_base + offset + PWMCR); 103 90 writel(dc, pc->mmio_base + offset + PWMDCR); 104 91 writel(pv, pc->mmio_base + offset + PWMPCR); 105 92 106 - clk_disable_unprepare(pc->clk); 107 93 return 0; 108 - } 109 - 110 - static int pxa_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) 111 - { 112 - struct pxa_pwm_chip *pc = to_pxa_pwm_chip(chip); 113 - 114 - return clk_prepare_enable(pc->clk); 115 - } 116 - 117 - static void pxa_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) 118 - { 119 - struct pxa_pwm_chip *pc = to_pxa_pwm_chip(chip); 120 - 121 - clk_disable_unprepare(pc->clk); 122 94 } 123 95 124 96 static int pxa_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, 125 97 const struct pwm_state *state) 126 98 { 99 + struct pxa_pwm_chip *pc = to_pxa_pwm_chip(chip); 100 + u64 duty_cycle; 127 101 int err; 128 102 129 103 if (state->polarity != PWM_POLARITY_NORMAL) 130 104 return -EINVAL; 131 105 132 - if (!state->enabled) { 133 - if (pwm->state.enabled) 134 - pxa_pwm_disable(chip, pwm); 135 - 136 - return 0; 137 - } 138 - 139 - err = pxa_pwm_config(chip, pwm, state->duty_cycle, state->period); 106 + err = clk_prepare_enable(pc->clk); 140 107 if (err) 141 108 return err; 142 109 143 - if (!pwm->state.enabled) 144 - return pxa_pwm_enable(chip, pwm); 110 + duty_cycle = state->enabled ? state->duty_cycle : 0; 111 + 112 + err = pxa_pwm_config(chip, pwm, duty_cycle, state->period); 113 + if (err) { 114 + clk_disable_unprepare(pc->clk); 115 + return err; 116 + } 117 + 118 + if (state->enabled && !pwm->state.enabled) 119 + return 0; 120 + 121 + clk_disable_unprepare(pc->clk); 122 + 123 + if (!state->enabled && pwm->state.enabled) 124 + clk_disable_unprepare(pc->clk); 145 125 146 126 return 0; 147 127 }
+5 -3
drivers/pwm/pwm-raspberrypi-poe.c
··· 82 82 return 0; 83 83 } 84 84 85 - static void raspberrypi_pwm_get_state(struct pwm_chip *chip, 86 - struct pwm_device *pwm, 87 - struct pwm_state *state) 85 + static int raspberrypi_pwm_get_state(struct pwm_chip *chip, 86 + struct pwm_device *pwm, 87 + struct pwm_state *state) 88 88 { 89 89 struct raspberrypi_pwm *rpipwm = raspberrypi_pwm_from_chip(chip); 90 90 ··· 93 93 RPI_PWM_MAX_DUTY); 94 94 state->enabled = !!(rpipwm->duty_cycle); 95 95 state->polarity = PWM_POLARITY_NORMAL; 96 + 97 + return 0; 96 98 } 97 99 98 100 static int raspberrypi_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
+7 -5
drivers/pwm/pwm-rockchip.c
··· 57 57 return container_of(c, struct rockchip_pwm_chip, chip); 58 58 } 59 59 60 - static void rockchip_pwm_get_state(struct pwm_chip *chip, 61 - struct pwm_device *pwm, 62 - struct pwm_state *state) 60 + static int rockchip_pwm_get_state(struct pwm_chip *chip, 61 + struct pwm_device *pwm, 62 + struct pwm_state *state) 63 63 { 64 64 struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip); 65 65 u32 enable_conf = pc->data->enable_conf; ··· 70 70 71 71 ret = clk_enable(pc->pclk); 72 72 if (ret) 73 - return; 73 + return ret; 74 74 75 75 ret = clk_enable(pc->clk); 76 76 if (ret) 77 - return; 77 + return ret; 78 78 79 79 clk_rate = clk_get_rate(pc->clk); 80 80 ··· 96 96 97 97 clk_disable(pc->clk); 98 98 clk_disable(pc->pclk); 99 + 100 + return 0; 99 101 } 100 102 101 103 static void rockchip_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
+8 -3
drivers/pwm/pwm-sifive.c
··· 105 105 "New real_period = %u ns\n", ddata->real_period); 106 106 } 107 107 108 - static void pwm_sifive_get_state(struct pwm_chip *chip, struct pwm_device *pwm, 109 - struct pwm_state *state) 108 + static int pwm_sifive_get_state(struct pwm_chip *chip, struct pwm_device *pwm, 109 + struct pwm_state *state) 110 110 { 111 111 struct pwm_sifive_ddata *ddata = pwm_sifive_chip_to_ddata(chip); 112 112 u32 duty, val; ··· 123 123 state->duty_cycle = 124 124 (u64)duty * ddata->real_period >> PWM_SIFIVE_CMPWIDTH; 125 125 state->polarity = PWM_POLARITY_INVERSED; 126 + 127 + return 0; 126 128 } 127 129 128 130 static int pwm_sifive_apply(struct pwm_chip *chip, struct pwm_device *pwm, ··· 206 204 struct pwm_sifive_ddata *ddata = 207 205 container_of(nb, struct pwm_sifive_ddata, notifier); 208 206 209 - if (event == POST_RATE_CHANGE) 207 + if (event == POST_RATE_CHANGE) { 208 + mutex_lock(&ddata->lock); 210 209 pwm_sifive_update_clock(ddata, ndata->new_rate); 210 + mutex_unlock(&ddata->lock); 211 + } 211 212 212 213 return NOTIFY_OK; 213 214 }
+5 -3
drivers/pwm/pwm-sl28cpld.c
··· 87 87 #define sl28cpld_pwm_from_chip(_chip) \ 88 88 container_of(_chip, struct sl28cpld_pwm, pwm_chip) 89 89 90 - static void sl28cpld_pwm_get_state(struct pwm_chip *chip, 91 - struct pwm_device *pwm, 92 - struct pwm_state *state) 90 + static int sl28cpld_pwm_get_state(struct pwm_chip *chip, 91 + struct pwm_device *pwm, 92 + struct pwm_state *state) 93 93 { 94 94 struct sl28cpld_pwm *priv = sl28cpld_pwm_from_chip(chip); 95 95 unsigned int reg; ··· 115 115 * the PWM core. 116 116 */ 117 117 state->duty_cycle = min(state->duty_cycle, state->period); 118 + 119 + return 0; 118 120 } 119 121 120 122 static int sl28cpld_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
+5 -3
drivers/pwm/pwm-sprd.c
··· 65 65 writel_relaxed(val, spc->base + offset); 66 66 } 67 67 68 - static void sprd_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, 69 - struct pwm_state *state) 68 + static int sprd_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, 69 + struct pwm_state *state) 70 70 { 71 71 struct sprd_pwm_chip *spc = 72 72 container_of(chip, struct sprd_pwm_chip, chip); ··· 83 83 if (ret) { 84 84 dev_err(spc->dev, "failed to enable pwm%u clocks\n", 85 85 pwm->hwpwm); 86 - return; 86 + return ret; 87 87 } 88 88 89 89 val = sprd_pwm_read(spc, pwm->hwpwm, SPRD_PWM_ENABLE); ··· 113 113 /* Disable PWM clocks if the PWM channel is not in enable state. */ 114 114 if (!state->enabled) 115 115 clk_bulk_disable_unprepare(SPRD_PWM_CHN_CLKS_NUM, chn->clks); 116 + 117 + return 0; 116 118 } 117 119 118 120 static int sprd_pwm_config(struct sprd_pwm_chip *spc, struct pwm_device *pwm,
+7 -6
drivers/pwm/pwm-stm32-lp.c
··· 140 140 141 141 if (reenable) { 142 142 /* Start LP timer in continuous mode */ 143 - ret = regmap_update_bits(priv->regmap, STM32_LPTIM_CR, 144 - STM32_LPTIM_CNTSTRT, 145 - STM32_LPTIM_CNTSTRT); 143 + ret = regmap_set_bits(priv->regmap, STM32_LPTIM_CR, 144 + STM32_LPTIM_CNTSTRT); 146 145 if (ret) { 147 146 regmap_write(priv->regmap, STM32_LPTIM_CR, 0); 148 147 goto err; ··· 156 157 return ret; 157 158 } 158 159 159 - static void stm32_pwm_lp_get_state(struct pwm_chip *chip, 160 - struct pwm_device *pwm, 161 - struct pwm_state *state) 160 + static int stm32_pwm_lp_get_state(struct pwm_chip *chip, 161 + struct pwm_device *pwm, 162 + struct pwm_state *state) 162 163 { 163 164 struct stm32_pwm_lp *priv = to_stm32_pwm_lp(chip); 164 165 unsigned long rate = clk_get_rate(priv->clk); ··· 184 185 tmp = prd - val; 185 186 tmp = (tmp << presc) * NSEC_PER_SEC; 186 187 state->duty_cycle = DIV_ROUND_CLOSEST_ULL(tmp, rate); 188 + 189 + return 0; 187 190 } 188 191 189 192 static const struct pwm_ops stm32_pwm_lp_ops = {
+16 -18
drivers/pwm/pwm-stm32.c
··· 115 115 int ret; 116 116 117 117 /* Ensure registers have been updated, enable counter and capture */ 118 - regmap_update_bits(priv->regmap, TIM_EGR, TIM_EGR_UG, TIM_EGR_UG); 119 - regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, TIM_CR1_CEN); 118 + regmap_set_bits(priv->regmap, TIM_EGR, TIM_EGR_UG); 119 + regmap_set_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN); 120 120 121 121 /* Use cc1 or cc3 DMA resp for PWM input channels 1 & 2 or 3 & 4 */ 122 122 dma_id = pwm->hwpwm < 2 ? STM32_TIMERS_DMA_CH1 : STM32_TIMERS_DMA_CH3; 123 123 ccen = pwm->hwpwm < 2 ? TIM_CCER_CC12E : TIM_CCER_CC34E; 124 124 ccr = pwm->hwpwm < 2 ? TIM_CCR1 : TIM_CCR3; 125 - regmap_update_bits(priv->regmap, TIM_CCER, ccen, ccen); 125 + regmap_set_bits(priv->regmap, TIM_CCER, ccen); 126 126 127 127 /* 128 128 * Timer DMA burst mode. Request 2 registers, 2 bursts, to get both ··· 160 160 } 161 161 162 162 stop: 163 - regmap_update_bits(priv->regmap, TIM_CCER, ccen, 0); 164 - regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0); 163 + regmap_clear_bits(priv->regmap, TIM_CCER, ccen); 164 + regmap_clear_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN); 165 165 166 166 return ret; 167 167 } ··· 359 359 360 360 regmap_write(priv->regmap, TIM_PSC, prescaler); 361 361 regmap_write(priv->regmap, TIM_ARR, prd - 1); 362 - regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, TIM_CR1_ARPE); 362 + regmap_set_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE); 363 363 364 364 /* Calculate the duty cycles */ 365 365 dty = prd * duty_ns; ··· 377 377 else 378 378 regmap_update_bits(priv->regmap, TIM_CCMR2, mask, ccmr); 379 379 380 - regmap_update_bits(priv->regmap, TIM_BDTR, TIM_BDTR_MOE, TIM_BDTR_MOE); 380 + regmap_set_bits(priv->regmap, TIM_BDTR, TIM_BDTR_MOE); 381 381 382 382 return 0; 383 383 } ··· 411 411 if (priv->have_complementary_output) 412 412 mask |= TIM_CCER_CC1NE << (ch * 4); 413 413 414 - regmap_update_bits(priv->regmap, TIM_CCER, mask, mask); 414 + regmap_set_bits(priv->regmap, TIM_CCER, mask); 415 415 416 416 /* Make sure that registers are updated */ 417 - regmap_update_bits(priv->regmap, TIM_EGR, TIM_EGR_UG, TIM_EGR_UG); 417 + regmap_set_bits(priv->regmap, TIM_EGR, TIM_EGR_UG); 418 418 419 419 /* Enable controller */ 420 - regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, TIM_CR1_CEN); 420 + regmap_set_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN); 421 421 422 422 return 0; 423 423 } ··· 431 431 if (priv->have_complementary_output) 432 432 mask |= TIM_CCER_CC1NE << (ch * 4); 433 433 434 - regmap_update_bits(priv->regmap, TIM_CCER, mask, 0); 434 + regmap_clear_bits(priv->regmap, TIM_CCER, mask); 435 435 436 436 /* When all channels are disabled, we can disable the controller */ 437 437 if (!active_channels(priv)) 438 - regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0); 438 + regmap_clear_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN); 439 439 440 440 clk_disable(priv->clk); 441 441 } ··· 568 568 * If complementary bit doesn't exist writing 1 will have no 569 569 * effect so we can detect it. 570 570 */ 571 - regmap_update_bits(priv->regmap, 572 - TIM_CCER, TIM_CCER_CC1NE, TIM_CCER_CC1NE); 571 + regmap_set_bits(priv->regmap, TIM_CCER, TIM_CCER_CC1NE); 573 572 regmap_read(priv->regmap, TIM_CCER, &ccer); 574 - regmap_update_bits(priv->regmap, TIM_CCER, TIM_CCER_CC1NE, 0); 573 + regmap_clear_bits(priv->regmap, TIM_CCER, TIM_CCER_CC1NE); 575 574 576 575 priv->have_complementary_output = (ccer != 0); 577 576 } ··· 584 585 * If channels enable bits don't exist writing 1 will have no 585 586 * effect so we can detect and count them. 586 587 */ 587 - regmap_update_bits(priv->regmap, 588 - TIM_CCER, TIM_CCER_CCXE, TIM_CCER_CCXE); 588 + regmap_set_bits(priv->regmap, TIM_CCER, TIM_CCER_CCXE); 589 589 regmap_read(priv->regmap, TIM_CCER, &ccer); 590 - regmap_update_bits(priv->regmap, TIM_CCER, TIM_CCER_CCXE, 0); 590 + regmap_clear_bits(priv->regmap, TIM_CCER, TIM_CCER_CCXE); 591 591 592 592 if (ccer & TIM_CCER_CC1E) 593 593 npwm++;
+9 -5
drivers/pwm/pwm-sun4i.c
··· 108 108 writel(val, chip->base + offset); 109 109 } 110 110 111 - static void sun4i_pwm_get_state(struct pwm_chip *chip, 112 - struct pwm_device *pwm, 113 - struct pwm_state *state) 111 + static int sun4i_pwm_get_state(struct pwm_chip *chip, 112 + struct pwm_device *pwm, 113 + struct pwm_state *state) 114 114 { 115 115 struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip); 116 116 u64 clk_rate, tmp; ··· 118 118 unsigned int prescaler; 119 119 120 120 clk_rate = clk_get_rate(sun4i_pwm->clk); 121 + if (!clk_rate) 122 + return -EINVAL; 121 123 122 124 val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG); 123 125 ··· 134 132 state->duty_cycle = DIV_ROUND_UP_ULL(state->period, 2); 135 133 state->polarity = PWM_POLARITY_NORMAL; 136 134 state->enabled = true; 137 - return; 135 + return 0; 138 136 } 139 137 140 138 if ((PWM_REG_PRESCAL(val, pwm->hwpwm) == PWM_PRESCAL_MASK) && ··· 144 142 prescaler = prescaler_table[PWM_REG_PRESCAL(val, pwm->hwpwm)]; 145 143 146 144 if (prescaler == 0) 147 - return; 145 + return -EINVAL; 148 146 149 147 if (val & BIT_CH(PWM_ACT_STATE, pwm->hwpwm)) 150 148 state->polarity = PWM_POLARITY_NORMAL; ··· 164 162 165 163 tmp = (u64)prescaler * NSEC_PER_SEC * PWM_REG_PRD(val); 166 164 state->period = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate); 165 + 166 + return 0; 167 167 } 168 168 169 169 static int sun4i_pwm_calculate(struct sun4i_pwm_chip *sun4i_pwm,
+4 -2
drivers/pwm/pwm-sunplus.c
··· 124 124 return 0; 125 125 } 126 126 127 - static void sunplus_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, 128 - struct pwm_state *state) 127 + static int sunplus_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, 128 + struct pwm_state *state) 129 129 { 130 130 struct sunplus_pwm *priv = to_sunplus_pwm(chip); 131 131 u32 mode0, dd_freq, duty; ··· 155 155 } 156 156 157 157 state->polarity = PWM_POLARITY_NORMAL; 158 + 159 + return 0; 158 160 } 159 161 160 162 static const struct pwm_ops sunplus_pwm_ops = {
+13 -2
drivers/pwm/pwm-tegra.c
··· 145 145 * source clock rate as required_clk_rate, PWM controller will 146 146 * be able to configure the requested period. 147 147 */ 148 - required_clk_rate = 149 - (NSEC_PER_SEC / period_ns) << PWM_DUTY_WIDTH; 148 + required_clk_rate = DIV_ROUND_UP_ULL((u64)NSEC_PER_SEC << PWM_DUTY_WIDTH, 149 + period_ns); 150 + 151 + if (required_clk_rate > clk_round_rate(pc->clk, required_clk_rate)) 152 + /* 153 + * required_clk_rate is a lower bound for the input 154 + * rate; for lower rates there is no value for PWM_SCALE 155 + * that yields a period less than or equal to the 156 + * requested period. Hence, for lower rates, double the 157 + * required_clk_rate to get a clock rate that can meet 158 + * the requested period. 159 + */ 160 + required_clk_rate *= 2; 150 161 151 162 err = dev_pm_opp_set_rate(pc->dev, required_clk_rate); 152 163 if (err < 0)
+4 -2
drivers/pwm/pwm-visconti.c
··· 103 103 return 0; 104 104 } 105 105 106 - static void visconti_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, 107 - struct pwm_state *state) 106 + static int visconti_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, 107 + struct pwm_state *state) 108 108 { 109 109 struct visconti_pwm_chip *priv = visconti_pwm_from_chip(chip); 110 110 u32 period, duty, pwmc0, pwmc0_clk; ··· 122 122 state->polarity = PWM_POLARITY_NORMAL; 123 123 124 124 state->enabled = true; 125 + 126 + return 0; 125 127 } 126 128 127 129 static const struct pwm_ops visconti_pwm_ops = {
+5 -3
drivers/pwm/pwm-xilinx.c
··· 169 169 return 0; 170 170 } 171 171 172 - static void xilinx_pwm_get_state(struct pwm_chip *chip, 173 - struct pwm_device *unused, 174 - struct pwm_state *state) 172 + static int xilinx_pwm_get_state(struct pwm_chip *chip, 173 + struct pwm_device *unused, 174 + struct pwm_state *state) 175 175 { 176 176 struct xilinx_timer_priv *priv = xilinx_pwm_chip_to_priv(chip); 177 177 u32 tlr0, tlr1, tcsr0, tcsr1; ··· 191 191 */ 192 192 if (state->period == state->duty_cycle) 193 193 state->duty_cycle = 0; 194 + 195 + return 0; 194 196 } 195 197 196 198 static const struct pwm_ops xilinx_pwm_ops = {
+2 -2
include/linux/pwm.h
··· 276 276 struct pwm_capture *result, unsigned long timeout); 277 277 int (*apply)(struct pwm_chip *chip, struct pwm_device *pwm, 278 278 const struct pwm_state *state); 279 - void (*get_state)(struct pwm_chip *chip, struct pwm_device *pwm, 280 - struct pwm_state *state); 279 + int (*get_state)(struct pwm_chip *chip, struct pwm_device *pwm, 280 + struct pwm_state *state); 281 281 struct module *owner; 282 282 }; 283 283
+10 -10
include/trace/events/pwm.h
··· 10 10 11 11 DECLARE_EVENT_CLASS(pwm, 12 12 13 - TP_PROTO(struct pwm_device *pwm, const struct pwm_state *state), 13 + TP_PROTO(struct pwm_device *pwm, const struct pwm_state *state, int err), 14 14 15 - TP_ARGS(pwm, state), 15 + TP_ARGS(pwm, state, err), 16 16 17 17 TP_STRUCT__entry( 18 18 __field(struct pwm_device *, pwm) ··· 20 20 __field(u64, duty_cycle) 21 21 __field(enum pwm_polarity, polarity) 22 22 __field(bool, enabled) 23 + __field(int, err) 23 24 ), 24 25 25 26 TP_fast_assign( ··· 29 28 __entry->duty_cycle = state->duty_cycle; 30 29 __entry->polarity = state->polarity; 31 30 __entry->enabled = state->enabled; 31 + __entry->err = err; 32 32 ), 33 33 34 - TP_printk("%p: period=%llu duty_cycle=%llu polarity=%d enabled=%d", 34 + TP_printk("%p: period=%llu duty_cycle=%llu polarity=%d enabled=%d err=%d", 35 35 __entry->pwm, __entry->period, __entry->duty_cycle, 36 - __entry->polarity, __entry->enabled) 36 + __entry->polarity, __entry->enabled, __entry->err) 37 37 38 38 ); 39 39 40 40 DEFINE_EVENT(pwm, pwm_apply, 41 41 42 - TP_PROTO(struct pwm_device *pwm, const struct pwm_state *state), 42 + TP_PROTO(struct pwm_device *pwm, const struct pwm_state *state, int err), 43 43 44 - TP_ARGS(pwm, state) 45 - 44 + TP_ARGS(pwm, state, err) 46 45 ); 47 46 48 47 DEFINE_EVENT(pwm, pwm_get, 49 48 50 - TP_PROTO(struct pwm_device *pwm, const struct pwm_state *state), 49 + TP_PROTO(struct pwm_device *pwm, const struct pwm_state *state, int err), 51 50 52 - TP_ARGS(pwm, state) 53 - 51 + TP_ARGS(pwm, state, err) 54 52 ); 55 53 56 54 #endif /* _TRACE_PWM_H */