Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'char-misc-3.19-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc
Pull char/misc driver fixes from Greg KH:
"Here are three small driver fixes for reported issues for 3.19-rc5.
All of these have been in linux-next for a while with no reported
problems"
* tag 'char-misc-3.19-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc:
mcb: mcb-pci: Only remap the 1st 0x200 bytes of BAR 0
mei: add ABI documentation for fw_status exported through sysfs
mei: clean reset bit before reset
+46
-9
+15
Documentation/ABI/testing/sysfs-class-mei
+15
Documentation/ABI/testing/sysfs-class-mei
···
14
14
The /sys/class/mei/meiN directory is created for
15
15
each probed mei device
16
16
17
+
What: /sys/class/mei/meiN/fw_status
18
+
Date: Nov 2014
19
+
KernelVersion: 3.19
20
+
Contact: Tomas Winkler <tomas.winkler@intel.com>
21
+
Description: Display fw status registers content
22
+
23
+
The ME FW writes its status information into fw status
24
+
registers for BIOS and OS to monitor fw health.
25
+
26
+
The register contains running state, power management
27
+
state, error codes, and others. The way the registers
28
+
are decoded depends on PCH or SoC generation.
29
+
Also number of registers varies between 1 and 6
30
+
depending on generation.
31
+
+1
drivers/mcb/mcb-internal.h
+1
drivers/mcb/mcb-internal.h
+18
-9
drivers/mcb/mcb-pci.c
+18
-9
drivers/mcb/mcb-pci.c
···
17
17
18
18
struct priv {
19
19
struct mcb_bus *bus;
20
+
phys_addr_t mapbase;
20
21
void __iomem *base;
21
22
};
22
23
···
32
31
33
32
static int mcb_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
34
33
{
34
+
struct resource *res;
35
35
struct priv *priv;
36
-
phys_addr_t mapbase;
37
36
int ret;
38
37
int num_cells;
39
38
unsigned long flags;
···
48
47
return -ENODEV;
49
48
}
50
49
51
-
mapbase = pci_resource_start(pdev, 0);
52
-
if (!mapbase) {
50
+
priv->mapbase = pci_resource_start(pdev, 0);
51
+
if (!priv->mapbase) {
53
52
dev_err(&pdev->dev, "No PCI resource\n");
54
53
goto err_start;
55
54
}
56
55
57
-
ret = pci_request_region(pdev, 0, KBUILD_MODNAME);
58
-
if (ret) {
59
-
dev_err(&pdev->dev, "Failed to request PCI BARs\n");
56
+
res = request_mem_region(priv->mapbase, CHAM_HEADER_SIZE,
57
+
KBUILD_MODNAME);
58
+
if (IS_ERR(res)) {
59
+
dev_err(&pdev->dev, "Failed to request PCI memory\n");
60
+
ret = PTR_ERR(res);
60
61
goto err_start;
61
62
}
62
63
63
-
priv->base = pci_iomap(pdev, 0, 0);
64
+
priv->base = ioremap(priv->mapbase, CHAM_HEADER_SIZE);
64
65
if (!priv->base) {
65
66
dev_err(&pdev->dev, "Cannot ioremap\n");
66
67
ret = -ENOMEM;
···
87
84
88
85
priv->bus->get_irq = mcb_pci_get_irq;
89
86
90
-
ret = chameleon_parse_cells(priv->bus, mapbase, priv->base);
87
+
ret = chameleon_parse_cells(priv->bus, priv->mapbase, priv->base);
91
88
if (ret < 0)
92
89
goto err_drvdata;
93
90
num_cells = ret;
···
96
93
97
94
mcb_bus_add_devices(priv->bus);
98
95
96
+
return 0;
97
+
99
98
err_drvdata:
100
-
pci_iounmap(pdev, priv->base);
99
+
iounmap(priv->base);
101
100
err_ioremap:
102
101
pci_release_region(pdev, 0);
103
102
err_start:
···
112
107
struct priv *priv = pci_get_drvdata(pdev);
113
108
114
109
mcb_release_bus(priv->bus);
110
+
111
+
iounmap(priv->base);
112
+
release_region(priv->mapbase, CHAM_HEADER_SIZE);
113
+
pci_disable_device(pdev);
115
114
}
116
115
117
116
static const struct pci_device_id mcb_pci_tbl[] = {
+12
drivers/misc/mei/hw-me.c
+12
drivers/misc/mei/hw-me.c
···
234
234
struct mei_me_hw *hw = to_me_hw(dev);
235
235
u32 hcsr = mei_hcsr_read(hw);
236
236
237
+
/* H_RST may be found lit before reset is started,
238
+
* for example if preceding reset flow hasn't completed.
239
+
* In that case asserting H_RST will be ignored, therefore
240
+
* we need to clean H_RST bit to start a successful reset sequence.
241
+
*/
242
+
if ((hcsr & H_RST) == H_RST) {
243
+
dev_warn(dev->dev, "H_RST is set = 0x%08X", hcsr);
244
+
hcsr &= ~H_RST;
245
+
mei_me_reg_write(hw, H_CSR, hcsr);
246
+
hcsr = mei_hcsr_read(hw);
247
+
}
248
+
237
249
hcsr |= H_RST | H_IG | H_IS;
238
250
239
251
if (intr_enable)