Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
interconnect: qcom: Add MSM8996 interconnect provider driver
Add a driver for the MSM8996 NoCs. This chip is similar to SDM660 where
some busses are controlled by RPM, while others directly by the AP with
writes to QoS registers.
Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com>
Link: https://lore.kernel.org/r/20211021132329.234942-5-y.oudjana@protonmail.com
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> #db820c
Signed-off-by: Georgi Djakov <djakov@kernel.org>
authored by
Yassine Oudjana
and committed by
Georgi Djakov
7add937f
3e9fdc6b
+2263
+9
drivers/interconnect/qcom/Kconfig
+9
drivers/interconnect/qcom/Kconfig
···
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This is a driver for the Qualcomm Network-on-Chip on msm8974-based
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platforms.
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config INTERCONNECT_QCOM_MSM8996
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tristate "Qualcomm MSM8996 interconnect driver"
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depends on INTERCONNECT_QCOM
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depends on QCOM_SMD_RPM
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select INTERCONNECT_QCOM_SMD_RPM
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help
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This is a driver for the Qualcomm Network-on-Chip on msm8996-based
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platforms.
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+
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config INTERCONNECT_QCOM_OSM_L3
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tristate "Qualcomm OSM L3 interconnect driver"
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depends on INTERCONNECT_QCOM || COMPILE_TEST
+2
drivers/interconnect/qcom/Makefile
+2
drivers/interconnect/qcom/Makefile
···
4
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qnoc-msm8916-objs := msm8916.o
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5
qnoc-msm8939-objs := msm8939.o
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qnoc-msm8974-objs := msm8974.o
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qnoc-msm8996-objs := msm8996.o
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icc-osm-l3-objs := osm-l3.o
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qnoc-qcs404-objs := qcs404.o
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icc-rpmh-obj := icc-rpmh.o
···
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obj-$(CONFIG_INTERCONNECT_QCOM_MSM8916) += qnoc-msm8916.o
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obj-$(CONFIG_INTERCONNECT_QCOM_MSM8939) += qnoc-msm8939.o
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obj-$(CONFIG_INTERCONNECT_QCOM_MSM8974) += qnoc-msm8974.o
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+
obj-$(CONFIG_INTERCONNECT_QCOM_MSM8996) += qnoc-msm8996.o
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obj-$(CONFIG_INTERCONNECT_QCOM_OSM_L3) += icc-osm-l3.o
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obj-$(CONFIG_INTERCONNECT_QCOM_QCS404) += qnoc-qcs404.o
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obj-$(CONFIG_INTERCONNECT_QCOM_RPMH) += icc-rpmh.o
+2103
drivers/interconnect/qcom/msm8996.c
+2103
drivers/interconnect/qcom/msm8996.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/*
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* Qualcomm MSM8996 Network-on-Chip (NoC) QoS driver
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*
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* Copyright (c) 2021 Yassine Oudjana <y.oudjana@protonmail.com>
6
+
*/
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+
8
+
#include <linux/clk.h>
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#include <linux/device.h>
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#include <linux/interconnect-provider.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/of_platform.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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+
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#include <dt-bindings/interconnect/qcom,msm8996.h>
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+
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#include "icc-rpm.h"
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#include "smd-rpm.h"
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#include "msm8996.h"
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+
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static const char * const bus_mm_clocks[] = {
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"bus",
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"bus_a",
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"iface"
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};
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+
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static const char * const bus_a0noc_clocks[] = {
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"aggre0_snoc_axi",
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"aggre0_cnoc_ahb",
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"aggre0_noc_mpu_cfg"
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};
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+
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static const u16 mas_a0noc_common_links[] = {
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MSM8996_SLAVE_A0NOC_SNOC
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};
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+
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static struct qcom_icc_node mas_pcie_0 = {
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.name = "mas_pcie_0",
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.id = MSM8996_MASTER_PCIE_0,
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.buswidth = 8,
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.mas_rpm_id = 65,
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.slv_rpm_id = -1,
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.qos.ap_owned = true,
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.qos.qos_mode = NOC_QOS_MODE_FIXED,
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.qos.areq_prio = 1,
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.qos.prio_level = 1,
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.qos.qos_port = 0,
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.num_links = ARRAY_SIZE(mas_a0noc_common_links),
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.links = mas_a0noc_common_links
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};
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+
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static struct qcom_icc_node mas_pcie_1 = {
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.name = "mas_pcie_1",
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.id = MSM8996_MASTER_PCIE_1,
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.buswidth = 8,
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.mas_rpm_id = 66,
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.slv_rpm_id = -1,
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.qos.ap_owned = true,
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.qos.qos_mode = NOC_QOS_MODE_FIXED,
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.qos.areq_prio = 1,
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.qos.prio_level = 1,
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.qos.qos_port = 1,
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.num_links = ARRAY_SIZE(mas_a0noc_common_links),
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.links = mas_a0noc_common_links
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};
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+
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static struct qcom_icc_node mas_pcie_2 = {
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.name = "mas_pcie_2",
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.id = MSM8996_MASTER_PCIE_2,
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.buswidth = 8,
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.mas_rpm_id = 119,
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.slv_rpm_id = -1,
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.qos.ap_owned = true,
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.qos.qos_mode = NOC_QOS_MODE_FIXED,
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.qos.areq_prio = 1,
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.qos.prio_level = 1,
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.qos.qos_port = 2,
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.num_links = ARRAY_SIZE(mas_a0noc_common_links),
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.links = mas_a0noc_common_links
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};
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static const u16 mas_a1noc_common_links[] = {
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MSM8996_SLAVE_A1NOC_SNOC
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};
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static struct qcom_icc_node mas_cnoc_a1noc = {
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.name = "mas_cnoc_a1noc",
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.id = MSM8996_MASTER_CNOC_A1NOC,
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.buswidth = 8,
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.mas_rpm_id = 116,
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.slv_rpm_id = -1,
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.qos.ap_owned = true,
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.qos.qos_mode = NOC_QOS_MODE_INVALID,
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.num_links = ARRAY_SIZE(mas_a1noc_common_links),
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.links = mas_a1noc_common_links
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};
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+
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static struct qcom_icc_node mas_crypto_c0 = {
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.name = "mas_crypto_c0",
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.id = MSM8996_MASTER_CRYPTO_CORE0,
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.buswidth = 8,
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.mas_rpm_id = 23,
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.slv_rpm_id = -1,
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.qos.ap_owned = true,
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.qos.qos_mode = NOC_QOS_MODE_FIXED,
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.qos.areq_prio = 1,
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.qos.prio_level = 1,
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.qos.qos_port = 0,
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.num_links = ARRAY_SIZE(mas_a1noc_common_links),
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.links = mas_a1noc_common_links
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};
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+
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static struct qcom_icc_node mas_pnoc_a1noc = {
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.name = "mas_pnoc_a1noc",
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.id = MSM8996_MASTER_PNOC_A1NOC,
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.buswidth = 8,
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.mas_rpm_id = 117,
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.slv_rpm_id = -1,
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.qos.ap_owned = false,
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.qos.qos_mode = NOC_QOS_MODE_FIXED,
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.qos.areq_prio = 0,
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.qos.prio_level = 0,
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.qos.qos_port = 1,
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.num_links = ARRAY_SIZE(mas_a1noc_common_links),
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.links = mas_a1noc_common_links
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};
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+
131
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static const u16 mas_a2noc_common_links[] = {
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MSM8996_SLAVE_A2NOC_SNOC
133
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};
134
+
135
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static struct qcom_icc_node mas_usb3 = {
136
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.name = "mas_usb3",
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.id = MSM8996_MASTER_USB3,
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.buswidth = 8,
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.mas_rpm_id = 32,
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.slv_rpm_id = -1,
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.qos.ap_owned = true,
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.qos.qos_mode = NOC_QOS_MODE_FIXED,
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.qos.areq_prio = 1,
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.qos.prio_level = 1,
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.qos.qos_port = 3,
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.num_links = ARRAY_SIZE(mas_a2noc_common_links),
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.links = mas_a2noc_common_links
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};
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+
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static struct qcom_icc_node mas_ipa = {
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.name = "mas_ipa",
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.id = MSM8996_MASTER_IPA,
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.buswidth = 8,
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.mas_rpm_id = 59,
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.slv_rpm_id = -1,
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.qos.ap_owned = true,
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.qos.qos_mode = NOC_QOS_MODE_FIXED,
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.qos.areq_prio = 0,
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.qos.prio_level = 0,
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.qos.qos_port = -1,
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.num_links = ARRAY_SIZE(mas_a2noc_common_links),
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.links = mas_a2noc_common_links
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};
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+
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static struct qcom_icc_node mas_ufs = {
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.name = "mas_ufs",
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.id = MSM8996_MASTER_UFS,
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.buswidth = 8,
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.mas_rpm_id = 68,
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.slv_rpm_id = -1,
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.qos.ap_owned = true,
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.qos.qos_mode = NOC_QOS_MODE_FIXED,
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.qos.areq_prio = 1,
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.qos.prio_level = 1,
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.qos.qos_port = 2,
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.num_links = ARRAY_SIZE(mas_a2noc_common_links),
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.links = mas_a2noc_common_links
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};
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+
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static const u16 mas_apps_proc_links[] = {
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MSM8996_SLAVE_BIMC_SNOC_1,
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MSM8996_SLAVE_EBI_CH0,
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MSM8996_SLAVE_BIMC_SNOC_0
184
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};
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static struct qcom_icc_node mas_apps_proc = {
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.name = "mas_apps_proc",
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.id = MSM8996_MASTER_AMPSS_M0,
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.buswidth = 8,
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.mas_rpm_id = 0,
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.slv_rpm_id = -1,
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.qos.ap_owned = true,
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.qos.qos_mode = NOC_QOS_MODE_FIXED,
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.qos.areq_prio = 0,
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.qos.prio_level = 0,
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.qos.qos_port = 0,
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.num_links = ARRAY_SIZE(mas_apps_proc_links),
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.links = mas_apps_proc_links
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};
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+
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static const u16 mas_oxili_common_links[] = {
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MSM8996_SLAVE_BIMC_SNOC_1,
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MSM8996_SLAVE_HMSS_L3,
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MSM8996_SLAVE_EBI_CH0,
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MSM8996_SLAVE_BIMC_SNOC_0
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};
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+
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static struct qcom_icc_node mas_oxili = {
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.name = "mas_oxili",
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.id = MSM8996_MASTER_GRAPHICS_3D,
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.buswidth = 8,
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.mas_rpm_id = 6,
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.slv_rpm_id = -1,
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.qos.ap_owned = true,
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.qos.qos_mode = NOC_QOS_MODE_BYPASS,
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.qos.areq_prio = 0,
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.qos.prio_level = 0,
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.qos.qos_port = 1,
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.num_links = ARRAY_SIZE(mas_oxili_common_links),
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.links = mas_oxili_common_links
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};
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+
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static struct qcom_icc_node mas_mnoc_bimc = {
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.name = "mas_mnoc_bimc",
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.id = MSM8996_MASTER_MNOC_BIMC,
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.buswidth = 8,
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.mas_rpm_id = 2,
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.slv_rpm_id = -1,
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.qos.ap_owned = true,
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.qos.qos_mode = NOC_QOS_MODE_BYPASS,
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.qos.areq_prio = 0,
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.qos.prio_level = 0,
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.qos.qos_port = 2,
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.num_links = ARRAY_SIZE(mas_oxili_common_links),
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.links = mas_oxili_common_links
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};
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+
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static const u16 mas_snoc_bimc_links[] = {
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MSM8996_SLAVE_HMSS_L3,
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MSM8996_SLAVE_EBI_CH0
241
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};
242
+
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static struct qcom_icc_node mas_snoc_bimc = {
244
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.name = "mas_snoc_bimc",
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.id = MSM8996_MASTER_SNOC_BIMC,
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.buswidth = 8,
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.mas_rpm_id = 3,
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.slv_rpm_id = -1,
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.qos.ap_owned = false,
250
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.qos.qos_mode = NOC_QOS_MODE_BYPASS,
251
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.qos.areq_prio = 0,
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.qos.prio_level = 0,
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.qos.qos_port = -1,
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.num_links = ARRAY_SIZE(mas_snoc_bimc_links),
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.links = mas_snoc_bimc_links
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};
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+
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static const u16 mas_snoc_cnoc_links[] = {
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MSM8996_SLAVE_CLK_CTL,
260
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MSM8996_SLAVE_RBCPR_CX,
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MSM8996_SLAVE_A2NOC_SMMU_CFG,
262
+
MSM8996_SLAVE_A0NOC_MPU_CFG,
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+
MSM8996_SLAVE_MESSAGE_RAM,
264
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MSM8996_SLAVE_CNOC_MNOC_MMSS_CFG,
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MSM8996_SLAVE_PCIE_0_CFG,
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MSM8996_SLAVE_TLMM,
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+
MSM8996_SLAVE_MPM,
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MSM8996_SLAVE_A0NOC_SMMU_CFG,
269
+
MSM8996_SLAVE_EBI1_PHY_CFG,
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+
MSM8996_SLAVE_BIMC_CFG,
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+
MSM8996_SLAVE_PIMEM_CFG,
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+
MSM8996_SLAVE_RBCPR_MX,
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+
MSM8996_SLAVE_PRNG,
274
+
MSM8996_SLAVE_PCIE20_AHB2PHY,
275
+
MSM8996_SLAVE_A2NOC_MPU_CFG,
276
+
MSM8996_SLAVE_QDSS_CFG,
277
+
MSM8996_SLAVE_A2NOC_CFG,
278
+
MSM8996_SLAVE_A0NOC_CFG,
279
+
MSM8996_SLAVE_UFS_CFG,
280
+
MSM8996_SLAVE_CRYPTO_0_CFG,
281
+
MSM8996_SLAVE_PCIE_1_CFG,
282
+
MSM8996_SLAVE_SNOC_CFG,
283
+
MSM8996_SLAVE_SNOC_MPU_CFG,
284
+
MSM8996_SLAVE_A1NOC_MPU_CFG,
285
+
MSM8996_SLAVE_A1NOC_SMMU_CFG,
286
+
MSM8996_SLAVE_PCIE_2_CFG,
287
+
MSM8996_SLAVE_CNOC_MNOC_CFG,
288
+
MSM8996_SLAVE_QDSS_RBCPR_APU_CFG,
289
+
MSM8996_SLAVE_PMIC_ARB,
290
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MSM8996_SLAVE_IMEM_CFG,
291
+
MSM8996_SLAVE_A1NOC_CFG,
292
+
MSM8996_SLAVE_SSC_CFG,
293
+
MSM8996_SLAVE_TCSR,
294
+
MSM8996_SLAVE_LPASS_SMMU_CFG,
295
+
MSM8996_SLAVE_DCC_CFG
296
+
};
297
+
298
+
static struct qcom_icc_node mas_snoc_cnoc = {
299
+
.name = "mas_snoc_cnoc",
300
+
.id = MSM8996_MASTER_SNOC_CNOC,
301
+
.buswidth = 8,
302
+
.mas_rpm_id = 52,
303
+
.slv_rpm_id = -1,
304
+
.num_links = ARRAY_SIZE(mas_snoc_cnoc_links),
305
+
.links = mas_snoc_cnoc_links
306
+
};
307
+
308
+
static const u16 mas_qdss_dap_links[] = {
309
+
MSM8996_SLAVE_QDSS_RBCPR_APU_CFG,
310
+
MSM8996_SLAVE_RBCPR_CX,
311
+
MSM8996_SLAVE_A2NOC_SMMU_CFG,
312
+
MSM8996_SLAVE_A0NOC_MPU_CFG,
313
+
MSM8996_SLAVE_MESSAGE_RAM,
314
+
MSM8996_SLAVE_PCIE_0_CFG,
315
+
MSM8996_SLAVE_TLMM,
316
+
MSM8996_SLAVE_MPM,
317
+
MSM8996_SLAVE_A0NOC_SMMU_CFG,
318
+
MSM8996_SLAVE_EBI1_PHY_CFG,
319
+
MSM8996_SLAVE_BIMC_CFG,
320
+
MSM8996_SLAVE_PIMEM_CFG,
321
+
MSM8996_SLAVE_RBCPR_MX,
322
+
MSM8996_SLAVE_CLK_CTL,
323
+
MSM8996_SLAVE_PRNG,
324
+
MSM8996_SLAVE_PCIE20_AHB2PHY,
325
+
MSM8996_SLAVE_A2NOC_MPU_CFG,
326
+
MSM8996_SLAVE_QDSS_CFG,
327
+
MSM8996_SLAVE_A2NOC_CFG,
328
+
MSM8996_SLAVE_A0NOC_CFG,
329
+
MSM8996_SLAVE_UFS_CFG,
330
+
MSM8996_SLAVE_CRYPTO_0_CFG,
331
+
MSM8996_SLAVE_CNOC_A1NOC,
332
+
MSM8996_SLAVE_PCIE_1_CFG,
333
+
MSM8996_SLAVE_SNOC_CFG,
334
+
MSM8996_SLAVE_SNOC_MPU_CFG,
335
+
MSM8996_SLAVE_A1NOC_MPU_CFG,
336
+
MSM8996_SLAVE_A1NOC_SMMU_CFG,
337
+
MSM8996_SLAVE_PCIE_2_CFG,
338
+
MSM8996_SLAVE_CNOC_MNOC_CFG,
339
+
MSM8996_SLAVE_CNOC_MNOC_MMSS_CFG,
340
+
MSM8996_SLAVE_PMIC_ARB,
341
+
MSM8996_SLAVE_IMEM_CFG,
342
+
MSM8996_SLAVE_A1NOC_CFG,
343
+
MSM8996_SLAVE_SSC_CFG,
344
+
MSM8996_SLAVE_TCSR,
345
+
MSM8996_SLAVE_LPASS_SMMU_CFG,
346
+
MSM8996_SLAVE_DCC_CFG
347
+
};
348
+
349
+
static struct qcom_icc_node mas_qdss_dap = {
350
+
.name = "mas_qdss_dap",
351
+
.id = MSM8996_MASTER_QDSS_DAP,
352
+
.buswidth = 8,
353
+
.mas_rpm_id = 49,
354
+
.slv_rpm_id = -1,
355
+
.qos.ap_owned = true,
356
+
.qos.qos_mode = NOC_QOS_MODE_INVALID,
357
+
.num_links = ARRAY_SIZE(mas_qdss_dap_links),
358
+
.links = mas_qdss_dap_links
359
+
};
360
+
361
+
static const u16 mas_cnoc_mnoc_mmss_cfg_links[] = {
362
+
MSM8996_SLAVE_MMAGIC_CFG,
363
+
MSM8996_SLAVE_DSA_MPU_CFG,
364
+
MSM8996_SLAVE_MMSS_CLK_CFG,
365
+
MSM8996_SLAVE_CAMERA_THROTTLE_CFG,
366
+
MSM8996_SLAVE_VENUS_CFG,
367
+
MSM8996_SLAVE_SMMU_VFE_CFG,
368
+
MSM8996_SLAVE_MISC_CFG,
369
+
MSM8996_SLAVE_SMMU_CPP_CFG,
370
+
MSM8996_SLAVE_GRAPHICS_3D_CFG,
371
+
MSM8996_SLAVE_DISPLAY_THROTTLE_CFG,
372
+
MSM8996_SLAVE_VENUS_THROTTLE_CFG,
373
+
MSM8996_SLAVE_CAMERA_CFG,
374
+
MSM8996_SLAVE_DISPLAY_CFG,
375
+
MSM8996_SLAVE_CPR_CFG,
376
+
MSM8996_SLAVE_SMMU_ROTATOR_CFG,
377
+
MSM8996_SLAVE_DSA_CFG,
378
+
MSM8996_SLAVE_SMMU_VENUS_CFG,
379
+
MSM8996_SLAVE_VMEM_CFG,
380
+
MSM8996_SLAVE_SMMU_JPEG_CFG,
381
+
MSM8996_SLAVE_SMMU_MDP_CFG,
382
+
MSM8996_SLAVE_MNOC_MPU_CFG
383
+
};
384
+
385
+
static struct qcom_icc_node mas_cnoc_mnoc_mmss_cfg = {
386
+
.name = "mas_cnoc_mnoc_mmss_cfg",
387
+
.id = MSM8996_MASTER_CNOC_MNOC_MMSS_CFG,
388
+
.buswidth = 8,
389
+
.mas_rpm_id = 4,
390
+
.slv_rpm_id = -1,
391
+
.qos.ap_owned = true,
392
+
.qos.qos_mode = NOC_QOS_MODE_INVALID,
393
+
.num_links = ARRAY_SIZE(mas_cnoc_mnoc_mmss_cfg_links),
394
+
.links = mas_cnoc_mnoc_mmss_cfg_links
395
+
};
396
+
397
+
static const u16 mas_cnoc_mnoc_cfg_links[] = {
398
+
MSM8996_SLAVE_SERVICE_MNOC
399
+
};
400
+
401
+
static struct qcom_icc_node mas_cnoc_mnoc_cfg = {
402
+
.name = "mas_cnoc_mnoc_cfg",
403
+
.id = MSM8996_MASTER_CNOC_MNOC_CFG,
404
+
.buswidth = 8,
405
+
.mas_rpm_id = 5,
406
+
.slv_rpm_id = -1,
407
+
.qos.ap_owned = true,
408
+
.qos.qos_mode = NOC_QOS_MODE_INVALID,
409
+
.num_links = ARRAY_SIZE(mas_cnoc_mnoc_cfg_links),
410
+
.links = mas_cnoc_mnoc_cfg_links
411
+
};
412
+
413
+
static const u16 mas_mnoc_bimc_common_links[] = {
414
+
MSM8996_SLAVE_MNOC_BIMC
415
+
};
416
+
417
+
static struct qcom_icc_node mas_cpp = {
418
+
.name = "mas_cpp",
419
+
.id = MSM8996_MASTER_CPP,
420
+
.buswidth = 32,
421
+
.mas_rpm_id = 115,
422
+
.slv_rpm_id = -1,
423
+
.qos.ap_owned = true,
424
+
.qos.qos_mode = NOC_QOS_MODE_BYPASS,
425
+
.qos.areq_prio = 0,
426
+
.qos.prio_level = 0,
427
+
.qos.qos_port = 5,
428
+
.num_links = ARRAY_SIZE(mas_mnoc_bimc_common_links),
429
+
.links = mas_mnoc_bimc_common_links
430
+
};
431
+
432
+
static struct qcom_icc_node mas_jpeg = {
433
+
.name = "mas_jpeg",
434
+
.id = MSM8996_MASTER_JPEG,
435
+
.buswidth = 32,
436
+
.mas_rpm_id = 7,
437
+
.slv_rpm_id = -1,
438
+
.qos.ap_owned = true,
439
+
.qos.qos_mode = NOC_QOS_MODE_BYPASS,
440
+
.qos.areq_prio = 0,
441
+
.qos.prio_level = 0,
442
+
.qos.qos_port = 7,
443
+
.num_links = ARRAY_SIZE(mas_mnoc_bimc_common_links),
444
+
.links = mas_mnoc_bimc_common_links
445
+
};
446
+
447
+
static struct qcom_icc_node mas_mdp_p0 = {
448
+
.name = "mas_mdp_p0",
449
+
.id = MSM8996_MASTER_MDP_PORT0,
450
+
.buswidth = 32,
451
+
.mas_rpm_id = 8,
452
+
.slv_rpm_id = -1,
453
+
.qos.ap_owned = true,
454
+
.qos.qos_mode = NOC_QOS_MODE_BYPASS,
455
+
.qos.areq_prio = 0,
456
+
.qos.prio_level = 0,
457
+
.qos.qos_port = 1,
458
+
.num_links = ARRAY_SIZE(mas_mnoc_bimc_common_links),
459
+
.links = mas_mnoc_bimc_common_links
460
+
};
461
+
462
+
static struct qcom_icc_node mas_mdp_p1 = {
463
+
.name = "mas_mdp_p1",
464
+
.id = MSM8996_MASTER_MDP_PORT1,
465
+
.buswidth = 32,
466
+
.mas_rpm_id = 61,
467
+
.slv_rpm_id = -1,
468
+
.qos.ap_owned = true,
469
+
.qos.qos_mode = NOC_QOS_MODE_BYPASS,
470
+
.qos.areq_prio = 0,
471
+
.qos.prio_level = 0,
472
+
.qos.qos_port = 2,
473
+
.num_links = ARRAY_SIZE(mas_mnoc_bimc_common_links),
474
+
.links = mas_mnoc_bimc_common_links
475
+
};
476
+
477
+
static struct qcom_icc_node mas_rotator = {
478
+
.name = "mas_rotator",
479
+
.id = MSM8996_MASTER_ROTATOR,
480
+
.buswidth = 32,
481
+
.mas_rpm_id = 120,
482
+
.slv_rpm_id = -1,
483
+
.qos.ap_owned = true,
484
+
.qos.qos_mode = NOC_QOS_MODE_BYPASS,
485
+
.qos.areq_prio = 0,
486
+
.qos.prio_level = 0,
487
+
.qos.qos_port = 0,
488
+
.num_links = ARRAY_SIZE(mas_mnoc_bimc_common_links),
489
+
.links = mas_mnoc_bimc_common_links
490
+
};
491
+
492
+
static struct qcom_icc_node mas_venus = {
493
+
.name = "mas_venus",
494
+
.id = MSM8996_MASTER_VIDEO_P0,
495
+
.buswidth = 32,
496
+
.mas_rpm_id = 9,
497
+
.slv_rpm_id = -1,
498
+
.qos.ap_owned = true,
499
+
.qos.qos_mode = NOC_QOS_MODE_BYPASS,
500
+
.qos.areq_prio = 0,
501
+
.qos.prio_level = 0,
502
+
.qos.qos_port = 3,
503
+
.num_links = ARRAY_SIZE(mas_mnoc_bimc_common_links),
504
+
.links = mas_mnoc_bimc_common_links
505
+
};
506
+
507
+
static struct qcom_icc_node mas_vfe = {
508
+
.name = "mas_vfe",
509
+
.id = MSM8996_MASTER_VFE,
510
+
.buswidth = 32,
511
+
.mas_rpm_id = 11,
512
+
.slv_rpm_id = -1,
513
+
.qos.ap_owned = true,
514
+
.qos.qos_mode = NOC_QOS_MODE_BYPASS,
515
+
.qos.areq_prio = 0,
516
+
.qos.prio_level = 0,
517
+
.qos.qos_port = 6,
518
+
.num_links = ARRAY_SIZE(mas_mnoc_bimc_common_links),
519
+
.links = mas_mnoc_bimc_common_links
520
+
};
521
+
522
+
static const u16 mas_vmem_common_links[] = {
523
+
MSM8996_SLAVE_VMEM
524
+
};
525
+
526
+
static struct qcom_icc_node mas_snoc_vmem = {
527
+
.name = "mas_snoc_vmem",
528
+
.id = MSM8996_MASTER_SNOC_VMEM,
529
+
.buswidth = 32,
530
+
.mas_rpm_id = 114,
531
+
.slv_rpm_id = -1,
532
+
.qos.ap_owned = true,
533
+
.qos.qos_mode = NOC_QOS_MODE_INVALID,
534
+
.num_links = ARRAY_SIZE(mas_vmem_common_links),
535
+
.links = mas_vmem_common_links
536
+
};
537
+
538
+
static struct qcom_icc_node mas_venus_vmem = {
539
+
.name = "mas_venus_vmem",
540
+
.id = MSM8996_MASTER_VIDEO_P0_OCMEM,
541
+
.buswidth = 32,
542
+
.mas_rpm_id = 121,
543
+
.slv_rpm_id = -1,
544
+
.qos.ap_owned = true,
545
+
.qos.qos_mode = NOC_QOS_MODE_INVALID,
546
+
.num_links = ARRAY_SIZE(mas_vmem_common_links),
547
+
.links = mas_vmem_common_links
548
+
};
549
+
550
+
static const u16 mas_snoc_pnoc_links[] = {
551
+
MSM8996_SLAVE_BLSP_1,
552
+
MSM8996_SLAVE_BLSP_2,
553
+
MSM8996_SLAVE_SDCC_1,
554
+
MSM8996_SLAVE_SDCC_2,
555
+
MSM8996_SLAVE_SDCC_4,
556
+
MSM8996_SLAVE_TSIF,
557
+
MSM8996_SLAVE_PDM,
558
+
MSM8996_SLAVE_AHB2PHY
559
+
};
560
+
561
+
static struct qcom_icc_node mas_snoc_pnoc = {
562
+
.name = "mas_snoc_pnoc",
563
+
.id = MSM8996_MASTER_SNOC_PNOC,
564
+
.buswidth = 8,
565
+
.mas_rpm_id = 44,
566
+
.slv_rpm_id = -1,
567
+
.num_links = ARRAY_SIZE(mas_snoc_pnoc_links),
568
+
.links = mas_snoc_pnoc_links
569
+
};
570
+
571
+
static const u16 mas_pnoc_a1noc_common_links[] = {
572
+
MSM8996_SLAVE_PNOC_A1NOC
573
+
};
574
+
575
+
static struct qcom_icc_node mas_sdcc_1 = {
576
+
.name = "mas_sdcc_1",
577
+
.id = MSM8996_MASTER_SDCC_1,
578
+
.buswidth = 8,
579
+
.mas_rpm_id = 33,
580
+
.slv_rpm_id = -1,
581
+
.num_links = ARRAY_SIZE(mas_pnoc_a1noc_common_links),
582
+
.links = mas_pnoc_a1noc_common_links
583
+
};
584
+
585
+
static struct qcom_icc_node mas_sdcc_2 = {
586
+
.name = "mas_sdcc_2",
587
+
.id = MSM8996_MASTER_SDCC_2,
588
+
.buswidth = 8,
589
+
.mas_rpm_id = 35,
590
+
.slv_rpm_id = -1,
591
+
.num_links = ARRAY_SIZE(mas_pnoc_a1noc_common_links),
592
+
.links = mas_pnoc_a1noc_common_links
593
+
};
594
+
595
+
static struct qcom_icc_node mas_sdcc_4 = {
596
+
.name = "mas_sdcc_4",
597
+
.id = MSM8996_MASTER_SDCC_4,
598
+
.buswidth = 8,
599
+
.mas_rpm_id = 36,
600
+
.slv_rpm_id = -1,
601
+
.num_links = ARRAY_SIZE(mas_pnoc_a1noc_common_links),
602
+
.links = mas_pnoc_a1noc_common_links
603
+
};
604
+
605
+
static struct qcom_icc_node mas_usb_hs = {
606
+
.name = "mas_usb_hs",
607
+
.id = MSM8996_MASTER_USB_HS,
608
+
.buswidth = 8,
609
+
.mas_rpm_id = 42,
610
+
.slv_rpm_id = -1,
611
+
.num_links = ARRAY_SIZE(mas_pnoc_a1noc_common_links),
612
+
.links = mas_pnoc_a1noc_common_links
613
+
};
614
+
615
+
static struct qcom_icc_node mas_blsp_1 = {
616
+
.name = "mas_blsp_1",
617
+
.id = MSM8996_MASTER_BLSP_1,
618
+
.buswidth = 4,
619
+
.mas_rpm_id = 41,
620
+
.slv_rpm_id = -1,
621
+
.num_links = ARRAY_SIZE(mas_pnoc_a1noc_common_links),
622
+
.links = mas_pnoc_a1noc_common_links
623
+
};
624
+
625
+
static struct qcom_icc_node mas_blsp_2 = {
626
+
.name = "mas_blsp_2",
627
+
.id = MSM8996_MASTER_BLSP_2,
628
+
.buswidth = 4,
629
+
.mas_rpm_id = 39,
630
+
.slv_rpm_id = -1,
631
+
.num_links = ARRAY_SIZE(mas_pnoc_a1noc_common_links),
632
+
.links = mas_pnoc_a1noc_common_links
633
+
};
634
+
635
+
static struct qcom_icc_node mas_tsif = {
636
+
.name = "mas_tsif",
637
+
.id = MSM8996_MASTER_TSIF,
638
+
.buswidth = 4,
639
+
.mas_rpm_id = 37,
640
+
.slv_rpm_id = -1,
641
+
.num_links = ARRAY_SIZE(mas_pnoc_a1noc_common_links),
642
+
.links = mas_pnoc_a1noc_common_links
643
+
};
644
+
645
+
static const u16 mas_hmss_links[] = {
646
+
MSM8996_SLAVE_PIMEM,
647
+
MSM8996_SLAVE_OCIMEM,
648
+
MSM8996_SLAVE_SNOC_BIMC
649
+
};
650
+
651
+
static struct qcom_icc_node mas_hmss = {
652
+
.name = "mas_hmss",
653
+
.id = MSM8996_MASTER_HMSS,
654
+
.buswidth = 8,
655
+
.mas_rpm_id = 118,
656
+
.slv_rpm_id = -1,
657
+
.qos.ap_owned = true,
658
+
.qos.qos_mode = NOC_QOS_MODE_FIXED,
659
+
.qos.areq_prio = 1,
660
+
.qos.prio_level = 1,
661
+
.qos.qos_port = 4,
662
+
.num_links = ARRAY_SIZE(mas_hmss_links),
663
+
.links = mas_hmss_links
664
+
};
665
+
666
+
static const u16 mas_qdss_common_links[] = {
667
+
MSM8996_SLAVE_PIMEM,
668
+
MSM8996_SLAVE_USB3,
669
+
MSM8996_SLAVE_OCIMEM,
670
+
MSM8996_SLAVE_SNOC_BIMC,
671
+
MSM8996_SLAVE_SNOC_PNOC
672
+
};
673
+
674
+
static struct qcom_icc_node mas_qdss_bam = {
675
+
.name = "mas_qdss_bam",
676
+
.id = MSM8996_MASTER_QDSS_BAM,
677
+
.buswidth = 16,
678
+
.mas_rpm_id = 19,
679
+
.slv_rpm_id = -1,
680
+
.qos.ap_owned = true,
681
+
.qos.qos_mode = NOC_QOS_MODE_FIXED,
682
+
.qos.areq_prio = 1,
683
+
.qos.prio_level = 1,
684
+
.qos.qos_port = 2,
685
+
.num_links = ARRAY_SIZE(mas_qdss_common_links),
686
+
.links = mas_qdss_common_links
687
+
};
688
+
689
+
static const u16 mas_snoc_cfg_links[] = {
690
+
MSM8996_SLAVE_SERVICE_SNOC
691
+
};
692
+
693
+
static struct qcom_icc_node mas_snoc_cfg = {
694
+
.name = "mas_snoc_cfg",
695
+
.id = MSM8996_MASTER_SNOC_CFG,
696
+
.buswidth = 16,
697
+
.mas_rpm_id = 20,
698
+
.slv_rpm_id = -1,
699
+
.qos.ap_owned = true,
700
+
.qos.qos_mode = NOC_QOS_MODE_INVALID,
701
+
.num_links = ARRAY_SIZE(mas_snoc_cfg_links),
702
+
.links = mas_snoc_cfg_links
703
+
};
704
+
705
+
static const u16 mas_bimc_snoc_0_links[] = {
706
+
MSM8996_SLAVE_SNOC_VMEM,
707
+
MSM8996_SLAVE_USB3,
708
+
MSM8996_SLAVE_PIMEM,
709
+
MSM8996_SLAVE_LPASS,
710
+
MSM8996_SLAVE_APPSS,
711
+
MSM8996_SLAVE_SNOC_CNOC,
712
+
MSM8996_SLAVE_SNOC_PNOC,
713
+
MSM8996_SLAVE_OCIMEM,
714
+
MSM8996_SLAVE_QDSS_STM
715
+
};
716
+
717
+
static struct qcom_icc_node mas_bimc_snoc_0 = {
718
+
.name = "mas_bimc_snoc_0",
719
+
.id = MSM8996_MASTER_BIMC_SNOC_0,
720
+
.buswidth = 16,
721
+
.mas_rpm_id = 21,
722
+
.slv_rpm_id = -1,
723
+
.qos.ap_owned = true,
724
+
.qos.qos_mode = NOC_QOS_MODE_INVALID,
725
+
.num_links = ARRAY_SIZE(mas_bimc_snoc_0_links),
726
+
.links = mas_bimc_snoc_0_links
727
+
};
728
+
729
+
static const u16 mas_bimc_snoc_1_links[] = {
730
+
MSM8996_SLAVE_PCIE_2,
731
+
MSM8996_SLAVE_PCIE_1,
732
+
MSM8996_SLAVE_PCIE_0
733
+
};
734
+
735
+
static struct qcom_icc_node mas_bimc_snoc_1 = {
736
+
.name = "mas_bimc_snoc_1",
737
+
.id = MSM8996_MASTER_BIMC_SNOC_1,
738
+
.buswidth = 16,
739
+
.mas_rpm_id = 109,
740
+
.slv_rpm_id = -1,
741
+
.qos.ap_owned = true,
742
+
.qos.qos_mode = NOC_QOS_MODE_INVALID,
743
+
.num_links = ARRAY_SIZE(mas_bimc_snoc_1_links),
744
+
.links = mas_bimc_snoc_1_links
745
+
};
746
+
747
+
static const u16 mas_a0noc_snoc_links[] = {
748
+
MSM8996_SLAVE_SNOC_PNOC,
749
+
MSM8996_SLAVE_OCIMEM,
750
+
MSM8996_SLAVE_APPSS,
751
+
MSM8996_SLAVE_SNOC_BIMC,
752
+
MSM8996_SLAVE_PIMEM
753
+
};
754
+
755
+
static struct qcom_icc_node mas_a0noc_snoc = {
756
+
.name = "mas_a0noc_snoc",
757
+
.id = MSM8996_MASTER_A0NOC_SNOC,
758
+
.buswidth = 16,
759
+
.mas_rpm_id = 110,
760
+
.slv_rpm_id = -1,
761
+
.qos.ap_owned = true,
762
+
.qos.qos_mode = NOC_QOS_MODE_INVALID,
763
+
.num_links = ARRAY_SIZE(mas_a0noc_snoc_links),
764
+
.links = mas_a0noc_snoc_links
765
+
};
766
+
767
+
static const u16 mas_a1noc_snoc_links[] = {
768
+
MSM8996_SLAVE_SNOC_VMEM,
769
+
MSM8996_SLAVE_USB3,
770
+
MSM8996_SLAVE_PCIE_0,
771
+
MSM8996_SLAVE_PIMEM,
772
+
MSM8996_SLAVE_PCIE_2,
773
+
MSM8996_SLAVE_LPASS,
774
+
MSM8996_SLAVE_PCIE_1,
775
+
MSM8996_SLAVE_APPSS,
776
+
MSM8996_SLAVE_SNOC_BIMC,
777
+
MSM8996_SLAVE_SNOC_CNOC,
778
+
MSM8996_SLAVE_SNOC_PNOC,
779
+
MSM8996_SLAVE_OCIMEM,
780
+
MSM8996_SLAVE_QDSS_STM
781
+
};
782
+
783
+
static struct qcom_icc_node mas_a1noc_snoc = {
784
+
.name = "mas_a1noc_snoc",
785
+
.id = MSM8996_MASTER_A1NOC_SNOC,
786
+
.buswidth = 16,
787
+
.mas_rpm_id = 111,
788
+
.slv_rpm_id = -1,
789
+
.num_links = ARRAY_SIZE(mas_a1noc_snoc_links),
790
+
.links = mas_a1noc_snoc_links
791
+
};
792
+
793
+
static const u16 mas_a2noc_snoc_links[] = {
794
+
MSM8996_SLAVE_SNOC_VMEM,
795
+
MSM8996_SLAVE_USB3,
796
+
MSM8996_SLAVE_PCIE_1,
797
+
MSM8996_SLAVE_PIMEM,
798
+
MSM8996_SLAVE_PCIE_2,
799
+
MSM8996_SLAVE_QDSS_STM,
800
+
MSM8996_SLAVE_LPASS,
801
+
MSM8996_SLAVE_SNOC_BIMC,
802
+
MSM8996_SLAVE_SNOC_CNOC,
803
+
MSM8996_SLAVE_SNOC_PNOC,
804
+
MSM8996_SLAVE_OCIMEM,
805
+
MSM8996_SLAVE_PCIE_0
806
+
};
807
+
808
+
static struct qcom_icc_node mas_a2noc_snoc = {
809
+
.name = "mas_a2noc_snoc",
810
+
.id = MSM8996_MASTER_A2NOC_SNOC,
811
+
.buswidth = 16,
812
+
.mas_rpm_id = 112,
813
+
.slv_rpm_id = -1,
814
+
.num_links = ARRAY_SIZE(mas_a2noc_snoc_links),
815
+
.links = mas_a2noc_snoc_links
816
+
};
817
+
818
+
static struct qcom_icc_node mas_qdss_etr = {
819
+
.name = "mas_qdss_etr",
820
+
.id = MSM8996_MASTER_QDSS_ETR,
821
+
.buswidth = 16,
822
+
.mas_rpm_id = 31,
823
+
.slv_rpm_id = -1,
824
+
.qos.ap_owned = true,
825
+
.qos.qos_mode = NOC_QOS_MODE_FIXED,
826
+
.qos.areq_prio = 1,
827
+
.qos.prio_level = 1,
828
+
.qos.qos_port = 3,
829
+
.num_links = ARRAY_SIZE(mas_qdss_common_links),
830
+
.links = mas_qdss_common_links
831
+
};
832
+
833
+
static const u16 slv_a0noc_snoc_links[] = {
834
+
MSM8996_MASTER_A0NOC_SNOC
835
+
};
836
+
837
+
static struct qcom_icc_node slv_a0noc_snoc = {
838
+
.name = "slv_a0noc_snoc",
839
+
.id = MSM8996_SLAVE_A0NOC_SNOC,
840
+
.buswidth = 8,
841
+
.mas_rpm_id = -1,
842
+
.slv_rpm_id = 141,
843
+
.qos.ap_owned = true,
844
+
.qos.qos_mode = NOC_QOS_MODE_INVALID,
845
+
.num_links = ARRAY_SIZE(slv_a0noc_snoc_links),
846
+
.links = slv_a0noc_snoc_links
847
+
};
848
+
849
+
static const u16 slv_a1noc_snoc_links[] = {
850
+
MSM8996_MASTER_A1NOC_SNOC
851
+
};
852
+
853
+
static struct qcom_icc_node slv_a1noc_snoc = {
854
+
.name = "slv_a1noc_snoc",
855
+
.id = MSM8996_SLAVE_A1NOC_SNOC,
856
+
.buswidth = 8,
857
+
.mas_rpm_id = -1,
858
+
.slv_rpm_id = 142,
859
+
.num_links = ARRAY_SIZE(slv_a1noc_snoc_links),
860
+
.links = slv_a1noc_snoc_links
861
+
};
862
+
863
+
static const u16 slv_a2noc_snoc_links[] = {
864
+
MSM8996_MASTER_A2NOC_SNOC
865
+
};
866
+
867
+
static struct qcom_icc_node slv_a2noc_snoc = {
868
+
.name = "slv_a2noc_snoc",
869
+
.id = MSM8996_SLAVE_A2NOC_SNOC,
870
+
.buswidth = 8,
871
+
.mas_rpm_id = -1,
872
+
.slv_rpm_id = 143,
873
+
.num_links = ARRAY_SIZE(slv_a2noc_snoc_links),
874
+
.links = slv_a2noc_snoc_links
875
+
};
876
+
877
+
static struct qcom_icc_node slv_ebi = {
878
+
.name = "slv_ebi",
879
+
.id = MSM8996_SLAVE_EBI_CH0,
880
+
.buswidth = 8,
881
+
.mas_rpm_id = -1,
882
+
.slv_rpm_id = 0
883
+
};
884
+
885
+
static struct qcom_icc_node slv_hmss_l3 = {
886
+
.name = "slv_hmss_l3",
887
+
.id = MSM8996_SLAVE_HMSS_L3,
888
+
.buswidth = 8,
889
+
.mas_rpm_id = -1,
890
+
.slv_rpm_id = 160
891
+
};
892
+
893
+
static const u16 slv_bimc_snoc_0_links[] = {
894
+
MSM8996_MASTER_BIMC_SNOC_0
895
+
};
896
+
897
+
static struct qcom_icc_node slv_bimc_snoc_0 = {
898
+
.name = "slv_bimc_snoc_0",
899
+
.id = MSM8996_SLAVE_BIMC_SNOC_0,
900
+
.buswidth = 8,
901
+
.mas_rpm_id = -1,
902
+
.slv_rpm_id = 2,
903
+
.qos.ap_owned = true,
904
+
.qos.qos_mode = NOC_QOS_MODE_INVALID,
905
+
.num_links = ARRAY_SIZE(slv_bimc_snoc_0_links),
906
+
.links = slv_bimc_snoc_0_links
907
+
};
908
+
909
+
static const u16 slv_bimc_snoc_1_links[] = {
910
+
MSM8996_MASTER_BIMC_SNOC_1
911
+
};
912
+
913
+
static struct qcom_icc_node slv_bimc_snoc_1 = {
914
+
.name = "slv_bimc_snoc_1",
915
+
.id = MSM8996_SLAVE_BIMC_SNOC_1,
916
+
.buswidth = 8,
917
+
.mas_rpm_id = -1,
918
+
.slv_rpm_id = 138,
919
+
.qos.ap_owned = true,
920
+
.qos.qos_mode = NOC_QOS_MODE_INVALID,
921
+
.num_links = ARRAY_SIZE(slv_bimc_snoc_1_links),
922
+
.links = slv_bimc_snoc_1_links
923
+
};
924
+
925
+
static const u16 slv_cnoc_a1noc_links[] = {
926
+
MSM8996_MASTER_CNOC_A1NOC
927
+
};
928
+
929
+
static struct qcom_icc_node slv_cnoc_a1noc = {
930
+
.name = "slv_cnoc_a1noc",
931
+
.id = MSM8996_SLAVE_CNOC_A1NOC,
932
+
.buswidth = 4,
933
+
.mas_rpm_id = -1,
934
+
.slv_rpm_id = 75,
935
+
.qos.ap_owned = true,
936
+
.qos.qos_mode = NOC_QOS_MODE_INVALID,
937
+
.num_links = ARRAY_SIZE(slv_cnoc_a1noc_links),
938
+
.links = slv_cnoc_a1noc_links
939
+
};
940
+
941
+
static struct qcom_icc_node slv_clk_ctl = {
942
+
.name = "slv_clk_ctl",
943
+
.id = MSM8996_SLAVE_CLK_CTL,
944
+
.buswidth = 4,
945
+
.mas_rpm_id = -1,
946
+
.slv_rpm_id = 47
947
+
};
948
+
949
+
static struct qcom_icc_node slv_tcsr = {
950
+
.name = "slv_tcsr",
951
+
.id = MSM8996_SLAVE_TCSR,
952
+
.buswidth = 4,
953
+
.mas_rpm_id = -1,
954
+
.slv_rpm_id = 50
955
+
};
956
+
957
+
static struct qcom_icc_node slv_tlmm = {
958
+
.name = "slv_tlmm",
959
+
.id = MSM8996_SLAVE_TLMM,
960
+
.buswidth = 4,
961
+
.mas_rpm_id = -1,
962
+
.slv_rpm_id = 51
963
+
};
964
+
965
+
static struct qcom_icc_node slv_crypto0_cfg = {
966
+
.name = "slv_crypto0_cfg",
967
+
.id = MSM8996_SLAVE_CRYPTO_0_CFG,
968
+
.buswidth = 4,
969
+
.mas_rpm_id = -1,
970
+
.slv_rpm_id = 52,
971
+
.qos.ap_owned = true,
972
+
.qos.qos_mode = NOC_QOS_MODE_INVALID
973
+
};
974
+
975
+
static struct qcom_icc_node slv_mpm = {
976
+
.name = "slv_mpm",
977
+
.id = MSM8996_SLAVE_MPM,
978
+
.buswidth = 4,
979
+
.mas_rpm_id = -1,
980
+
.slv_rpm_id = 62,
981
+
.qos.ap_owned = true,
982
+
.qos.qos_mode = NOC_QOS_MODE_INVALID
983
+
};
984
+
985
+
static struct qcom_icc_node slv_pimem_cfg = {
986
+
.name = "slv_pimem_cfg",
987
+
.id = MSM8996_SLAVE_PIMEM_CFG,
988
+
.buswidth = 4,
989
+
.mas_rpm_id = -1,
990
+
.slv_rpm_id = 167,
991
+
.qos.ap_owned = true,
992
+
.qos.qos_mode = NOC_QOS_MODE_INVALID
993
+
};
994
+
995
+
static struct qcom_icc_node slv_imem_cfg = {
996
+
.name = "slv_imem_cfg",
997
+
.id = MSM8996_SLAVE_IMEM_CFG,
998
+
.buswidth = 4,
999
+
.mas_rpm_id = -1,
1000
+
.slv_rpm_id = 54,
1001
+
.qos.ap_owned = true,
1002
+
.qos.qos_mode = NOC_QOS_MODE_INVALID
1003
+
};
1004
+
1005
+
static struct qcom_icc_node slv_message_ram = {
1006
+
.name = "slv_message_ram",
1007
+
.id = MSM8996_SLAVE_MESSAGE_RAM,
1008
+
.buswidth = 4,
1009
+
.mas_rpm_id = -1,
1010
+
.slv_rpm_id = 55
1011
+
};
1012
+
1013
+
static struct qcom_icc_node slv_bimc_cfg = {
1014
+
.name = "slv_bimc_cfg",
1015
+
.id = MSM8996_SLAVE_BIMC_CFG,
1016
+
.buswidth = 4,
1017
+
.mas_rpm_id = -1,
1018
+
.slv_rpm_id = 56,
1019
+
.qos.ap_owned = true,
1020
+
.qos.qos_mode = NOC_QOS_MODE_INVALID
1021
+
};
1022
+
1023
+
static struct qcom_icc_node slv_pmic_arb = {
1024
+
.name = "slv_pmic_arb",
1025
+
.id = MSM8996_SLAVE_PMIC_ARB,
1026
+
.buswidth = 4,
1027
+
.mas_rpm_id = -1,
1028
+
.slv_rpm_id = 59
1029
+
};
1030
+
1031
+
static struct qcom_icc_node slv_prng = {
1032
+
.name = "slv_prng",
1033
+
.id = MSM8996_SLAVE_PRNG,
1034
+
.buswidth = 4,
1035
+
.mas_rpm_id = -1,
1036
+
.slv_rpm_id = 127,
1037
+
.qos.ap_owned = true,
1038
+
.qos.qos_mode = NOC_QOS_MODE_INVALID
1039
+
};
1040
+
1041
+
static struct qcom_icc_node slv_dcc_cfg = {
1042
+
.name = "slv_dcc_cfg",
1043
+
.id = MSM8996_SLAVE_DCC_CFG,
1044
+
.buswidth = 4,
1045
+
.mas_rpm_id = -1,
1046
+
.slv_rpm_id = 155,
1047
+
.qos.ap_owned = true,
1048
+
.qos.qos_mode = NOC_QOS_MODE_INVALID
1049
+
};
1050
+
1051
+
static struct qcom_icc_node slv_rbcpr_mx = {
1052
+
.name = "slv_rbcpr_mx",
1053
+
.id = MSM8996_SLAVE_RBCPR_MX,
1054
+
.buswidth = 4,
1055
+
.mas_rpm_id = -1,
1056
+
.slv_rpm_id = 170,
1057
+
.qos.ap_owned = true,
1058
+
.qos.qos_mode = NOC_QOS_MODE_INVALID
1059
+
};
1060
+
1061
+
static struct qcom_icc_node slv_qdss_cfg = {
1062
+
.name = "slv_qdss_cfg",
1063
+
.id = MSM8996_SLAVE_QDSS_CFG,
1064
+
.buswidth = 4,
1065
+
.mas_rpm_id = -1,
1066
+
.slv_rpm_id = 63,
1067
+
.qos.ap_owned = true,
1068
+
.qos.qos_mode = NOC_QOS_MODE_INVALID
1069
+
};
1070
+
1071
+
static struct qcom_icc_node slv_rbcpr_cx = {
1072
+
.name = "slv_rbcpr_cx",
1073
+
.id = MSM8996_SLAVE_RBCPR_CX,
1074
+
.buswidth = 4,
1075
+
.mas_rpm_id = -1,
1076
+
.slv_rpm_id = 169,
1077
+
.qos.ap_owned = true,
1078
+
.qos.qos_mode = NOC_QOS_MODE_INVALID
1079
+
};
1080
+
1081
+
static struct qcom_icc_node slv_cpu_apu_cfg = {
1082
+
.name = "slv_cpu_apu_cfg",
1083
+
.id = MSM8996_SLAVE_QDSS_RBCPR_APU_CFG,
1084
+
.buswidth = 4,
1085
+
.mas_rpm_id = -1,
1086
+
.slv_rpm_id = 168,
1087
+
.qos.ap_owned = true,
1088
+
.qos.qos_mode = NOC_QOS_MODE_INVALID
1089
+
};
1090
+
1091
+
static const u16 slv_cnoc_mnoc_cfg_links[] = {
1092
+
MSM8996_MASTER_CNOC_MNOC_CFG
1093
+
};
1094
+
1095
+
static struct qcom_icc_node slv_cnoc_mnoc_cfg = {
1096
+
.name = "slv_cnoc_mnoc_cfg",
1097
+
.id = MSM8996_SLAVE_CNOC_MNOC_CFG,
1098
+
.buswidth = 4,
1099
+
.mas_rpm_id = -1,
1100
+
.slv_rpm_id = 66,
1101
+
.qos.ap_owned = true,
1102
+
.qos.qos_mode = NOC_QOS_MODE_INVALID,
1103
+
.num_links = ARRAY_SIZE(slv_cnoc_mnoc_cfg_links),
1104
+
.links = slv_cnoc_mnoc_cfg_links
1105
+
};
1106
+
1107
+
static struct qcom_icc_node slv_snoc_cfg = {
1108
+
.name = "slv_snoc_cfg",
1109
+
.id = MSM8996_SLAVE_SNOC_CFG,
1110
+
.buswidth = 4,
1111
+
.mas_rpm_id = -1,
1112
+
.slv_rpm_id = 70,
1113
+
.qos.ap_owned = true,
1114
+
.qos.qos_mode = NOC_QOS_MODE_INVALID
1115
+
};
1116
+
1117
+
static struct qcom_icc_node slv_snoc_mpu_cfg = {
1118
+
.name = "slv_snoc_mpu_cfg",
1119
+
.id = MSM8996_SLAVE_SNOC_MPU_CFG,
1120
+
.buswidth = 4,
1121
+
.mas_rpm_id = -1,
1122
+
.slv_rpm_id = 67,
1123
+
.qos.ap_owned = true,
1124
+
.qos.qos_mode = NOC_QOS_MODE_INVALID
1125
+
};
1126
+
1127
+
static struct qcom_icc_node slv_ebi1_phy_cfg = {
1128
+
.name = "slv_ebi1_phy_cfg",
1129
+
.id = MSM8996_SLAVE_EBI1_PHY_CFG,
1130
+
.buswidth = 4,
1131
+
.mas_rpm_id = -1,
1132
+
.slv_rpm_id = 73,
1133
+
.qos.ap_owned = true,
1134
+
.qos.qos_mode = NOC_QOS_MODE_INVALID
1135
+
};
1136
+
1137
+
static struct qcom_icc_node slv_a0noc_cfg = {
1138
+
.name = "slv_a0noc_cfg",
1139
+
.id = MSM8996_SLAVE_A0NOC_CFG,
1140
+
.buswidth = 4,
1141
+
.mas_rpm_id = -1,
1142
+
.slv_rpm_id = 144,
1143
+
.qos.ap_owned = true,
1144
+
.qos.qos_mode = NOC_QOS_MODE_INVALID
1145
+
};
1146
+
1147
+
static struct qcom_icc_node slv_pcie_1_cfg = {
1148
+
.name = "slv_pcie_1_cfg",
1149
+
.id = MSM8996_SLAVE_PCIE_1_CFG,
1150
+
.buswidth = 4,
1151
+
.mas_rpm_id = -1,
1152
+
.slv_rpm_id = 89,
1153
+
.qos.ap_owned = true,
1154
+
.qos.qos_mode = NOC_QOS_MODE_INVALID
1155
+
};
1156
+
1157
+
static struct qcom_icc_node slv_pcie_2_cfg = {
1158
+
.name = "slv_pcie_2_cfg",
1159
+
.id = MSM8996_SLAVE_PCIE_2_CFG,
1160
+
.buswidth = 4,
1161
+
.mas_rpm_id = -1,
1162
+
.slv_rpm_id = 165,
1163
+
.qos.ap_owned = true,
1164
+
.qos.qos_mode = NOC_QOS_MODE_INVALID
1165
+
};
1166
+
1167
+
static struct qcom_icc_node slv_pcie_0_cfg = {
1168
+
.name = "slv_pcie_0_cfg",
1169
+
.id = MSM8996_SLAVE_PCIE_0_CFG,
1170
+
.buswidth = 4,
1171
+
.mas_rpm_id = -1,
1172
+
.slv_rpm_id = 88,
1173
+
.qos.ap_owned = true,
1174
+
.qos.qos_mode = NOC_QOS_MODE_INVALID
1175
+
};
1176
+
1177
+
static struct qcom_icc_node slv_pcie20_ahb2phy = {
1178
+
.name = "slv_pcie20_ahb2phy",
1179
+
.id = MSM8996_SLAVE_PCIE20_AHB2PHY,
1180
+
.buswidth = 4,
1181
+
.mas_rpm_id = -1,
1182
+
.slv_rpm_id = 163,
1183
+
.qos.ap_owned = true,
1184
+
.qos.qos_mode = NOC_QOS_MODE_INVALID
1185
+
};
1186
+
1187
+
static struct qcom_icc_node slv_a0noc_mpu_cfg = {
1188
+
.name = "slv_a0noc_mpu_cfg",
1189
+
.id = MSM8996_SLAVE_A0NOC_MPU_CFG,
1190
+
.buswidth = 4,
1191
+
.mas_rpm_id = -1,
1192
+
.slv_rpm_id = 145,
1193
+
.qos.ap_owned = true,
1194
+
.qos.qos_mode = NOC_QOS_MODE_INVALID
1195
+
};
1196
+
1197
+
static struct qcom_icc_node slv_ufs_cfg = {
1198
+
.name = "slv_ufs_cfg",
1199
+
.id = MSM8996_SLAVE_UFS_CFG,
1200
+
.buswidth = 4,
1201
+
.mas_rpm_id = -1,
1202
+
.slv_rpm_id = 92,
1203
+
.qos.ap_owned = true,
1204
+
.qos.qos_mode = NOC_QOS_MODE_INVALID
1205
+
};
1206
+
1207
+
static struct qcom_icc_node slv_a1noc_cfg = {
1208
+
.name = "slv_a1noc_cfg",
1209
+
.id = MSM8996_SLAVE_A1NOC_CFG,
1210
+
.buswidth = 4,
1211
+
.mas_rpm_id = -1,
1212
+
.slv_rpm_id = 147,
1213
+
.qos.ap_owned = true,
1214
+
.qos.qos_mode = NOC_QOS_MODE_INVALID
1215
+
};
1216
+
1217
+
static struct qcom_icc_node slv_a1noc_mpu_cfg = {
1218
+
.name = "slv_a1noc_mpu_cfg",
1219
+
.id = MSM8996_SLAVE_A1NOC_MPU_CFG,
1220
+
.buswidth = 4,
1221
+
.mas_rpm_id = -1,
1222
+
.slv_rpm_id = 148,
1223
+
.qos.ap_owned = true,
1224
+
.qos.qos_mode = NOC_QOS_MODE_INVALID
1225
+
};
1226
+
1227
+
static struct qcom_icc_node slv_a2noc_cfg = {
1228
+
.name = "slv_a2noc_cfg",
1229
+
.id = MSM8996_SLAVE_A2NOC_CFG,
1230
+
.buswidth = 4,
1231
+
.mas_rpm_id = -1,
1232
+
.slv_rpm_id = 150,
1233
+
.qos.ap_owned = true,
1234
+
.qos.qos_mode = NOC_QOS_MODE_INVALID
1235
+
};
1236
+
1237
+
static struct qcom_icc_node slv_a2noc_mpu_cfg = {
1238
+
.name = "slv_a2noc_mpu_cfg",
1239
+
.id = MSM8996_SLAVE_A2NOC_MPU_CFG,
1240
+
.buswidth = 4,
1241
+
.mas_rpm_id = -1,
1242
+
.slv_rpm_id = 151,
1243
+
.qos.ap_owned = true,
1244
+
.qos.qos_mode = NOC_QOS_MODE_INVALID
1245
+
};
1246
+
1247
+
static struct qcom_icc_node slv_ssc_cfg = {
1248
+
.name = "slv_ssc_cfg",
1249
+
.id = MSM8996_SLAVE_SSC_CFG,
1250
+
.buswidth = 4,
1251
+
.mas_rpm_id = -1,
1252
+
.slv_rpm_id = 177,
1253
+
.qos.ap_owned = true,
1254
+
.qos.qos_mode = NOC_QOS_MODE_INVALID
1255
+
};
1256
+
1257
+
static struct qcom_icc_node slv_a0noc_smmu_cfg = {
1258
+
.name = "slv_a0noc_smmu_cfg",
1259
+
.id = MSM8996_SLAVE_A0NOC_SMMU_CFG,
1260
+
.buswidth = 8,
1261
+
.mas_rpm_id = -1,
1262
+
.slv_rpm_id = 146,
1263
+
.qos.ap_owned = true,
1264
+
.qos.qos_mode = NOC_QOS_MODE_INVALID
1265
+
};
1266
+
1267
+
static struct qcom_icc_node slv_a1noc_smmu_cfg = {
1268
+
.name = "slv_a1noc_smmu_cfg",
1269
+
.id = MSM8996_SLAVE_A1NOC_SMMU_CFG,
1270
+
.buswidth = 8,
1271
+
.mas_rpm_id = -1,
1272
+
.slv_rpm_id = 149,
1273
+
.qos.ap_owned = true,
1274
+
.qos.qos_mode = NOC_QOS_MODE_INVALID
1275
+
};
1276
+
1277
+
static struct qcom_icc_node slv_a2noc_smmu_cfg = {
1278
+
.name = "slv_a2noc_smmu_cfg",
1279
+
.id = MSM8996_SLAVE_A2NOC_SMMU_CFG,
1280
+
.buswidth = 8,
1281
+
.mas_rpm_id = -1,
1282
+
.slv_rpm_id = 152,
1283
+
.qos.ap_owned = true,
1284
+
.qos.qos_mode = NOC_QOS_MODE_INVALID
1285
+
};
1286
+
1287
+
static struct qcom_icc_node slv_lpass_smmu_cfg = {
1288
+
.name = "slv_lpass_smmu_cfg",
1289
+
.id = MSM8996_SLAVE_LPASS_SMMU_CFG,
1290
+
.buswidth = 8,
1291
+
.mas_rpm_id = -1,
1292
+
.slv_rpm_id = 161,
1293
+
.qos.ap_owned = true,
1294
+
.qos.qos_mode = NOC_QOS_MODE_INVALID
1295
+
};
1296
+
1297
+
static const u16 slv_cnoc_mnoc_mmss_cfg_links[] = {
1298
+
MSM8996_MASTER_CNOC_MNOC_MMSS_CFG
1299
+
};
1300
+
1301
+
static struct qcom_icc_node slv_cnoc_mnoc_mmss_cfg = {
1302
+
.name = "slv_cnoc_mnoc_mmss_cfg",
1303
+
.id = MSM8996_SLAVE_CNOC_MNOC_MMSS_CFG,
1304
+
.buswidth = 8,
1305
+
.mas_rpm_id = -1,
1306
+
.slv_rpm_id = 58,
1307
+
.qos.ap_owned = true,
1308
+
.qos.qos_mode = NOC_QOS_MODE_INVALID,
1309
+
.num_links = ARRAY_SIZE(slv_cnoc_mnoc_mmss_cfg_links),
1310
+
.links = slv_cnoc_mnoc_mmss_cfg_links
1311
+
};
1312
+
1313
+
static struct qcom_icc_node slv_mmagic_cfg = {
1314
+
.name = "slv_mmagic_cfg",
1315
+
.id = MSM8996_SLAVE_MMAGIC_CFG,
1316
+
.buswidth = 8,
1317
+
.mas_rpm_id = -1,
1318
+
.slv_rpm_id = 162,
1319
+
.qos.ap_owned = true,
1320
+
.qos.qos_mode = NOC_QOS_MODE_INVALID
1321
+
};
1322
+
1323
+
static struct qcom_icc_node slv_cpr_cfg = {
1324
+
.name = "slv_cpr_cfg",
1325
+
.id = MSM8996_SLAVE_CPR_CFG,
1326
+
.buswidth = 8,
1327
+
.mas_rpm_id = -1,
1328
+
.slv_rpm_id = 6,
1329
+
.qos.ap_owned = true,
1330
+
.qos.qos_mode = NOC_QOS_MODE_INVALID
1331
+
};
1332
+
1333
+
static struct qcom_icc_node slv_misc_cfg = {
1334
+
.name = "slv_misc_cfg",
1335
+
.id = MSM8996_SLAVE_MISC_CFG,
1336
+
.buswidth = 8,
1337
+
.mas_rpm_id = -1,
1338
+
.slv_rpm_id = 8,
1339
+
.qos.ap_owned = true,
1340
+
.qos.qos_mode = NOC_QOS_MODE_INVALID
1341
+
};
1342
+
1343
+
static struct qcom_icc_node slv_venus_throttle_cfg = {
1344
+
.name = "slv_venus_throttle_cfg",
1345
+
.id = MSM8996_SLAVE_VENUS_THROTTLE_CFG,
1346
+
.buswidth = 8,
1347
+
.mas_rpm_id = -1,
1348
+
.slv_rpm_id = 178,
1349
+
.qos.ap_owned = true,
1350
+
.qos.qos_mode = NOC_QOS_MODE_INVALID
1351
+
};
1352
+
1353
+
static struct qcom_icc_node slv_venus_cfg = {
1354
+
.name = "slv_venus_cfg",
1355
+
.id = MSM8996_SLAVE_VENUS_CFG,
1356
+
.buswidth = 8,
1357
+
.mas_rpm_id = -1,
1358
+
.slv_rpm_id = 10,
1359
+
.qos.ap_owned = true,
1360
+
.qos.qos_mode = NOC_QOS_MODE_INVALID
1361
+
};
1362
+
1363
+
static struct qcom_icc_node slv_vmem_cfg = {
1364
+
.name = "slv_vmem_cfg",
1365
+
.id = MSM8996_SLAVE_VMEM_CFG,
1366
+
.buswidth = 8,
1367
+
.mas_rpm_id = -1,
1368
+
.slv_rpm_id = 180,
1369
+
.qos.ap_owned = true,
1370
+
.qos.qos_mode = NOC_QOS_MODE_INVALID
1371
+
};
1372
+
1373
+
static struct qcom_icc_node slv_dsa_cfg = {
1374
+
.name = "slv_dsa_cfg",
1375
+
.id = MSM8996_SLAVE_DSA_CFG,
1376
+
.buswidth = 8,
1377
+
.mas_rpm_id = -1,
1378
+
.slv_rpm_id = 157,
1379
+
.qos.ap_owned = true,
1380
+
.qos.qos_mode = NOC_QOS_MODE_INVALID
1381
+
};
1382
+
1383
+
static struct qcom_icc_node slv_mnoc_clocks_cfg = {
1384
+
.name = "slv_mnoc_clocks_cfg",
1385
+
.id = MSM8996_SLAVE_MMSS_CLK_CFG,
1386
+
.buswidth = 8,
1387
+
.mas_rpm_id = -1,
1388
+
.slv_rpm_id = 12,
1389
+
.qos.ap_owned = true,
1390
+
.qos.qos_mode = NOC_QOS_MODE_INVALID
1391
+
};
1392
+
1393
+
static struct qcom_icc_node slv_dsa_mpu_cfg = {
1394
+
.name = "slv_dsa_mpu_cfg",
1395
+
.id = MSM8996_SLAVE_DSA_MPU_CFG,
1396
+
.buswidth = 8,
1397
+
.mas_rpm_id = -1,
1398
+
.slv_rpm_id = 158,
1399
+
.qos.ap_owned = true,
1400
+
.qos.qos_mode = NOC_QOS_MODE_INVALID
1401
+
};
1402
+
1403
+
static struct qcom_icc_node slv_mnoc_mpu_cfg = {
1404
+
.name = "slv_mnoc_mpu_cfg",
1405
+
.id = MSM8996_SLAVE_MNOC_MPU_CFG,
1406
+
.buswidth = 8,
1407
+
.mas_rpm_id = -1,
1408
+
.slv_rpm_id = 14,
1409
+
.qos.ap_owned = true,
1410
+
.qos.qos_mode = NOC_QOS_MODE_INVALID
1411
+
};
1412
+
1413
+
static struct qcom_icc_node slv_display_cfg = {
1414
+
.name = "slv_display_cfg",
1415
+
.id = MSM8996_SLAVE_DISPLAY_CFG,
1416
+
.buswidth = 8,
1417
+
.mas_rpm_id = -1,
1418
+
.slv_rpm_id = 4,
1419
+
.qos.ap_owned = true,
1420
+
.qos.qos_mode = NOC_QOS_MODE_INVALID
1421
+
};
1422
+
1423
+
static struct qcom_icc_node slv_display_throttle_cfg = {
1424
+
.name = "slv_display_throttle_cfg",
1425
+
.id = MSM8996_SLAVE_DISPLAY_THROTTLE_CFG,
1426
+
.buswidth = 8,
1427
+
.mas_rpm_id = -1,
1428
+
.slv_rpm_id = 156,
1429
+
.qos.ap_owned = true,
1430
+
.qos.qos_mode = NOC_QOS_MODE_INVALID
1431
+
};
1432
+
1433
+
static struct qcom_icc_node slv_camera_cfg = {
1434
+
.name = "slv_camera_cfg",
1435
+
.id = MSM8996_SLAVE_CAMERA_CFG,
1436
+
.buswidth = 8,
1437
+
.mas_rpm_id = -1,
1438
+
.slv_rpm_id = 3,
1439
+
.qos.ap_owned = true,
1440
+
.qos.qos_mode = NOC_QOS_MODE_INVALID
1441
+
};
1442
+
1443
+
static struct qcom_icc_node slv_camera_throttle_cfg = {
1444
+
.name = "slv_camera_throttle_cfg",
1445
+
.id = MSM8996_SLAVE_CAMERA_THROTTLE_CFG,
1446
+
.buswidth = 8,
1447
+
.mas_rpm_id = -1,
1448
+
.slv_rpm_id = 154,
1449
+
.qos.ap_owned = true,
1450
+
.qos.qos_mode = NOC_QOS_MODE_INVALID
1451
+
};
1452
+
1453
+
static struct qcom_icc_node slv_oxili_cfg = {
1454
+
.name = "slv_oxili_cfg",
1455
+
.id = MSM8996_SLAVE_GRAPHICS_3D_CFG,
1456
+
.buswidth = 8,
1457
+
.mas_rpm_id = -1,
1458
+
.slv_rpm_id = 11,
1459
+
.qos.ap_owned = true,
1460
+
.qos.qos_mode = NOC_QOS_MODE_INVALID
1461
+
};
1462
+
1463
+
static struct qcom_icc_node slv_smmu_mdp_cfg = {
1464
+
.name = "slv_smmu_mdp_cfg",
1465
+
.id = MSM8996_SLAVE_SMMU_MDP_CFG,
1466
+
.buswidth = 8,
1467
+
.mas_rpm_id = -1,
1468
+
.slv_rpm_id = 173,
1469
+
.qos.ap_owned = true,
1470
+
.qos.qos_mode = NOC_QOS_MODE_INVALID
1471
+
};
1472
+
1473
+
static struct qcom_icc_node slv_smmu_rot_cfg = {
1474
+
.name = "slv_smmu_rot_cfg",
1475
+
.id = MSM8996_SLAVE_SMMU_ROTATOR_CFG,
1476
+
.buswidth = 8,
1477
+
.mas_rpm_id = -1,
1478
+
.slv_rpm_id = 174,
1479
+
.qos.ap_owned = true,
1480
+
.qos.qos_mode = NOC_QOS_MODE_INVALID
1481
+
};
1482
+
1483
+
static struct qcom_icc_node slv_smmu_venus_cfg = {
1484
+
.name = "slv_smmu_venus_cfg",
1485
+
.id = MSM8996_SLAVE_SMMU_VENUS_CFG,
1486
+
.buswidth = 8,
1487
+
.mas_rpm_id = -1,
1488
+
.slv_rpm_id = 175,
1489
+
.qos.ap_owned = true,
1490
+
.qos.qos_mode = NOC_QOS_MODE_INVALID
1491
+
};
1492
+
1493
+
static struct qcom_icc_node slv_smmu_cpp_cfg = {
1494
+
.name = "slv_smmu_cpp_cfg",
1495
+
.id = MSM8996_SLAVE_SMMU_CPP_CFG,
1496
+
.buswidth = 8,
1497
+
.mas_rpm_id = -1,
1498
+
.slv_rpm_id = 171,
1499
+
.qos.ap_owned = true,
1500
+
.qos.qos_mode = NOC_QOS_MODE_INVALID
1501
+
};
1502
+
1503
+
static struct qcom_icc_node slv_smmu_jpeg_cfg = {
1504
+
.name = "slv_smmu_jpeg_cfg",
1505
+
.id = MSM8996_SLAVE_SMMU_JPEG_CFG,
1506
+
.buswidth = 8,
1507
+
.mas_rpm_id = -1,
1508
+
.slv_rpm_id = 172,
1509
+
.qos.ap_owned = true,
1510
+
.qos.qos_mode = NOC_QOS_MODE_INVALID
1511
+
};
1512
+
1513
+
static struct qcom_icc_node slv_smmu_vfe_cfg = {
1514
+
.name = "slv_smmu_vfe_cfg",
1515
+
.id = MSM8996_SLAVE_SMMU_VFE_CFG,
1516
+
.buswidth = 8,
1517
+
.mas_rpm_id = -1,
1518
+
.slv_rpm_id = 176,
1519
+
.qos.ap_owned = true,
1520
+
.qos.qos_mode = NOC_QOS_MODE_INVALID
1521
+
};
1522
+
1523
+
static const u16 slv_mnoc_bimc_links[] = {
1524
+
MSM8996_MASTER_MNOC_BIMC
1525
+
};
1526
+
1527
+
static struct qcom_icc_node slv_mnoc_bimc = {
1528
+
.name = "slv_mnoc_bimc",
1529
+
.id = MSM8996_SLAVE_MNOC_BIMC,
1530
+
.buswidth = 32,
1531
+
.mas_rpm_id = -1,
1532
+
.slv_rpm_id = 16,
1533
+
.qos.ap_owned = true,
1534
+
.qos.qos_mode = NOC_QOS_MODE_INVALID,
1535
+
.num_links = ARRAY_SIZE(slv_mnoc_bimc_links),
1536
+
.links = slv_mnoc_bimc_links
1537
+
};
1538
+
1539
+
static struct qcom_icc_node slv_vmem = {
1540
+
.name = "slv_vmem",
1541
+
.id = MSM8996_SLAVE_VMEM,
1542
+
.buswidth = 32,
1543
+
.mas_rpm_id = -1,
1544
+
.slv_rpm_id = 179,
1545
+
.qos.ap_owned = true,
1546
+
.qos.qos_mode = NOC_QOS_MODE_INVALID
1547
+
};
1548
+
1549
+
static struct qcom_icc_node slv_srvc_mnoc = {
1550
+
.name = "slv_srvc_mnoc",
1551
+
.id = MSM8996_SLAVE_SERVICE_MNOC,
1552
+
.buswidth = 8,
1553
+
.mas_rpm_id = -1,
1554
+
.slv_rpm_id = 17,
1555
+
.qos.ap_owned = true,
1556
+
.qos.qos_mode = NOC_QOS_MODE_INVALID
1557
+
};
1558
+
1559
+
static const u16 slv_pnoc_a1noc_links[] = {
1560
+
MSM8996_MASTER_PNOC_A1NOC
1561
+
};
1562
+
1563
+
static struct qcom_icc_node slv_pnoc_a1noc = {
1564
+
.name = "slv_pnoc_a1noc",
1565
+
.id = MSM8996_SLAVE_PNOC_A1NOC,
1566
+
.buswidth = 8,
1567
+
.mas_rpm_id = -1,
1568
+
.slv_rpm_id = 139,
1569
+
.num_links = ARRAY_SIZE(slv_pnoc_a1noc_links),
1570
+
.links = slv_pnoc_a1noc_links
1571
+
};
1572
+
1573
+
static struct qcom_icc_node slv_usb_hs = {
1574
+
.name = "slv_usb_hs",
1575
+
.id = MSM8996_SLAVE_USB_HS,
1576
+
.buswidth = 4,
1577
+
.mas_rpm_id = -1,
1578
+
.slv_rpm_id = 40
1579
+
};
1580
+
1581
+
static struct qcom_icc_node slv_sdcc_2 = {
1582
+
.name = "slv_sdcc_2",
1583
+
.id = MSM8996_SLAVE_SDCC_2,
1584
+
.buswidth = 4,
1585
+
.mas_rpm_id = -1,
1586
+
.slv_rpm_id = 33
1587
+
};
1588
+
1589
+
static struct qcom_icc_node slv_sdcc_4 = {
1590
+
.name = "slv_sdcc_4",
1591
+
.id = MSM8996_SLAVE_SDCC_4,
1592
+
.buswidth = 4,
1593
+
.mas_rpm_id = -1,
1594
+
.slv_rpm_id = 34
1595
+
};
1596
+
1597
+
static struct qcom_icc_node slv_tsif = {
1598
+
.name = "slv_tsif",
1599
+
.id = MSM8996_SLAVE_TSIF,
1600
+
.buswidth = 4,
1601
+
.mas_rpm_id = -1,
1602
+
.slv_rpm_id = 35
1603
+
};
1604
+
1605
+
static struct qcom_icc_node slv_blsp_2 = {
1606
+
.name = "slv_blsp_2",
1607
+
.id = MSM8996_SLAVE_BLSP_2,
1608
+
.buswidth = 4,
1609
+
.mas_rpm_id = -1,
1610
+
.slv_rpm_id = 37
1611
+
};
1612
+
1613
+
static struct qcom_icc_node slv_sdcc_1 = {
1614
+
.name = "slv_sdcc_1",
1615
+
.id = MSM8996_SLAVE_SDCC_1,
1616
+
.buswidth = 4,
1617
+
.mas_rpm_id = -1,
1618
+
.slv_rpm_id = 31
1619
+
};
1620
+
1621
+
static struct qcom_icc_node slv_blsp_1 = {
1622
+
.name = "slv_blsp_1",
1623
+
.id = MSM8996_SLAVE_BLSP_1,
1624
+
.buswidth = 4,
1625
+
.mas_rpm_id = -1,
1626
+
.slv_rpm_id = 39
1627
+
};
1628
+
1629
+
static struct qcom_icc_node slv_pdm = {
1630
+
.name = "slv_pdm",
1631
+
.id = MSM8996_SLAVE_PDM,
1632
+
.buswidth = 4,
1633
+
.mas_rpm_id = -1,
1634
+
.slv_rpm_id = 41
1635
+
};
1636
+
1637
+
static struct qcom_icc_node slv_ahb2phy = {
1638
+
.name = "slv_ahb2phy",
1639
+
.id = MSM8996_SLAVE_AHB2PHY,
1640
+
.buswidth = 4,
1641
+
.mas_rpm_id = -1,
1642
+
.slv_rpm_id = 153,
1643
+
.qos.ap_owned = true,
1644
+
.qos.qos_mode = NOC_QOS_MODE_INVALID
1645
+
};
1646
+
1647
+
static struct qcom_icc_node slv_hmss = {
1648
+
.name = "slv_hmss",
1649
+
.id = MSM8996_SLAVE_APPSS,
1650
+
.buswidth = 16,
1651
+
.mas_rpm_id = -1,
1652
+
.slv_rpm_id = 20,
1653
+
.qos.ap_owned = true,
1654
+
.qos.qos_mode = NOC_QOS_MODE_INVALID
1655
+
};
1656
+
1657
+
static struct qcom_icc_node slv_lpass = {
1658
+
.name = "slv_lpass",
1659
+
.id = MSM8996_SLAVE_LPASS,
1660
+
.buswidth = 16,
1661
+
.mas_rpm_id = -1,
1662
+
.slv_rpm_id = 21,
1663
+
.qos.ap_owned = true,
1664
+
.qos.qos_mode = NOC_QOS_MODE_INVALID
1665
+
};
1666
+
1667
+
static struct qcom_icc_node slv_usb3 = {
1668
+
.name = "slv_usb3",
1669
+
.id = MSM8996_SLAVE_USB3,
1670
+
.buswidth = 16,
1671
+
.mas_rpm_id = -1,
1672
+
.slv_rpm_id = 22,
1673
+
.qos.ap_owned = true,
1674
+
.qos.qos_mode = NOC_QOS_MODE_INVALID
1675
+
};
1676
+
1677
+
static const u16 slv_snoc_bimc_links[] = {
1678
+
MSM8996_MASTER_SNOC_BIMC
1679
+
};
1680
+
1681
+
static struct qcom_icc_node slv_snoc_bimc = {
1682
+
.name = "slv_snoc_bimc",
1683
+
.id = MSM8996_SLAVE_SNOC_BIMC,
1684
+
.buswidth = 32,
1685
+
.mas_rpm_id = -1,
1686
+
.slv_rpm_id = 24,
1687
+
.num_links = ARRAY_SIZE(slv_snoc_bimc_links),
1688
+
.links = slv_snoc_bimc_links
1689
+
};
1690
+
1691
+
static const u16 slv_snoc_cnoc_links[] = {
1692
+
MSM8996_MASTER_SNOC_CNOC
1693
+
};
1694
+
1695
+
static struct qcom_icc_node slv_snoc_cnoc = {
1696
+
.name = "slv_snoc_cnoc",
1697
+
.id = MSM8996_SLAVE_SNOC_CNOC,
1698
+
.buswidth = 16,
1699
+
.mas_rpm_id = -1,
1700
+
.slv_rpm_id = 25,
1701
+
.num_links = ARRAY_SIZE(slv_snoc_cnoc_links),
1702
+
.links = slv_snoc_cnoc_links
1703
+
};
1704
+
1705
+
static struct qcom_icc_node slv_imem = {
1706
+
.name = "slv_imem",
1707
+
.id = MSM8996_SLAVE_OCIMEM,
1708
+
.buswidth = 16,
1709
+
.mas_rpm_id = -1,
1710
+
.slv_rpm_id = 26
1711
+
};
1712
+
1713
+
static struct qcom_icc_node slv_pimem = {
1714
+
.name = "slv_pimem",
1715
+
.id = MSM8996_SLAVE_PIMEM,
1716
+
.buswidth = 16,
1717
+
.mas_rpm_id = -1,
1718
+
.slv_rpm_id = 166
1719
+
};
1720
+
1721
+
static const u16 slv_snoc_vmem_links[] = {
1722
+
MSM8996_MASTER_SNOC_VMEM
1723
+
};
1724
+
1725
+
static struct qcom_icc_node slv_snoc_vmem = {
1726
+
.name = "slv_snoc_vmem",
1727
+
.id = MSM8996_SLAVE_SNOC_VMEM,
1728
+
.buswidth = 16,
1729
+
.mas_rpm_id = -1,
1730
+
.slv_rpm_id = 140,
1731
+
.qos.ap_owned = true,
1732
+
.qos.qos_mode = NOC_QOS_MODE_INVALID,
1733
+
.num_links = ARRAY_SIZE(slv_snoc_vmem_links),
1734
+
.links = slv_snoc_vmem_links
1735
+
};
1736
+
1737
+
static const u16 slv_snoc_pnoc_links[] = {
1738
+
MSM8996_MASTER_SNOC_PNOC
1739
+
};
1740
+
1741
+
static struct qcom_icc_node slv_snoc_pnoc = {
1742
+
.name = "slv_snoc_pnoc",
1743
+
.id = MSM8996_SLAVE_SNOC_PNOC,
1744
+
.buswidth = 16,
1745
+
.mas_rpm_id = -1,
1746
+
.slv_rpm_id = 28,
1747
+
.num_links = ARRAY_SIZE(slv_snoc_pnoc_links),
1748
+
.links = slv_snoc_pnoc_links
1749
+
};
1750
+
1751
+
static struct qcom_icc_node slv_qdss_stm = {
1752
+
.name = "slv_qdss_stm",
1753
+
.id = MSM8996_SLAVE_QDSS_STM,
1754
+
.buswidth = 16,
1755
+
.mas_rpm_id = -1,
1756
+
.slv_rpm_id = 30
1757
+
};
1758
+
1759
+
static struct qcom_icc_node slv_pcie_0 = {
1760
+
.name = "slv_pcie_0",
1761
+
.id = MSM8996_SLAVE_PCIE_0,
1762
+
.buswidth = 16,
1763
+
.mas_rpm_id = -1,
1764
+
.slv_rpm_id = 84,
1765
+
.qos.ap_owned = true,
1766
+
.qos.qos_mode = NOC_QOS_MODE_INVALID
1767
+
};
1768
+
1769
+
static struct qcom_icc_node slv_pcie_1 = {
1770
+
.name = "slv_pcie_1",
1771
+
.id = MSM8996_SLAVE_PCIE_1,
1772
+
.buswidth = 16,
1773
+
.mas_rpm_id = -1,
1774
+
.slv_rpm_id = 85,
1775
+
.qos.ap_owned = true,
1776
+
.qos.qos_mode = NOC_QOS_MODE_INVALID
1777
+
};
1778
+
1779
+
static struct qcom_icc_node slv_pcie_2 = {
1780
+
.name = "slv_pcie_2",
1781
+
.id = MSM8996_SLAVE_PCIE_2,
1782
+
.buswidth = 16,
1783
+
.mas_rpm_id = -1,
1784
+
.slv_rpm_id = 164,
1785
+
.qos.ap_owned = true,
1786
+
.qos.qos_mode = NOC_QOS_MODE_INVALID
1787
+
};
1788
+
1789
+
static struct qcom_icc_node slv_srvc_snoc = {
1790
+
.name = "slv_srvc_snoc",
1791
+
.id = MSM8996_SLAVE_SERVICE_SNOC,
1792
+
.buswidth = 16,
1793
+
.mas_rpm_id = -1,
1794
+
.slv_rpm_id = 29,
1795
+
.qos.ap_owned = true,
1796
+
.qos.qos_mode = NOC_QOS_MODE_INVALID
1797
+
};
1798
+
1799
+
static struct qcom_icc_node *a0noc_nodes[] = {
1800
+
[MASTER_PCIE_0] = &mas_pcie_0,
1801
+
[MASTER_PCIE_1] = &mas_pcie_1,
1802
+
[MASTER_PCIE_2] = &mas_pcie_2
1803
+
};
1804
+
1805
+
static const struct regmap_config msm8996_a0noc_regmap_config = {
1806
+
.reg_bits = 32,
1807
+
.reg_stride = 4,
1808
+
.val_bits = 32,
1809
+
.max_register = 0x9000,
1810
+
.fast_io = true
1811
+
};
1812
+
1813
+
static const struct qcom_icc_desc msm8996_a0noc = {
1814
+
.nodes = a0noc_nodes,
1815
+
.num_nodes = ARRAY_SIZE(a0noc_nodes),
1816
+
.clocks = bus_a0noc_clocks,
1817
+
.num_clocks = ARRAY_SIZE(bus_a0noc_clocks),
1818
+
.has_bus_pd = true,
1819
+
.regmap_cfg = &msm8996_a0noc_regmap_config
1820
+
};
1821
+
1822
+
static struct qcom_icc_node *a1noc_nodes[] = {
1823
+
[MASTER_CNOC_A1NOC] = &mas_cnoc_a1noc,
1824
+
[MASTER_CRYPTO_CORE0] = &mas_crypto_c0,
1825
+
[MASTER_PNOC_A1NOC] = &mas_pnoc_a1noc
1826
+
};
1827
+
1828
+
static const struct regmap_config msm8996_a1noc_regmap_config = {
1829
+
.reg_bits = 32,
1830
+
.reg_stride = 4,
1831
+
.val_bits = 32,
1832
+
.max_register = 0x7000,
1833
+
.fast_io = true
1834
+
};
1835
+
1836
+
static const struct qcom_icc_desc msm8996_a1noc = {
1837
+
.nodes = a1noc_nodes,
1838
+
.num_nodes = ARRAY_SIZE(a1noc_nodes),
1839
+
.regmap_cfg = &msm8996_a1noc_regmap_config
1840
+
};
1841
+
1842
+
static struct qcom_icc_node *a2noc_nodes[] = {
1843
+
[MASTER_USB3] = &mas_usb3,
1844
+
[MASTER_IPA] = &mas_ipa,
1845
+
[MASTER_UFS] = &mas_ufs
1846
+
};
1847
+
1848
+
static const struct regmap_config msm8996_a2noc_regmap_config = {
1849
+
.reg_bits = 32,
1850
+
.reg_stride = 4,
1851
+
.val_bits = 32,
1852
+
.max_register = 0xa000,
1853
+
.fast_io = true
1854
+
};
1855
+
1856
+
static const struct qcom_icc_desc msm8996_a2noc = {
1857
+
.nodes = a2noc_nodes,
1858
+
.num_nodes = ARRAY_SIZE(a2noc_nodes),
1859
+
.regmap_cfg = &msm8996_a2noc_regmap_config
1860
+
};
1861
+
1862
+
static struct qcom_icc_node *bimc_nodes[] = {
1863
+
[MASTER_AMPSS_M0] = &mas_apps_proc,
1864
+
[MASTER_GRAPHICS_3D] = &mas_oxili,
1865
+
[MASTER_MNOC_BIMC] = &mas_mnoc_bimc,
1866
+
[MASTER_SNOC_BIMC] = &mas_snoc_bimc,
1867
+
[SLAVE_EBI_CH0] = &slv_ebi,
1868
+
[SLAVE_HMSS_L3] = &slv_hmss_l3,
1869
+
[SLAVE_BIMC_SNOC_0] = &slv_bimc_snoc_0,
1870
+
[SLAVE_BIMC_SNOC_1] = &slv_bimc_snoc_1
1871
+
};
1872
+
1873
+
static const struct regmap_config msm8996_bimc_regmap_config = {
1874
+
.reg_bits = 32,
1875
+
.reg_stride = 4,
1876
+
.val_bits = 32,
1877
+
.max_register = 0x62000,
1878
+
.fast_io = true
1879
+
};
1880
+
1881
+
static const struct qcom_icc_desc msm8996_bimc = {
1882
+
.nodes = bimc_nodes,
1883
+
.num_nodes = ARRAY_SIZE(bimc_nodes),
1884
+
.is_bimc_node = true,
1885
+
.regmap_cfg = &msm8996_bimc_regmap_config
1886
+
};
1887
+
1888
+
static struct qcom_icc_node *cnoc_nodes[] = {
1889
+
[MASTER_SNOC_CNOC] = &mas_snoc_cnoc,
1890
+
[MASTER_QDSS_DAP] = &mas_qdss_dap,
1891
+
[SLAVE_CNOC_A1NOC] = &slv_cnoc_a1noc,
1892
+
[SLAVE_CLK_CTL] = &slv_clk_ctl,
1893
+
[SLAVE_TCSR] = &slv_tcsr,
1894
+
[SLAVE_TLMM] = &slv_tlmm,
1895
+
[SLAVE_CRYPTO_0_CFG] = &slv_crypto0_cfg,
1896
+
[SLAVE_MPM] = &slv_mpm,
1897
+
[SLAVE_PIMEM_CFG] = &slv_pimem_cfg,
1898
+
[SLAVE_IMEM_CFG] = &slv_imem_cfg,
1899
+
[SLAVE_MESSAGE_RAM] = &slv_message_ram,
1900
+
[SLAVE_BIMC_CFG] = &slv_bimc_cfg,
1901
+
[SLAVE_PMIC_ARB] = &slv_pmic_arb,
1902
+
[SLAVE_PRNG] = &slv_prng,
1903
+
[SLAVE_DCC_CFG] = &slv_dcc_cfg,
1904
+
[SLAVE_RBCPR_MX] = &slv_rbcpr_mx,
1905
+
[SLAVE_QDSS_CFG] = &slv_qdss_cfg,
1906
+
[SLAVE_RBCPR_CX] = &slv_rbcpr_cx,
1907
+
[SLAVE_QDSS_RBCPR_APU] = &slv_cpu_apu_cfg,
1908
+
[SLAVE_CNOC_MNOC_CFG] = &slv_cnoc_mnoc_cfg,
1909
+
[SLAVE_SNOC_CFG] = &slv_snoc_cfg,
1910
+
[SLAVE_SNOC_MPU_CFG] = &slv_snoc_mpu_cfg,
1911
+
[SLAVE_EBI1_PHY_CFG] = &slv_ebi1_phy_cfg,
1912
+
[SLAVE_A0NOC_CFG] = &slv_a0noc_cfg,
1913
+
[SLAVE_PCIE_1_CFG] = &slv_pcie_1_cfg,
1914
+
[SLAVE_PCIE_2_CFG] = &slv_pcie_2_cfg,
1915
+
[SLAVE_PCIE_0_CFG] = &slv_pcie_0_cfg,
1916
+
[SLAVE_PCIE20_AHB2PHY] = &slv_pcie20_ahb2phy,
1917
+
[SLAVE_A0NOC_MPU_CFG] = &slv_a0noc_mpu_cfg,
1918
+
[SLAVE_UFS_CFG] = &slv_ufs_cfg,
1919
+
[SLAVE_A1NOC_CFG] = &slv_a1noc_cfg,
1920
+
[SLAVE_A1NOC_MPU_CFG] = &slv_a1noc_mpu_cfg,
1921
+
[SLAVE_A2NOC_CFG] = &slv_a2noc_cfg,
1922
+
[SLAVE_A2NOC_MPU_CFG] = &slv_a2noc_mpu_cfg,
1923
+
[SLAVE_SSC_CFG] = &slv_ssc_cfg,
1924
+
[SLAVE_A0NOC_SMMU_CFG] = &slv_a0noc_smmu_cfg,
1925
+
[SLAVE_A1NOC_SMMU_CFG] = &slv_a1noc_smmu_cfg,
1926
+
[SLAVE_A2NOC_SMMU_CFG] = &slv_a2noc_smmu_cfg,
1927
+
[SLAVE_LPASS_SMMU_CFG] = &slv_lpass_smmu_cfg,
1928
+
[SLAVE_CNOC_MNOC_MMSS_CFG] = &slv_cnoc_mnoc_mmss_cfg
1929
+
};
1930
+
1931
+
static const struct regmap_config msm8996_cnoc_regmap_config = {
1932
+
.reg_bits = 32,
1933
+
.reg_stride = 4,
1934
+
.val_bits = 32,
1935
+
.max_register = 0x1000,
1936
+
.fast_io = true
1937
+
};
1938
+
1939
+
static const struct qcom_icc_desc msm8996_cnoc = {
1940
+
.nodes = cnoc_nodes,
1941
+
.num_nodes = ARRAY_SIZE(cnoc_nodes),
1942
+
.regmap_cfg = &msm8996_cnoc_regmap_config
1943
+
};
1944
+
1945
+
static struct qcom_icc_node *mnoc_nodes[] = {
1946
+
[MASTER_CNOC_MNOC_CFG] = &mas_cnoc_mnoc_cfg,
1947
+
[MASTER_CPP] = &mas_cpp,
1948
+
[MASTER_JPEG] = &mas_jpeg,
1949
+
[MASTER_MDP_PORT0] = &mas_mdp_p0,
1950
+
[MASTER_MDP_PORT1] = &mas_mdp_p1,
1951
+
[MASTER_ROTATOR] = &mas_rotator,
1952
+
[MASTER_VIDEO_P0] = &mas_venus,
1953
+
[MASTER_VFE] = &mas_vfe,
1954
+
[MASTER_SNOC_VMEM] = &mas_snoc_vmem,
1955
+
[MASTER_VIDEO_P0_OCMEM] = &mas_venus_vmem,
1956
+
[MASTER_CNOC_MNOC_MMSS_CFG] = &mas_cnoc_mnoc_mmss_cfg,
1957
+
[SLAVE_MNOC_BIMC] = &slv_mnoc_bimc,
1958
+
[SLAVE_VMEM] = &slv_vmem,
1959
+
[SLAVE_SERVICE_MNOC] = &slv_srvc_mnoc,
1960
+
[SLAVE_MMAGIC_CFG] = &slv_mmagic_cfg,
1961
+
[SLAVE_CPR_CFG] = &slv_cpr_cfg,
1962
+
[SLAVE_MISC_CFG] = &slv_misc_cfg,
1963
+
[SLAVE_VENUS_THROTTLE_CFG] = &slv_venus_throttle_cfg,
1964
+
[SLAVE_VENUS_CFG] = &slv_venus_cfg,
1965
+
[SLAVE_VMEM_CFG] = &slv_vmem_cfg,
1966
+
[SLAVE_DSA_CFG] = &slv_dsa_cfg,
1967
+
[SLAVE_MMSS_CLK_CFG] = &slv_mnoc_clocks_cfg,
1968
+
[SLAVE_DSA_MPU_CFG] = &slv_dsa_mpu_cfg,
1969
+
[SLAVE_MNOC_MPU_CFG] = &slv_mnoc_mpu_cfg,
1970
+
[SLAVE_DISPLAY_CFG] = &slv_display_cfg,
1971
+
[SLAVE_DISPLAY_THROTTLE_CFG] = &slv_display_throttle_cfg,
1972
+
[SLAVE_CAMERA_CFG] = &slv_camera_cfg,
1973
+
[SLAVE_CAMERA_THROTTLE_CFG] = &slv_camera_throttle_cfg,
1974
+
[SLAVE_GRAPHICS_3D_CFG] = &slv_oxili_cfg,
1975
+
[SLAVE_SMMU_MDP_CFG] = &slv_smmu_mdp_cfg,
1976
+
[SLAVE_SMMU_ROT_CFG] = &slv_smmu_rot_cfg,
1977
+
[SLAVE_SMMU_VENUS_CFG] = &slv_smmu_venus_cfg,
1978
+
[SLAVE_SMMU_CPP_CFG] = &slv_smmu_cpp_cfg,
1979
+
[SLAVE_SMMU_JPEG_CFG] = &slv_smmu_jpeg_cfg,
1980
+
[SLAVE_SMMU_VFE_CFG] = &slv_smmu_vfe_cfg
1981
+
};
1982
+
1983
+
static const struct regmap_config msm8996_mnoc_regmap_config = {
1984
+
.reg_bits = 32,
1985
+
.reg_stride = 4,
1986
+
.val_bits = 32,
1987
+
.max_register = 0x20000,
1988
+
.fast_io = true
1989
+
};
1990
+
1991
+
static const struct qcom_icc_desc msm8996_mnoc = {
1992
+
.nodes = mnoc_nodes,
1993
+
.num_nodes = ARRAY_SIZE(mnoc_nodes),
1994
+
.clocks = bus_mm_clocks,
1995
+
.num_clocks = ARRAY_SIZE(bus_mm_clocks),
1996
+
.regmap_cfg = &msm8996_mnoc_regmap_config
1997
+
};
1998
+
1999
+
static struct qcom_icc_node *pnoc_nodes[] = {
2000
+
[MASTER_SNOC_PNOC] = &mas_snoc_pnoc,
2001
+
[MASTER_SDCC_1] = &mas_sdcc_1,
2002
+
[MASTER_SDCC_2] = &mas_sdcc_2,
2003
+
[MASTER_SDCC_4] = &mas_sdcc_4,
2004
+
[MASTER_USB_HS] = &mas_usb_hs,
2005
+
[MASTER_BLSP_1] = &mas_blsp_1,
2006
+
[MASTER_BLSP_2] = &mas_blsp_2,
2007
+
[MASTER_TSIF] = &mas_tsif,
2008
+
[SLAVE_PNOC_A1NOC] = &slv_pnoc_a1noc,
2009
+
[SLAVE_USB_HS] = &slv_usb_hs,
2010
+
[SLAVE_SDCC_2] = &slv_sdcc_2,
2011
+
[SLAVE_SDCC_4] = &slv_sdcc_4,
2012
+
[SLAVE_TSIF] = &slv_tsif,
2013
+
[SLAVE_BLSP_2] = &slv_blsp_2,
2014
+
[SLAVE_SDCC_1] = &slv_sdcc_1,
2015
+
[SLAVE_BLSP_1] = &slv_blsp_1,
2016
+
[SLAVE_PDM] = &slv_pdm,
2017
+
[SLAVE_AHB2PHY] = &slv_ahb2phy
2018
+
};
2019
+
2020
+
static const struct regmap_config msm8996_pnoc_regmap_config = {
2021
+
.reg_bits = 32,
2022
+
.reg_stride = 4,
2023
+
.val_bits = 32,
2024
+
.max_register = 0x3000,
2025
+
.fast_io = true
2026
+
};
2027
+
2028
+
static const struct qcom_icc_desc msm8996_pnoc = {
2029
+
.nodes = pnoc_nodes,
2030
+
.num_nodes = ARRAY_SIZE(pnoc_nodes),
2031
+
.regmap_cfg = &msm8996_pnoc_regmap_config
2032
+
};
2033
+
2034
+
static struct qcom_icc_node *snoc_nodes[] = {
2035
+
[MASTER_HMSS] = &mas_hmss,
2036
+
[MASTER_QDSS_BAM] = &mas_qdss_bam,
2037
+
[MASTER_SNOC_CFG] = &mas_snoc_cfg,
2038
+
[MASTER_BIMC_SNOC_0] = &mas_bimc_snoc_0,
2039
+
[MASTER_BIMC_SNOC_1] = &mas_bimc_snoc_1,
2040
+
[MASTER_A0NOC_SNOC] = &mas_a0noc_snoc,
2041
+
[MASTER_A1NOC_SNOC] = &mas_a1noc_snoc,
2042
+
[MASTER_A2NOC_SNOC] = &mas_a2noc_snoc,
2043
+
[MASTER_QDSS_ETR] = &mas_qdss_etr,
2044
+
[SLAVE_A0NOC_SNOC] = &slv_a0noc_snoc,
2045
+
[SLAVE_A1NOC_SNOC] = &slv_a1noc_snoc,
2046
+
[SLAVE_A2NOC_SNOC] = &slv_a2noc_snoc,
2047
+
[SLAVE_HMSS] = &slv_hmss,
2048
+
[SLAVE_LPASS] = &slv_lpass,
2049
+
[SLAVE_USB3] = &slv_usb3,
2050
+
[SLAVE_SNOC_BIMC] = &slv_snoc_bimc,
2051
+
[SLAVE_SNOC_CNOC] = &slv_snoc_cnoc,
2052
+
[SLAVE_IMEM] = &slv_imem,
2053
+
[SLAVE_PIMEM] = &slv_pimem,
2054
+
[SLAVE_SNOC_VMEM] = &slv_snoc_vmem,
2055
+
[SLAVE_SNOC_PNOC] = &slv_snoc_pnoc,
2056
+
[SLAVE_QDSS_STM] = &slv_qdss_stm,
2057
+
[SLAVE_PCIE_0] = &slv_pcie_0,
2058
+
[SLAVE_PCIE_1] = &slv_pcie_1,
2059
+
[SLAVE_PCIE_2] = &slv_pcie_2,
2060
+
[SLAVE_SERVICE_SNOC] = &slv_srvc_snoc
2061
+
};
2062
+
2063
+
static const struct regmap_config msm8996_snoc_regmap_config = {
2064
+
.reg_bits = 32,
2065
+
.reg_stride = 4,
2066
+
.val_bits = 32,
2067
+
.max_register = 0x20000,
2068
+
.fast_io = true
2069
+
};
2070
+
2071
+
static const struct qcom_icc_desc msm8996_snoc = {
2072
+
.nodes = snoc_nodes,
2073
+
.num_nodes = ARRAY_SIZE(snoc_nodes),
2074
+
.regmap_cfg = &msm8996_snoc_regmap_config
2075
+
};
2076
+
2077
+
static const struct of_device_id qnoc_of_match[] = {
2078
+
{ .compatible = "qcom,msm8996-a0noc", .data = &msm8996_a0noc},
2079
+
{ .compatible = "qcom,msm8996-a1noc", .data = &msm8996_a1noc},
2080
+
{ .compatible = "qcom,msm8996-a2noc", .data = &msm8996_a2noc},
2081
+
{ .compatible = "qcom,msm8996-bimc", .data = &msm8996_bimc},
2082
+
{ .compatible = "qcom,msm8996-cnoc", .data = &msm8996_cnoc},
2083
+
{ .compatible = "qcom,msm8996-mnoc", .data = &msm8996_mnoc},
2084
+
{ .compatible = "qcom,msm8996-pnoc", .data = &msm8996_pnoc},
2085
+
{ .compatible = "qcom,msm8996-snoc", .data = &msm8996_snoc},
2086
+
{ }
2087
+
};
2088
+
MODULE_DEVICE_TABLE(of, qnoc_of_match);
2089
+
2090
+
static struct platform_driver qnoc_driver = {
2091
+
.probe = qnoc_probe,
2092
+
.remove = qnoc_remove,
2093
+
.driver = {
2094
+
.name = "qnoc-msm8996",
2095
+
.of_match_table = qnoc_of_match,
2096
+
.sync_state = icc_sync_state,
2097
+
}
2098
+
};
2099
+
module_platform_driver(qnoc_driver);
2100
+
2101
+
MODULE_AUTHOR("Yassine Oudjana <y.oudjana@protonmail.com>");
2102
+
MODULE_DESCRIPTION("Qualcomm MSM8996 NoC driver");
2103
+
MODULE_LICENSE("GPL v2");
+149
drivers/interconnect/qcom/msm8996.h
+149
drivers/interconnect/qcom/msm8996.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0-only */
2
+
/*
3
+
* Qualcomm MSM8996 interconnect IDs
4
+
*
5
+
* Copyright (c) 2021 Yassine Oudjana <y.oudjana@protonmail.com>
6
+
*/
7
+
8
+
#ifndef __DRIVERS_INTERCONNECT_QCOM_MSM8996_H__
9
+
#define __DRIVERS_INTERCONNECT_QCOM_MSM8996_H__
10
+
11
+
#define MSM8996_MASTER_PCIE_0 1
12
+
#define MSM8996_MASTER_PCIE_1 2
13
+
#define MSM8996_MASTER_PCIE_2 3
14
+
#define MSM8996_MASTER_CNOC_A1NOC 4
15
+
#define MSM8996_MASTER_CRYPTO_CORE0 5
16
+
#define MSM8996_MASTER_PNOC_A1NOC 6
17
+
#define MSM8996_MASTER_USB3 7
18
+
#define MSM8996_MASTER_IPA 8
19
+
#define MSM8996_MASTER_UFS 9
20
+
#define MSM8996_MASTER_AMPSS_M0 10
21
+
#define MSM8996_MASTER_GRAPHICS_3D 11
22
+
#define MSM8996_MASTER_MNOC_BIMC 12
23
+
#define MSM8996_MASTER_SNOC_BIMC 13
24
+
#define MSM8996_MASTER_SNOC_CNOC 14
25
+
#define MSM8996_MASTER_QDSS_DAP 15
26
+
#define MSM8996_MASTER_CNOC_MNOC_MMSS_CFG 16
27
+
#define MSM8996_MASTER_CNOC_MNOC_CFG 17
28
+
#define MSM8996_MASTER_CPP 18
29
+
#define MSM8996_MASTER_JPEG 19
30
+
#define MSM8996_MASTER_MDP_PORT0 20
31
+
#define MSM8996_MASTER_MDP_PORT1 21
32
+
#define MSM8996_MASTER_ROTATOR 22
33
+
#define MSM8996_MASTER_VIDEO_P0 23
34
+
#define MSM8996_MASTER_VFE 24
35
+
#define MSM8996_MASTER_SNOC_VMEM 25
36
+
#define MSM8996_MASTER_VIDEO_P0_OCMEM 26
37
+
#define MSM8996_MASTER_SNOC_PNOC 27
38
+
#define MSM8996_MASTER_SDCC_1 28
39
+
#define MSM8996_MASTER_SDCC_2 29
40
+
#define MSM8996_MASTER_SDCC_4 30
41
+
#define MSM8996_MASTER_USB_HS 31
42
+
#define MSM8996_MASTER_BLSP_1 32
43
+
#define MSM8996_MASTER_BLSP_2 33
44
+
#define MSM8996_MASTER_TSIF 34
45
+
#define MSM8996_MASTER_HMSS 35
46
+
#define MSM8996_MASTER_QDSS_BAM 36
47
+
#define MSM8996_MASTER_SNOC_CFG 37
48
+
#define MSM8996_MASTER_BIMC_SNOC_0 38
49
+
#define MSM8996_MASTER_BIMC_SNOC_1 39
50
+
#define MSM8996_MASTER_A0NOC_SNOC 40
51
+
#define MSM8996_MASTER_A1NOC_SNOC 41
52
+
#define MSM8996_MASTER_A2NOC_SNOC 42
53
+
#define MSM8996_MASTER_QDSS_ETR 43
54
+
55
+
#define MSM8996_SLAVE_A0NOC_SNOC 44
56
+
#define MSM8996_SLAVE_A1NOC_SNOC 45
57
+
#define MSM8996_SLAVE_A2NOC_SNOC 46
58
+
#define MSM8996_SLAVE_EBI_CH0 47
59
+
#define MSM8996_SLAVE_HMSS_L3 48
60
+
#define MSM8996_SLAVE_BIMC_SNOC_0 49
61
+
#define MSM8996_SLAVE_BIMC_SNOC_1 50
62
+
#define MSM8996_SLAVE_CNOC_A1NOC 51
63
+
#define MSM8996_SLAVE_CLK_CTL 52
64
+
#define MSM8996_SLAVE_TCSR 53
65
+
#define MSM8996_SLAVE_TLMM 54
66
+
#define MSM8996_SLAVE_CRYPTO_0_CFG 55
67
+
#define MSM8996_SLAVE_MPM 56
68
+
#define MSM8996_SLAVE_PIMEM_CFG 57
69
+
#define MSM8996_SLAVE_IMEM_CFG 58
70
+
#define MSM8996_SLAVE_MESSAGE_RAM 59
71
+
#define MSM8996_SLAVE_BIMC_CFG 60
72
+
#define MSM8996_SLAVE_PMIC_ARB 61
73
+
#define MSM8996_SLAVE_PRNG 62
74
+
#define MSM8996_SLAVE_DCC_CFG 63
75
+
#define MSM8996_SLAVE_RBCPR_MX 64
76
+
#define MSM8996_SLAVE_QDSS_CFG 65
77
+
#define MSM8996_SLAVE_RBCPR_CX 66
78
+
#define MSM8996_SLAVE_QDSS_RBCPR_APU_CFG 67
79
+
#define MSM8996_SLAVE_CNOC_MNOC_CFG 68
80
+
#define MSM8996_SLAVE_SNOC_CFG 69
81
+
#define MSM8996_SLAVE_SNOC_MPU_CFG 70
82
+
#define MSM8996_SLAVE_EBI1_PHY_CFG 71
83
+
#define MSM8996_SLAVE_A0NOC_CFG 72
84
+
#define MSM8996_SLAVE_PCIE_1_CFG 73
85
+
#define MSM8996_SLAVE_PCIE_2_CFG 74
86
+
#define MSM8996_SLAVE_PCIE_0_CFG 75
87
+
#define MSM8996_SLAVE_PCIE20_AHB2PHY 76
88
+
#define MSM8996_SLAVE_A0NOC_MPU_CFG 77
89
+
#define MSM8996_SLAVE_UFS_CFG 78
90
+
#define MSM8996_SLAVE_A1NOC_CFG 79
91
+
#define MSM8996_SLAVE_A1NOC_MPU_CFG 80
92
+
#define MSM8996_SLAVE_A2NOC_CFG 81
93
+
#define MSM8996_SLAVE_A2NOC_MPU_CFG 82
94
+
#define MSM8996_SLAVE_SSC_CFG 83
95
+
#define MSM8996_SLAVE_A0NOC_SMMU_CFG 84
96
+
#define MSM8996_SLAVE_A1NOC_SMMU_CFG 85
97
+
#define MSM8996_SLAVE_A2NOC_SMMU_CFG 86
98
+
#define MSM8996_SLAVE_LPASS_SMMU_CFG 87
99
+
#define MSM8996_SLAVE_CNOC_MNOC_MMSS_CFG 88
100
+
#define MSM8996_SLAVE_MMAGIC_CFG 89
101
+
#define MSM8996_SLAVE_CPR_CFG 90
102
+
#define MSM8996_SLAVE_MISC_CFG 91
103
+
#define MSM8996_SLAVE_VENUS_THROTTLE_CFG 92
104
+
#define MSM8996_SLAVE_VENUS_CFG 93
105
+
#define MSM8996_SLAVE_VMEM_CFG 94
106
+
#define MSM8996_SLAVE_DSA_CFG 95
107
+
#define MSM8996_SLAVE_MMSS_CLK_CFG 96
108
+
#define MSM8996_SLAVE_DSA_MPU_CFG 97
109
+
#define MSM8996_SLAVE_MNOC_MPU_CFG 98
110
+
#define MSM8996_SLAVE_DISPLAY_CFG 99
111
+
#define MSM8996_SLAVE_DISPLAY_THROTTLE_CFG 100
112
+
#define MSM8996_SLAVE_CAMERA_CFG 101
113
+
#define MSM8996_SLAVE_CAMERA_THROTTLE_CFG 102
114
+
#define MSM8996_SLAVE_GRAPHICS_3D_CFG 103
115
+
#define MSM8996_SLAVE_SMMU_MDP_CFG 104
116
+
#define MSM8996_SLAVE_SMMU_ROTATOR_CFG 105
117
+
#define MSM8996_SLAVE_SMMU_VENUS_CFG 106
118
+
#define MSM8996_SLAVE_SMMU_CPP_CFG 107
119
+
#define MSM8996_SLAVE_SMMU_JPEG_CFG 108
120
+
#define MSM8996_SLAVE_SMMU_VFE_CFG 109
121
+
#define MSM8996_SLAVE_MNOC_BIMC 110
122
+
#define MSM8996_SLAVE_VMEM 111
123
+
#define MSM8996_SLAVE_SERVICE_MNOC 112
124
+
#define MSM8996_SLAVE_PNOC_A1NOC 113
125
+
#define MSM8996_SLAVE_USB_HS 114
126
+
#define MSM8996_SLAVE_SDCC_2 115
127
+
#define MSM8996_SLAVE_SDCC_4 116
128
+
#define MSM8996_SLAVE_TSIF 117
129
+
#define MSM8996_SLAVE_BLSP_2 118
130
+
#define MSM8996_SLAVE_SDCC_1 119
131
+
#define MSM8996_SLAVE_BLSP_1 120
132
+
#define MSM8996_SLAVE_PDM 121
133
+
#define MSM8996_SLAVE_AHB2PHY 122
134
+
#define MSM8996_SLAVE_APPSS 123
135
+
#define MSM8996_SLAVE_LPASS 124
136
+
#define MSM8996_SLAVE_USB3 125
137
+
#define MSM8996_SLAVE_SNOC_BIMC 126
138
+
#define MSM8996_SLAVE_SNOC_CNOC 127
139
+
#define MSM8996_SLAVE_OCIMEM 128
140
+
#define MSM8996_SLAVE_PIMEM 129
141
+
#define MSM8996_SLAVE_SNOC_VMEM 130
142
+
#define MSM8996_SLAVE_SNOC_PNOC 131
143
+
#define MSM8996_SLAVE_QDSS_STM 132
144
+
#define MSM8996_SLAVE_PCIE_0 133
145
+
#define MSM8996_SLAVE_PCIE_1 134
146
+
#define MSM8996_SLAVE_PCIE_2 135
147
+
#define MSM8996_SLAVE_SERVICE_SNOC 136
148
+
149
+
#endif /* __DRIVERS_INTERCONNECT_QCOM_MSM8996_H__ */