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SoC: SOF: Intel: hda/mtl: Improve and enable DMI L1

Merge series from Peter Ujfalusi <peter.ujfalusi@linux.intel.com>:

The first patch will improve the managing of DMI L1 by tracking it's
enabled/disabled state to avoid unconditional changes to it's state.

The remaining two patch will enable the DMI L1 for MTL platforms (ACE 1.0)

+27 -13
+5 -3
sound/soc/sof/intel/hda-ctrl.c
··· 158 158 */ 159 159 int hda_dsp_ctrl_clock_power_gating(struct snd_sof_dev *sdev, bool enable) 160 160 { 161 + struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; 161 162 u32 val; 162 163 163 164 /* enable/disable audio dsp clock gating */ 164 165 val = enable ? PCI_CGCTL_ADSPDCGE : 0; 165 166 snd_sof_pci_update_bits(sdev, PCI_CGCTL, PCI_CGCTL_ADSPDCGE, val); 166 167 167 - /* enable/disable DMI Link L1 support */ 168 + /* disable the DMI link when requested. But enable only if it wasn't disabled previously */ 168 169 val = enable ? HDA_VS_INTEL_EM2_L1SEN : 0; 169 - snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, HDA_VS_INTEL_EM2, 170 - HDA_VS_INTEL_EM2_L1SEN, val); 170 + if (!enable || !hda->l1_disabled) 171 + snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, HDA_VS_INTEL_EM2, 172 + HDA_VS_INTEL_EM2_L1SEN, val); 171 173 172 174 /* enable/disable audio dsp power gating */ 173 175 val = enable ? 0 : PCI_PGCTL_ADSPPGD;
+4 -6
sound/soc/sof/intel/hda-dsp.c
··· 776 776 } 777 777 778 778 /* restore L1SEN bit */ 779 - if (hda->l1_support_changed) 779 + if (hda->l1_disabled) 780 780 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, 781 781 HDA_VS_INTEL_EM2, 782 782 HDA_VS_INTEL_EM2_L1SEN, 0); ··· 868 868 } 869 869 870 870 /* enable L1SEN to make sure the system can enter S0Ix */ 871 - hda->l1_support_changed = 872 - snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, 873 - HDA_VS_INTEL_EM2, 874 - HDA_VS_INTEL_EM2_L1SEN, 875 - HDA_VS_INTEL_EM2_L1SEN); 871 + if (hda->l1_disabled) 872 + snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, HDA_VS_INTEL_EM2, 873 + HDA_VS_INTEL_EM2_L1SEN, HDA_VS_INTEL_EM2_L1SEN); 876 874 877 875 /* stop the CORB/RIRB DMA if it is On */ 878 876 hda_codec_suspend_cmd_io(sdev);
+12 -3
sound/soc/sof/intel/hda-stream.c
··· 182 182 struct hdac_ext_stream * 183 183 hda_dsp_stream_get(struct snd_sof_dev *sdev, int direction, u32 flags) 184 184 { 185 + const struct sof_intel_dsp_desc *chip_info = get_chip_info(sdev->pdata); 186 + struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; 185 187 struct hdac_bus *bus = sof_to_bus(sdev); 186 188 struct sof_intel_hda_stream *hda_stream; 187 189 struct hdac_ext_stream *hext_stream = NULL; ··· 222 220 /* 223 221 * Prevent DMI Link L1 entry for streams that don't support it. 224 222 * Workaround to address a known issue with host DMA that results 225 - * in xruns during pause/release in capture scenarios. 223 + * in xruns during pause/release in capture scenarios. This is not needed for the ACE IP. 226 224 */ 227 - if (!(flags & SOF_HDA_STREAM_DMI_L1_COMPATIBLE)) 225 + if (chip_info->hw_ip_version < SOF_INTEL_ACE_1_0 && 226 + !(flags & SOF_HDA_STREAM_DMI_L1_COMPATIBLE)) { 228 227 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, 229 228 HDA_VS_INTEL_EM2, 230 229 HDA_VS_INTEL_EM2_L1SEN, 0); 230 + hda->l1_disabled = true; 231 + } 231 232 232 233 return hext_stream; 233 234 } ··· 238 233 /* free a stream */ 239 234 int hda_dsp_stream_put(struct snd_sof_dev *sdev, int direction, int stream_tag) 240 235 { 236 + const struct sof_intel_dsp_desc *chip_info = get_chip_info(sdev->pdata); 237 + struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; 241 238 struct hdac_bus *bus = sof_to_bus(sdev); 242 239 struct sof_intel_hda_stream *hda_stream; 243 240 struct hdac_ext_stream *hext_stream; ··· 271 264 spin_unlock_irq(&bus->reg_lock); 272 265 273 266 /* Enable DMI L1 if permitted */ 274 - if (dmi_l1_enable) 267 + if (chip_info->hw_ip_version < SOF_INTEL_ACE_1_0 && dmi_l1_enable) { 275 268 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, HDA_VS_INTEL_EM2, 276 269 HDA_VS_INTEL_EM2_L1SEN, HDA_VS_INTEL_EM2_L1SEN); 270 + hda->l1_disabled = false; 271 + } 277 272 278 273 if (!found) { 279 274 dev_err(sdev->dev, "%s: stream_tag %d not opened!\n",
+1 -1
sound/soc/sof/intel/hda.h
··· 502 502 u32 stream_max; 503 503 504 504 /* PM related */ 505 - bool l1_support_changed;/* during suspend, is L1SEN changed or not */ 505 + bool l1_disabled;/* is DMI link L1 disabled? */ 506 506 507 507 /* DMIC device */ 508 508 struct platform_device *dmic_dev;
+3
sound/soc/sof/intel/mtl.c
··· 280 280 } 281 281 282 282 hda_sdw_int_enable(sdev, true); 283 + 284 + /* enable DMI L1 */ 285 + snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, MTL_EM2, MTL_EM2_L1SEN, MTL_EM2_L1SEN); 283 286 return 0; 284 287 } 285 288
+2
sound/soc/sof/intel/mtl.h
··· 28 28 #define MTL_HFINTIPPTR_PTR_MASK GENMASK(20, 0) 29 29 30 30 #define MTL_HDA_VS_D0I3C 0x1D4A 31 + #define MTL_EM2 0x1c44 32 + #define MTL_EM2_L1SEN BIT(13) 31 33 32 34 #define MTL_DSP2CXCAP_PRIMARY_CORE 0x178D00 33 35 #define MTL_DSP2CXCTL_PRIMARY_CORE 0x178D04