Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'drm-fixes-2019-01-11-1' of git://anongit.freedesktop.org/drm/drm
Pull more drm fixes from Daniel Vetter:
"Dave sends out his pull, everybody remembers holidays are over :-)
Since Dave's already in weekend mode and it was quite a few patches I
figured better to apply all the pulls and forward them to you. Hence
here 2nd part of bugfixes for -rc2.
nouveau:
- backlight fix
- falcon register access fix
- fan fix.
i915:
- Disable PSR for Apple panels
- Broxton ERR_PTR error state fix
- Kabylake VECS workaround fix
- Unwind failure on pinning the gen7 ppgtt
- GVT workload request allocation fix
core:
- Fix fb-helper to work correctly with SDL 1.2 bugs
- Fix lockdep warning in the atomic ioctl and setproperty"
* tag 'drm-fixes-2019-01-11-1' of git://anongit.freedesktop.org/drm/drm:
drm/nouveau/falcon: avoid touching registers if engine is off
drm/nouveau: Don't disable polling in fallback mode
drm/nouveau: register backlight on pascal and newer
drm: Fix documentation generation for DP_DPCD_QUIRK_NO_PSR
drm/i915: init per-engine WAs for all engines
drm/i915: Unwind failure on pinning the gen7 ppgtt
drm/i915: Skip the ERR_PTR error state
drm/i915: Disable PSR in Apple panels
gpu/drm: Fix lock held when returning to user space.
drm/fb-helper: Ignore the value of fb_var_screeninfo.pixclock
drm/fb-helper: Partially bring back workaround for bugs of SDL 1.2
drm/i915/gvt: Fix workload request allocation before request add
+192
-102
+1
-2
drivers/gpu/drm/drm_atomic_uapi.c
+1
-2
drivers/gpu/drm/drm_atomic_uapi.c
···
1296
1296
(arg->flags & DRM_MODE_PAGE_FLIP_EVENT))
1297
1297
return -EINVAL;
1298
1298
1299
-
drm_modeset_acquire_init(&ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE);
1300
-
1301
1299
state = drm_atomic_state_alloc(dev);
1302
1300
if (!state)
1303
1301
return -ENOMEM;
1304
1302
1303
+
drm_modeset_acquire_init(&ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE);
1305
1304
state->acquire_ctx = &ctx;
1306
1305
state->allow_modeset = !!(arg->flags & DRM_MODE_ATOMIC_ALLOW_MODESET);
1307
1306
+2
drivers/gpu/drm/drm_dp_helper.c
+2
drivers/gpu/drm/drm_dp_helper.c
···
1273
1273
{ OUI(0x00, 0x22, 0xb9), DEVICE_ID_ANY, true, BIT(DP_DPCD_QUIRK_CONSTANT_N) },
1274
1274
/* LG LP140WF6-SPM1 eDP panel */
1275
1275
{ OUI(0x00, 0x22, 0xb9), DEVICE_ID('s', 'i', 'v', 'a', 'r', 'T'), false, BIT(DP_DPCD_QUIRK_CONSTANT_N) },
1276
+
/* Apple panels need some additional handling to support PSR */
1277
+
{ OUI(0x00, 0x10, 0xfa), DEVICE_ID_ANY, false, BIT(DP_DPCD_QUIRK_NO_PSR) }
1276
1278
};
1277
1279
1278
1280
#undef OUI
+79
-54
drivers/gpu/drm/drm_fb_helper.c
+79
-54
drivers/gpu/drm/drm_fb_helper.c
···
1621
1621
var_1->transp.msb_right == var_2->transp.msb_right;
1622
1622
}
1623
1623
1624
+
static void drm_fb_helper_fill_pixel_fmt(struct fb_var_screeninfo *var,
1625
+
u8 depth)
1626
+
{
1627
+
switch (depth) {
1628
+
case 8:
1629
+
var->red.offset = 0;
1630
+
var->green.offset = 0;
1631
+
var->blue.offset = 0;
1632
+
var->red.length = 8; /* 8bit DAC */
1633
+
var->green.length = 8;
1634
+
var->blue.length = 8;
1635
+
var->transp.offset = 0;
1636
+
var->transp.length = 0;
1637
+
break;
1638
+
case 15:
1639
+
var->red.offset = 10;
1640
+
var->green.offset = 5;
1641
+
var->blue.offset = 0;
1642
+
var->red.length = 5;
1643
+
var->green.length = 5;
1644
+
var->blue.length = 5;
1645
+
var->transp.offset = 15;
1646
+
var->transp.length = 1;
1647
+
break;
1648
+
case 16:
1649
+
var->red.offset = 11;
1650
+
var->green.offset = 5;
1651
+
var->blue.offset = 0;
1652
+
var->red.length = 5;
1653
+
var->green.length = 6;
1654
+
var->blue.length = 5;
1655
+
var->transp.offset = 0;
1656
+
break;
1657
+
case 24:
1658
+
var->red.offset = 16;
1659
+
var->green.offset = 8;
1660
+
var->blue.offset = 0;
1661
+
var->red.length = 8;
1662
+
var->green.length = 8;
1663
+
var->blue.length = 8;
1664
+
var->transp.offset = 0;
1665
+
var->transp.length = 0;
1666
+
break;
1667
+
case 32:
1668
+
var->red.offset = 16;
1669
+
var->green.offset = 8;
1670
+
var->blue.offset = 0;
1671
+
var->red.length = 8;
1672
+
var->green.length = 8;
1673
+
var->blue.length = 8;
1674
+
var->transp.offset = 24;
1675
+
var->transp.length = 8;
1676
+
break;
1677
+
default:
1678
+
break;
1679
+
}
1680
+
}
1681
+
1624
1682
/**
1625
1683
* drm_fb_helper_check_var - implementation for &fb_ops.fb_check_var
1626
1684
* @var: screeninfo to check
···
1690
1632
struct drm_fb_helper *fb_helper = info->par;
1691
1633
struct drm_framebuffer *fb = fb_helper->fb;
1692
1634
1693
-
if (var->pixclock != 0 || in_dbg_master())
1635
+
if (in_dbg_master())
1694
1636
return -EINVAL;
1637
+
1638
+
if (var->pixclock != 0) {
1639
+
DRM_DEBUG("fbdev emulation doesn't support changing the pixel clock, value of pixclock is ignored\n");
1640
+
var->pixclock = 0;
1641
+
}
1695
1642
1696
1643
if ((drm_format_info_block_width(fb->format, 0) > 1) ||
1697
1644
(drm_format_info_block_height(fb->format, 0) > 1))
···
1715
1652
var->xres_virtual, var->yres_virtual,
1716
1653
fb->width, fb->height, fb->format->cpp[0] * 8);
1717
1654
return -EINVAL;
1655
+
}
1656
+
1657
+
/*
1658
+
* Workaround for SDL 1.2, which is known to be setting all pixel format
1659
+
* fields values to zero in some cases. We treat this situation as a
1660
+
* kind of "use some reasonable autodetected values".
1661
+
*/
1662
+
if (!var->red.offset && !var->green.offset &&
1663
+
!var->blue.offset && !var->transp.offset &&
1664
+
!var->red.length && !var->green.length &&
1665
+
!var->blue.length && !var->transp.length &&
1666
+
!var->red.msb_right && !var->green.msb_right &&
1667
+
!var->blue.msb_right && !var->transp.msb_right) {
1668
+
drm_fb_helper_fill_pixel_fmt(var, fb->format->depth);
1718
1669
}
1719
1670
1720
1671
/*
···
2044
1967
info->var.yoffset = 0;
2045
1968
info->var.activate = FB_ACTIVATE_NOW;
2046
1969
2047
-
switch (fb->format->depth) {
2048
-
case 8:
2049
-
info->var.red.offset = 0;
2050
-
info->var.green.offset = 0;
2051
-
info->var.blue.offset = 0;
2052
-
info->var.red.length = 8; /* 8bit DAC */
2053
-
info->var.green.length = 8;
2054
-
info->var.blue.length = 8;
2055
-
info->var.transp.offset = 0;
2056
-
info->var.transp.length = 0;
2057
-
break;
2058
-
case 15:
2059
-
info->var.red.offset = 10;
2060
-
info->var.green.offset = 5;
2061
-
info->var.blue.offset = 0;
2062
-
info->var.red.length = 5;
2063
-
info->var.green.length = 5;
2064
-
info->var.blue.length = 5;
2065
-
info->var.transp.offset = 15;
2066
-
info->var.transp.length = 1;
2067
-
break;
2068
-
case 16:
2069
-
info->var.red.offset = 11;
2070
-
info->var.green.offset = 5;
2071
-
info->var.blue.offset = 0;
2072
-
info->var.red.length = 5;
2073
-
info->var.green.length = 6;
2074
-
info->var.blue.length = 5;
2075
-
info->var.transp.offset = 0;
2076
-
break;
2077
-
case 24:
2078
-
info->var.red.offset = 16;
2079
-
info->var.green.offset = 8;
2080
-
info->var.blue.offset = 0;
2081
-
info->var.red.length = 8;
2082
-
info->var.green.length = 8;
2083
-
info->var.blue.length = 8;
2084
-
info->var.transp.offset = 0;
2085
-
info->var.transp.length = 0;
2086
-
break;
2087
-
case 32:
2088
-
info->var.red.offset = 16;
2089
-
info->var.green.offset = 8;
2090
-
info->var.blue.offset = 0;
2091
-
info->var.red.length = 8;
2092
-
info->var.green.length = 8;
2093
-
info->var.blue.length = 8;
2094
-
info->var.transp.offset = 24;
2095
-
info->var.transp.length = 8;
2096
-
break;
2097
-
default:
2098
-
break;
2099
-
}
1970
+
drm_fb_helper_fill_pixel_fmt(&info->var, fb->format->depth);
2100
1971
2101
1972
info->var.xres = fb_width;
2102
1973
info->var.yres = fb_height;
+2
-2
drivers/gpu/drm/drm_mode_object.c
+2
-2
drivers/gpu/drm/drm_mode_object.c
···
459
459
struct drm_modeset_acquire_ctx ctx;
460
460
int ret;
461
461
462
-
drm_modeset_acquire_init(&ctx, 0);
463
-
464
462
state = drm_atomic_state_alloc(dev);
465
463
if (!state)
466
464
return -ENOMEM;
465
+
466
+
drm_modeset_acquire_init(&ctx, 0);
467
467
state->acquire_ctx = &ctx;
468
468
retry:
469
469
if (prop == state->dev->mode_config.dpms_property) {
+42
-22
drivers/gpu/drm/i915/gvt/scheduler.c
+42
-22
drivers/gpu/drm/i915/gvt/scheduler.c
···
356
356
return 0;
357
357
}
358
358
359
+
static int
360
+
intel_gvt_workload_req_alloc(struct intel_vgpu_workload *workload)
361
+
{
362
+
struct intel_vgpu *vgpu = workload->vgpu;
363
+
struct intel_vgpu_submission *s = &vgpu->submission;
364
+
struct i915_gem_context *shadow_ctx = s->shadow_ctx;
365
+
struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
366
+
struct intel_engine_cs *engine = dev_priv->engine[workload->ring_id];
367
+
struct i915_request *rq;
368
+
int ret = 0;
369
+
370
+
lockdep_assert_held(&dev_priv->drm.struct_mutex);
371
+
372
+
if (workload->req)
373
+
goto out;
374
+
375
+
rq = i915_request_alloc(engine, shadow_ctx);
376
+
if (IS_ERR(rq)) {
377
+
gvt_vgpu_err("fail to allocate gem request\n");
378
+
ret = PTR_ERR(rq);
379
+
goto out;
380
+
}
381
+
workload->req = i915_request_get(rq);
382
+
out:
383
+
return ret;
384
+
}
385
+
359
386
/**
360
387
* intel_gvt_scan_and_shadow_workload - audit the workload by scanning and
361
388
* shadow it as well, include ringbuffer,wa_ctx and ctx.
···
399
372
struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
400
373
struct intel_engine_cs *engine = dev_priv->engine[workload->ring_id];
401
374
struct intel_context *ce;
402
-
struct i915_request *rq;
403
375
int ret;
404
376
405
377
lockdep_assert_held(&dev_priv->drm.struct_mutex);
406
378
407
-
if (workload->req)
379
+
if (workload->shadow)
408
380
return 0;
409
381
410
382
ret = set_context_ppgtt_from_shadow(workload, shadow_ctx);
···
443
417
goto err_shadow;
444
418
}
445
419
446
-
rq = i915_request_alloc(engine, shadow_ctx);
447
-
if (IS_ERR(rq)) {
448
-
gvt_vgpu_err("fail to allocate gem request\n");
449
-
ret = PTR_ERR(rq);
450
-
goto err_shadow;
451
-
}
452
-
workload->req = i915_request_get(rq);
453
-
454
-
ret = populate_shadow_context(workload);
455
-
if (ret)
456
-
goto err_req;
457
-
420
+
workload->shadow = true;
458
421
return 0;
459
-
err_req:
460
-
rq = fetch_and_zero(&workload->req);
461
-
i915_request_put(rq);
462
422
err_shadow:
463
423
release_shadow_wa_ctx(&workload->wa_ctx);
464
424
err_unpin:
···
683
671
mutex_lock(&vgpu->vgpu_lock);
684
672
mutex_lock(&dev_priv->drm.struct_mutex);
685
673
674
+
ret = intel_gvt_workload_req_alloc(workload);
675
+
if (ret)
676
+
goto err_req;
677
+
686
678
ret = intel_gvt_scan_and_shadow_workload(workload);
687
679
if (ret)
688
680
goto out;
689
681
682
+
ret = populate_shadow_context(workload);
683
+
if (ret) {
684
+
release_shadow_wa_ctx(&workload->wa_ctx);
685
+
goto out;
686
+
}
687
+
690
688
ret = prepare_workload(workload);
691
-
692
689
out:
693
-
if (ret)
694
-
workload->status = ret;
695
-
696
690
if (!IS_ERR_OR_NULL(workload->req)) {
697
691
gvt_dbg_sched("ring id %d submit workload to i915 %p\n",
698
692
ring_id, workload->req);
699
693
i915_request_add(workload->req);
700
694
workload->dispatched = true;
701
695
}
702
-
696
+
err_req:
697
+
if (ret)
698
+
workload->status = ret;
703
699
mutex_unlock(&dev_priv->drm.struct_mutex);
704
700
mutex_unlock(&vgpu->vgpu_lock);
705
701
return ret;
+1
drivers/gpu/drm/i915/gvt/scheduler.h
+1
drivers/gpu/drm/i915/gvt/scheduler.h
+9
-3
drivers/gpu/drm/i915/i915_debugfs.c
+9
-3
drivers/gpu/drm/i915/i915_debugfs.c
···
984
984
intel_runtime_pm_get(i915);
985
985
gpu = i915_capture_gpu_state(i915);
986
986
intel_runtime_pm_put(i915);
987
-
if (!gpu)
988
-
return -ENOMEM;
987
+
if (IS_ERR(gpu))
988
+
return PTR_ERR(gpu);
989
989
990
990
file->private_data = gpu;
991
991
return 0;
···
1018
1018
1019
1019
static int i915_error_state_open(struct inode *inode, struct file *file)
1020
1020
{
1021
-
file->private_data = i915_first_error_state(inode->i_private);
1021
+
struct i915_gpu_state *error;
1022
+
1023
+
error = i915_first_error_state(inode->i_private);
1024
+
if (IS_ERR(error))
1025
+
return PTR_ERR(error);
1026
+
1027
+
file->private_data = error;
1022
1028
return 0;
1023
1029
}
1024
1030
+12
-3
drivers/gpu/drm/i915/i915_gem_gtt.c
+12
-3
drivers/gpu/drm/i915/i915_gem_gtt.c
···
2075
2075
int gen6_ppgtt_pin(struct i915_hw_ppgtt *base)
2076
2076
{
2077
2077
struct gen6_hw_ppgtt *ppgtt = to_gen6_ppgtt(base);
2078
+
int err;
2078
2079
2079
2080
/*
2080
2081
* Workaround the limited maximum vma->pin_count and the aliasing_ppgtt
···
2091
2090
* allocator works in address space sizes, so it's multiplied by page
2092
2091
* size. We allocate at the top of the GTT to avoid fragmentation.
2093
2092
*/
2094
-
return i915_vma_pin(ppgtt->vma,
2095
-
0, GEN6_PD_ALIGN,
2096
-
PIN_GLOBAL | PIN_HIGH);
2093
+
err = i915_vma_pin(ppgtt->vma,
2094
+
0, GEN6_PD_ALIGN,
2095
+
PIN_GLOBAL | PIN_HIGH);
2096
+
if (err)
2097
+
goto unpin;
2098
+
2099
+
return 0;
2100
+
2101
+
unpin:
2102
+
ppgtt->pin_count = 0;
2103
+
return err;
2097
2104
}
2098
2105
2099
2106
void gen6_ppgtt_unpin(struct i915_hw_ppgtt *base)
+14
-9
drivers/gpu/drm/i915/i915_gpu_error.c
+14
-9
drivers/gpu/drm/i915/i915_gpu_error.c
···
1907
1907
{
1908
1908
struct i915_gpu_state *error;
1909
1909
1910
+
/* Check if GPU capture has been disabled */
1911
+
error = READ_ONCE(i915->gpu_error.first_error);
1912
+
if (IS_ERR(error))
1913
+
return error;
1914
+
1910
1915
error = kzalloc(sizeof(*error), GFP_ATOMIC);
1911
-
if (!error)
1912
-
return NULL;
1916
+
if (!error) {
1917
+
i915_disable_error_state(i915, -ENOMEM);
1918
+
return ERR_PTR(-ENOMEM);
1919
+
}
1913
1920
1914
1921
kref_init(&error->ref);
1915
1922
error->i915 = i915;
···
1952
1945
return;
1953
1946
1954
1947
error = i915_capture_gpu_state(i915);
1955
-
if (!error) {
1956
-
DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
1957
-
i915_disable_error_state(i915, -ENOMEM);
1948
+
if (IS_ERR(error))
1958
1949
return;
1959
-
}
1960
1950
1961
1951
i915_error_capture_msg(i915, error, engine_mask, error_msg);
1962
1952
DRM_INFO("%s\n", error->error_msg);
···
1991
1987
1992
1988
spin_lock_irq(&i915->gpu_error.lock);
1993
1989
error = i915->gpu_error.first_error;
1994
-
if (error)
1990
+
if (!IS_ERR_OR_NULL(error))
1995
1991
i915_gpu_state_get(error);
1996
1992
spin_unlock_irq(&i915->gpu_error.lock);
1997
1993
···
2004
2000
2005
2001
spin_lock_irq(&i915->gpu_error.lock);
2006
2002
error = i915->gpu_error.first_error;
2007
-
i915->gpu_error.first_error = NULL;
2003
+
if (error != ERR_PTR(-ENODEV)) /* if disabled, always disabled */
2004
+
i915->gpu_error.first_error = NULL;
2008
2005
spin_unlock_irq(&i915->gpu_error.lock);
2009
2006
2010
-
if (!IS_ERR(error))
2007
+
if (!IS_ERR_OR_NULL(error))
2011
2008
i915_gpu_state_put(error);
2012
2009
}
2013
2010
+3
-1
drivers/gpu/drm/i915/i915_sysfs.c
+3
-1
drivers/gpu/drm/i915/i915_sysfs.c
+2
-1
drivers/gpu/drm/i915/intel_lrc.c
+2
-1
drivers/gpu/drm/i915/intel_lrc.c
···
2244
2244
if (ret)
2245
2245
return ret;
2246
2246
2247
+
intel_engine_init_workarounds(engine);
2248
+
2247
2249
if (HAS_LOGICAL_RING_ELSQ(i915)) {
2248
2250
execlists->submit_reg = i915->regs +
2249
2251
i915_mmio_reg_offset(RING_EXECLIST_SQ_CONTENTS(engine));
···
2312
2310
}
2313
2311
2314
2312
intel_engine_init_whitelist(engine);
2315
-
intel_engine_init_workarounds(engine);
2316
2313
2317
2314
return 0;
2318
2315
}
+6
drivers/gpu/drm/i915/intel_psr.c
+6
drivers/gpu/drm/i915/intel_psr.c
···
274
274
DRM_DEBUG_KMS("eDP panel supports PSR version %x\n",
275
275
intel_dp->psr_dpcd[0]);
276
276
277
+
if (drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_NO_PSR)) {
278
+
DRM_DEBUG_KMS("PSR support not currently available for this panel\n");
279
+
return;
280
+
}
281
+
277
282
if (!(intel_dp->edp_dpcd[1] & DP_EDP_SET_POWER_CAP)) {
278
283
DRM_DEBUG_KMS("Panel lacks power state control, PSR cannot be enabled\n");
279
284
return;
280
285
}
286
+
281
287
dev_priv->psr.sink_support = true;
282
288
dev_priv->psr.sink_sync_latency =
283
289
intel_dp_get_sink_sync_latency(intel_dp);
+3
drivers/gpu/drm/nouveau/nouveau_backlight.c
+3
drivers/gpu/drm/nouveau/nouveau_backlight.c
···
253
253
case NV_DEVICE_INFO_V0_FERMI:
254
254
case NV_DEVICE_INFO_V0_KEPLER:
255
255
case NV_DEVICE_INFO_V0_MAXWELL:
256
+
case NV_DEVICE_INFO_V0_PASCAL:
257
+
case NV_DEVICE_INFO_V0_VOLTA:
258
+
case NV_DEVICE_INFO_V0_TURING:
256
259
ret = nv50_backlight_init(nv_encoder, &props, &ops);
257
260
break;
258
261
default:
+5
-2
drivers/gpu/drm/nouveau/nvkm/engine/falcon.c
+5
-2
drivers/gpu/drm/nouveau/nvkm/engine/falcon.c
···
22
22
#include <engine/falcon.h>
23
23
24
24
#include <core/gpuobj.h>
25
+
#include <subdev/mc.h>
25
26
#include <subdev/timer.h>
26
27
#include <engine/fifo.h>
27
28
···
108
107
}
109
108
}
110
109
111
-
nvkm_mask(device, base + 0x048, 0x00000003, 0x00000000);
112
-
nvkm_wr32(device, base + 0x014, 0xffffffff);
110
+
if (nvkm_mc_enabled(device, engine->subdev.index)) {
111
+
nvkm_mask(device, base + 0x048, 0x00000003, 0x00000000);
112
+
nvkm_wr32(device, base + 0x014, 0xffffffff);
113
+
}
113
114
return 0;
114
115
}
115
116
+4
-3
drivers/gpu/drm/nouveau/nvkm/subdev/therm/base.c
+4
-3
drivers/gpu/drm/nouveau/nvkm/subdev/therm/base.c
···
132
132
duty = nvkm_therm_update_linear(therm);
133
133
break;
134
134
case NVBIOS_THERM_FAN_OTHER:
135
-
if (therm->cstate)
135
+
if (therm->cstate) {
136
136
duty = therm->cstate;
137
-
else
137
+
poll = false;
138
+
} else {
138
139
duty = nvkm_therm_update_linear_fallback(therm);
139
-
poll = false;
140
+
}
140
141
break;
141
142
}
142
143
immd = false;
+7
include/drm/drm_dp_helper.h
+7
include/drm/drm_dp_helper.h
···
1365
1365
* to 16 bits. So will give a constant value (0x8000) for compatability.
1366
1366
*/
1367
1367
DP_DPCD_QUIRK_CONSTANT_N,
1368
+
/**
1369
+
* @DP_DPCD_QUIRK_NO_PSR:
1370
+
*
1371
+
* The device does not support PSR even if reports that it supports or
1372
+
* driver still need to implement proper handling for such device.
1373
+
*/
1374
+
DP_DPCD_QUIRK_NO_PSR,
1368
1375
};
1369
1376
1370
1377
/**