Merge tag 'clk-remove-deprecated-apis-v7.1' of ssh://github.com/masneyb/linux into clk-round

+1 -8

Documentation/driver-api/clk.rst

··· 77 77 void (*disable_unused)(struct clk_hw *hw); 78 78 unsigned long (*recalc_rate)(struct clk_hw *hw, 79 79 unsigned long parent_rate); 80 - long (*round_rate)(struct clk_hw *hw, 81 - unsigned long rate, 82 - unsigned long *parent_rate); 83 80 int (*determine_rate)(struct clk_hw *hw, 84 81 struct clk_rate_request *req); 85 82 int (*set_parent)(struct clk_hw *hw, u8 index); ··· 217 220 +----------------+------+-------------+---------------+-------------+------+ 218 221 |.recalc_rate | | y | | | | 219 222 +----------------+------+-------------+---------------+-------------+------+ 220 - |.round_rate | | y [1]_ | | | | 221 - +----------------+------+-------------+---------------+-------------+------+ 222 - |.determine_rate | | y [1]_ | | | | 223 + |.determine_rate | | y | | | | 223 224 +----------------+------+-------------+---------------+-------------+------+ 224 225 |.set_rate | | y | | | | 225 226 +----------------+------+-------------+---------------+-------------+------+ ··· 232 237 +----------------+------+-------------+---------------+-------------+------+ 233 238 |.init | | | | | | 234 239 +----------------+------+-------------+---------------+-------------+------+ 235 - 236 - .. [1] either one of round_rate or determine_rate is required. 237 240 238 241 Finally, register your clock at run-time with a hardware-specific 239 242 registration function. This function simply populates struct clk_foo's

+5 -33

drivers/clk/clk-composite.c

··· 47 47 struct clk_hw *parent_hw, 48 48 const struct clk_ops *rate_ops) 49 49 { 50 - long rate; 51 - 52 50 req->best_parent_hw = parent_hw; 53 51 req->best_parent_rate = clk_hw_get_rate(parent_hw); 54 52 55 - if (rate_ops->determine_rate) 56 - return rate_ops->determine_rate(rate_hw, req); 57 - 58 - rate = rate_ops->round_rate(rate_hw, req->rate, 59 - &req->best_parent_rate); 60 - if (rate < 0) 61 - return rate; 62 - 63 - req->rate = rate; 64 - 65 - return 0; 53 + return rate_ops->determine_rate(rate_hw, req); 66 54 } 67 55 68 56 static int clk_composite_determine_rate(struct clk_hw *hw, ··· 67 79 unsigned long best_rate = 0; 68 80 int i, ret; 69 81 70 - if (rate_hw && rate_ops && 71 - (rate_ops->determine_rate || rate_ops->round_rate) && 82 + if (rate_hw && rate_ops && rate_ops->determine_rate && 72 83 mux_hw && mux_ops && mux_ops->set_parent) { 73 84 req->best_parent_hw = NULL; 74 85 ··· 135 148 pr_err("clk: clk_composite_determine_rate function called, but no mux or rate callback set!\n"); 136 149 return -EINVAL; 137 150 } 138 - } 139 - 140 - static long clk_composite_round_rate(struct clk_hw *hw, unsigned long rate, 141 - unsigned long *prate) 142 - { 143 - struct clk_composite *composite = to_clk_composite(hw); 144 - const struct clk_ops *rate_ops = composite->rate_ops; 145 - struct clk_hw *rate_hw = composite->rate_hw; 146 - 147 - __clk_hw_set_clk(rate_hw, hw); 148 - 149 - return rate_ops->round_rate(rate_hw, rate, prate); 150 151 } 151 152 152 153 static int clk_composite_set_rate(struct clk_hw *hw, unsigned long rate, ··· 263 288 if (rate_ops->determine_rate) 264 289 clk_composite_ops->determine_rate = 265 290 clk_composite_determine_rate; 266 - else if (rate_ops->round_rate) 267 - clk_composite_ops->round_rate = 268 - clk_composite_round_rate; 269 291 270 - /* .set_rate requires either .round_rate or .determine_rate */ 292 + /* .set_rate requires .determine_rate */ 271 293 if (rate_ops->set_rate) { 272 - if (rate_ops->determine_rate || rate_ops->round_rate) 294 + if (rate_ops->determine_rate) 273 295 clk_composite_ops->set_rate = 274 296 clk_composite_set_rate; 275 297 else 276 - WARN(1, "%s: missing round_rate op is required\n", 298 + WARN(1, "%s: missing determine_rate op is required\n", 277 299 __func__); 278 300 } 279 301

-44

drivers/clk/clk-divider.c

··· 387 387 } 388 388 EXPORT_SYMBOL_GPL(divider_ro_determine_rate); 389 389 390 - long divider_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent, 391 - unsigned long rate, unsigned long *prate, 392 - const struct clk_div_table *table, 393 - u8 width, unsigned long flags) 394 - { 395 - struct clk_rate_request req; 396 - int ret; 397 - 398 - clk_hw_init_rate_request(hw, &req, rate); 399 - req.best_parent_rate = *prate; 400 - req.best_parent_hw = parent; 401 - 402 - ret = divider_determine_rate(hw, &req, table, width, flags); 403 - if (ret) 404 - return ret; 405 - 406 - *prate = req.best_parent_rate; 407 - 408 - return req.rate; 409 - } 410 - EXPORT_SYMBOL_GPL(divider_round_rate_parent); 411 - 412 - long divider_ro_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent, 413 - unsigned long rate, unsigned long *prate, 414 - const struct clk_div_table *table, u8 width, 415 - unsigned long flags, unsigned int val) 416 - { 417 - struct clk_rate_request req; 418 - int ret; 419 - 420 - clk_hw_init_rate_request(hw, &req, rate); 421 - req.best_parent_rate = *prate; 422 - req.best_parent_hw = parent; 423 - 424 - ret = divider_ro_determine_rate(hw, &req, table, width, flags, val); 425 - if (ret) 426 - return ret; 427 - 428 - *prate = req.best_parent_rate; 429 - 430 - return req.rate; 431 - } 432 - EXPORT_SYMBOL_GPL(divider_ro_round_rate_parent); 433 - 434 390 static int clk_divider_determine_rate(struct clk_hw *hw, 435 391 struct clk_rate_request *req) 436 392 {

+14 -25

drivers/clk/clk.c

··· 1560 1560 static int clk_core_determine_round_nolock(struct clk_core *core, 1561 1561 struct clk_rate_request *req) 1562 1562 { 1563 - long rate; 1564 - 1565 1563 lockdep_assert_held(&prepare_lock); 1566 1564 1567 1565 if (!core) ··· 1589 1591 req->rate = core->rate; 1590 1592 } else if (core->ops->determine_rate) { 1591 1593 return core->ops->determine_rate(core->hw, req); 1592 - } else if (core->ops->round_rate) { 1593 - rate = core->ops->round_rate(core->hw, req->rate, 1594 - &req->best_parent_rate); 1595 - if (rate < 0) 1596 - return rate; 1597 - 1598 - req->rate = rate; 1599 1594 } else { 1600 1595 return -EINVAL; 1601 1596 } ··· 1673 1682 1674 1683 static bool clk_core_can_round(struct clk_core * const core) 1675 1684 { 1676 - return core->ops->determine_rate || core->ops->round_rate; 1685 + return core->ops->determine_rate; 1677 1686 } 1678 1687 1679 1688 static int clk_core_round_rate_nolock(struct clk_core *core, ··· 1741 1750 * use. 1742 1751 * 1743 1752 * Context: prepare_lock must be held. 1744 - * For clk providers to call from within clk_ops such as .round_rate, 1753 + * For clk providers to call from within clk_ops such as 1745 1754 * .determine_rate. 1746 1755 * 1747 - * Return: returns rounded rate of hw clk if clk supports round_rate operation 1748 - * else returns the parent rate. 1756 + * Return: returns rounded rate of hw clk if clk supports determine_rate 1757 + * operation; else returns the parent rate. 1749 1758 */ 1750 1759 unsigned long clk_hw_round_rate(struct clk_hw *hw, unsigned long rate) 1751 1760 { ··· 2560 2569 * 2561 2570 * Setting the CLK_SET_RATE_PARENT flag allows the rate change operation to 2562 2571 * propagate up to clk's parent; whether or not this happens depends on the 2563 - * outcome of clk's .round_rate implementation. If *parent_rate is unchanged 2564 - * after calling .round_rate then upstream parent propagation is ignored. If 2565 - * *parent_rate comes back with a new rate for clk's parent then we propagate 2566 - * up to clk's parent and set its rate. Upward propagation will continue 2567 - * until either a clk does not support the CLK_SET_RATE_PARENT flag or 2568 - * .round_rate stops requesting changes to clk's parent_rate. 2572 + * outcome of clk's .determine_rate implementation. If req->best_parent_rate 2573 + * is unchanged after calling .determine_rate then upstream parent propagation 2574 + * is ignored. If req->best_parent_rate comes back with a new rate for clk's 2575 + * parent then we propagate up to clk's parent and set its rate. Upward 2576 + * propagation will continue until either a clk does not support the 2577 + * CLK_SET_RATE_PARENT flag or .determine_rate stops requesting changes to 2578 + * clk's parent_rate. 2569 2579 * 2570 2580 * Rate changes are accomplished via tree traversal that also recalculates the 2571 2581 * rates for the clocks and fires off POST_RATE_CHANGE notifiers. ··· 2695 2703 * FIXME: 2696 2704 * There is a catch. It may fail for the usual reason (clock 2697 2705 * broken, clock protected, etc) but also because: 2698 - * - round_rate() was not favorable and fell on the wrong 2699 - * side of the boundary 2700 2706 * - the determine_rate() callback does not really check for 2701 2707 * this corner case when determining the rate 2702 2708 */ ··· 3905 3915 } 3906 3916 3907 3917 /* check that clk_ops are sane. See Documentation/driver-api/clk.rst */ 3908 - if (core->ops->set_rate && 3909 - !((core->ops->round_rate || core->ops->determine_rate) && 3910 - core->ops->recalc_rate)) { 3911 - pr_err("%s: %s must implement .round_rate or .determine_rate in addition to .recalc_rate\n", 3918 + if (core->ops->set_rate && !core->ops->determine_rate && 3919 + core->ops->recalc_rate) { 3920 + pr_err("%s: %s must implement .determine_rate in addition to .recalc_rate\n", 3912 3921 __func__, core->name); 3913 3922 ret = -EINVAL; 3914 3923 goto out;

+8 -8

drivers/clk/clk_test.c

··· 241 241 * Test that, after a call to clk_set_rate(), the rate returned by 242 242 * clk_get_rate() matches. 243 243 * 244 - * This assumes that clk_ops.determine_rate or clk_ops.round_rate won't 245 - * modify the requested rate, which is our case in clk_dummy_rate_ops. 244 + * This assumes that clk_ops.determine_rate won't modify the requested rate, 245 + * which is our case in clk_dummy_rate_ops. 246 246 */ 247 247 static void clk_test_set_get_rate(struct kunit *test) 248 248 { ··· 266 266 * Test that, after several calls to clk_set_rate(), the rate returned 267 267 * by clk_get_rate() matches the last one. 268 268 * 269 - * This assumes that clk_ops.determine_rate or clk_ops.round_rate won't 270 - * modify the requested rate, which is our case in clk_dummy_rate_ops. 269 + * This assumes that clk_ops.determine_rate won't modify the requested rate, 270 + * which is our case in clk_dummy_rate_ops. 271 271 */ 272 272 static void clk_test_set_set_get_rate(struct kunit *test) 273 273 { ··· 1675 1675 * call to clk_set_rate_range(), the rate will be raised to match the 1676 1676 * new minimum. 1677 1677 * 1678 - * This assumes that clk_ops.determine_rate or clk_ops.round_rate won't 1679 - * modify the requested rate, which is our case in clk_dummy_rate_ops. 1678 + * This assumes that clk_ops.determine_rate won't modify the requested rate, 1679 + * which is our case in clk_dummy_rate_ops. 1680 1680 */ 1681 1681 static void clk_range_test_set_range_get_rate_raised(struct kunit *test) 1682 1682 { ··· 1707 1707 * call to clk_set_rate_range(), the rate will be lowered to match the 1708 1708 * new maximum. 1709 1709 * 1710 - * This assumes that clk_ops.determine_rate or clk_ops.round_rate won't 1711 - * modify the requested rate, which is our case in clk_dummy_rate_ops. 1710 + * This assumes that clk_ops.determine_rate won't modify the requested rate, 1711 + * which is our case in clk_dummy_rate_ops. 1712 1712 */ 1713 1713 static void clk_range_test_set_range_get_rate_lowered(struct kunit *test) 1714 1714 {

+6 -40

include/linux/clk-provider.h

··· 136 136 * 0. Returns the calculated rate. Optional, but recommended - if 137 137 * this op is not set then clock rate will be initialized to 0. 138 138 * 139 - * @round_rate: Given a target rate as input, returns the closest rate actually 140 - * supported by the clock. The parent rate is an input/output 141 - * parameter. 142 - * 143 139 * @determine_rate: Given a target rate as input, returns the closest rate 144 140 * actually supported by the clock, and optionally the parent clock 145 141 * that should be used to provide the clock rate. ··· 159 163 * 160 164 * @set_rate: Change the rate of this clock. The requested rate is specified 161 165 * by the second argument, which should typically be the return 162 - * of .round_rate call. The third argument gives the parent rate 163 - * which is likely helpful for most .set_rate implementation. 166 + * of .determine_rate call. The third argument gives the parent 167 + * rate which is likely helpful for most .set_rate implementation. 164 168 * Returns 0 on success, -EERROR otherwise. 165 169 * 166 170 * @set_rate_and_parent: Change the rate and the parent of this clock. The 167 171 * requested rate is specified by the second argument, which 168 - * should typically be the return of .round_rate call. The 172 + * should typically be the return of clk_round_rate() call. The 169 173 * third argument gives the parent rate which is likely helpful 170 174 * for most .set_rate_and_parent implementation. The fourth 171 175 * argument gives the parent index. This callback is optional (and ··· 240 244 void (*restore_context)(struct clk_hw *hw); 241 245 unsigned long (*recalc_rate)(struct clk_hw *hw, 242 246 unsigned long parent_rate); 243 - long (*round_rate)(struct clk_hw *hw, unsigned long rate, 244 - unsigned long *parent_rate); 245 247 int (*determine_rate)(struct clk_hw *hw, 246 248 struct clk_rate_request *req); 247 249 int (*set_parent)(struct clk_hw *hw, u8 index); ··· 673 679 * @lock: register lock 674 680 * 675 681 * Clock with an adjustable divider affecting its output frequency. Implements 676 - * .recalc_rate, .set_rate and .round_rate 682 + * .recalc_rate, .set_rate and .determine_rate 677 683 * 678 684 * @flags: 679 685 * CLK_DIVIDER_ONE_BASED - by default the divisor is the value read from the ··· 733 739 unsigned long divider_recalc_rate(struct clk_hw *hw, unsigned long parent_rate, 734 740 unsigned int val, const struct clk_div_table *table, 735 741 unsigned long flags, unsigned long width); 736 - long divider_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent, 737 - unsigned long rate, unsigned long *prate, 738 - const struct clk_div_table *table, 739 - u8 width, unsigned long flags); 740 - long divider_ro_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent, 741 - unsigned long rate, unsigned long *prate, 742 - const struct clk_div_table *table, u8 width, 743 - unsigned long flags, unsigned int val); 744 742 int divider_determine_rate(struct clk_hw *hw, struct clk_rate_request *req, 745 743 const struct clk_div_table *table, u8 width, 746 744 unsigned long flags); ··· 1112 1126 * 1113 1127 * Clock with a fixed multiplier and divider. The output frequency is the 1114 1128 * parent clock rate divided by div and multiplied by mult. 1115 - * Implements .recalc_rate, .set_rate, .round_rate and .recalc_accuracy 1129 + * Implements .recalc_rate, .set_rate, .determine_rate and .recalc_accuracy 1116 1130 * 1117 1131 * Flags: 1118 1132 * * CLK_FIXED_FACTOR_FIXED_ACCURACY - Use the value in @acc instead of the ··· 1240 1254 * @lock: register lock 1241 1255 * 1242 1256 * Clock with an adjustable multiplier affecting its output frequency. 1243 - * Implements .recalc_rate, .set_rate and .round_rate 1257 + * Implements .recalc_rate, .set_rate and .determine_rate 1244 1258 * 1245 1259 * @flags: 1246 1260 * CLK_MULTIPLIER_ZERO_BYPASS - By default, the multiplier is the value read ··· 1421 1435 { 1422 1436 dst->clk = src->clk; 1423 1437 dst->core = src->core; 1424 - } 1425 - 1426 - static inline long divider_round_rate(struct clk_hw *hw, unsigned long rate, 1427 - unsigned long *prate, 1428 - const struct clk_div_table *table, 1429 - u8 width, unsigned long flags) 1430 - { 1431 - return divider_round_rate_parent(hw, clk_hw_get_parent(hw), 1432 - rate, prate, table, width, flags); 1433 - } 1434 - 1435 - static inline long divider_ro_round_rate(struct clk_hw *hw, unsigned long rate, 1436 - unsigned long *prate, 1437 - const struct clk_div_table *table, 1438 - u8 width, unsigned long flags, 1439 - unsigned int val) 1440 - { 1441 - return divider_ro_round_rate_parent(hw, clk_hw_get_parent(hw), 1442 - rate, prate, table, width, flags, 1443 - val); 1444 1438 } 1445 1439 1446 1440 /*

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