+20 -24

Documentation/sound/alsa/ALSA-Configuration.txt

reviewed

··· 636 636 3stack-digout 3-jack in back, a HP out and a SPDIF out 637 637 5stack 5-jack in back, 2-jack in front 638 638 5stack-digout 5-jack in back, 2-jack in front, a SPDIF out 639 639 + 6stack 6-jack in back, 2-jack in front 640 640 + 6stack-digout 6-jack with a SPDIF out 639 641 w810 3-jack 640 642 z71v 3-jack (HP shared SPDIF) 641 643 asus 3-jack 642 644 uniwill 3-jack 643 645 F1734 2-jack 646 646 + test for testing/debugging purpose, almost all controls can be 647 647 + adjusted. Appearing only when compiled with 648 648 + $CONFIG_SND_DEBUG=y 644 649 645 650 CMI9880 646 651 minimal 3-jack in back ··· 1059 1054 1060 1055 The power-management is supported. 1061 1056 1057 1057 + Module snd-pxa2xx-ac97 (on arm only) 1058 1058 + ------------------------------------ 1059 1059 + 1060 1060 + Module for AC97 driver for the Intel PXA2xx chip 1061 1061 + 1062 1062 + For ARM architecture only. 1063 1063 + 1062 1064 Module snd-rme32 1063 1065 ---------------- 1064 1066 ··· 1182 1170 ------------------------------------- 1183 1171 1184 1172 Module for CS4231 sound chips found on Sparcs. 1173 1173 + 1174 1174 + Module supports up to 8 cards. 1175 1175 + 1176 1176 + Module snd-sun-dbri (on sparc only) 1177 1177 + ----------------------------------- 1178 1178 + 1179 1179 + Module for DBRI sound chips found on Sparcs. 1185 1180 1186 1181 Module supports up to 8 cards. 1187 1182 ··· 1390 1371 Module snd-vxpocket 1391 1372 ------------------- 1392 1373 1393 1393 - Module for Digigram VX-Pocket VX2 PCMCIA card. 1374 1374 + Module for Digigram VX-Pocket VX2 and 440 PCMCIA cards. 1394 1375 1395 1376 ibl - Capture IBL size. (default = 0, minimum size) 1396 1377 ··· 1399 1380 1400 1381 To activate the driver via the card manager, you'll need to set 1401 1382 up /etc/pcmcia/vxpocket.conf. See the sound/pcmcia/vx/vxpocket.c. 1402 1402 - 1403 1403 - When the driver is compiled as a module and the hotplug firmware 1404 1404 - is supported, the firmware data is loaded via hotplug automatically. 1405 1405 - Install the necessary firmware files in alsa-firmware package. 1406 1406 - When no hotplug fw loader is available, you need to load the 1407 1407 - firmware via vxloader utility in alsa-tools package. 1408 1408 - 1409 1409 - About capture IBL, see the description of snd-vx222 module. 1410 1410 - 1411 1411 - Note: the driver is build only when CONFIG_ISA is set. 1412 1412 - 1413 1413 - Module snd-vxp440 1414 1414 - ----------------- 1415 1415 - 1416 1416 - Module for Digigram VX-Pocket 440 PCMCIA card. 1417 1417 - 1418 1418 - ibl - Capture IBL size. (default = 0, minimum size) 1419 1419 - 1420 1420 - Module supports up to 8 cards. The module is compiled only when 1421 1421 - PCMCIA is supported on kernel. 1422 1422 - 1423 1423 - To activate the driver via the card manager, you'll need to set 1424 1424 - up /etc/pcmcia/vxp440.conf. See the sound/pcmcia/vx/vxp440.c. 1425 1383 1426 1384 When the driver is compiled as a module and the hotplug firmware 1427 1385 is supported, the firmware data is loaded via hotplug automatically.

+20 -17

include/sound/core.h

reviewed

··· 126 126 struct snd_monitor_file *next; 127 127 }; 128 128 129 129 - struct snd_shutdown_f_ops; /* define it later */ 129 129 + struct snd_shutdown_f_ops; /* define it later in init.c */ 130 130 131 131 /* main structure for soundcard */ 132 132 133 133 struct _snd_card { 134 134 - int number; /* number of soundcard (index to snd_cards) */ 134 134 + int number; /* number of soundcard (index to 135 135 + snd_cards) */ 135 136 136 137 char id[16]; /* id string of this card */ 137 138 char driver[16]; /* driver name */ 138 139 char shortname[32]; /* short name of this soundcard */ 139 140 char longname[80]; /* name of this soundcard */ 140 141 char mixername[80]; /* mixer name */ 141 141 - char components[80]; /* card components delimited with space */ 142 142 - 142 142 + char components[80]; /* card components delimited with 143 143 + space */ 143 144 struct module *module; /* top-level module */ 144 145 145 146 void *private_data; /* private data for soundcard */ 146 146 - void (*private_free) (snd_card_t *card); /* callback for freeing of private data */ 147 147 - 147 147 + void (*private_free) (snd_card_t *card); /* callback for freeing of 148 148 + private data */ 148 149 struct list_head devices; /* devices */ 149 150 150 151 unsigned int last_numid; /* last used numeric ID */ ··· 161 160 struct proc_dir_entry *proc_root_link; /* number link to real id */ 162 161 163 162 struct snd_monitor_file *files; /* all files associated to this card */ 164 164 - struct snd_shutdown_f_ops *s_f_ops; /* file operations in the shutdown state */ 163 163 + struct snd_shutdown_f_ops *s_f_ops; /* file operations in the shutdown 164 164 + state */ 165 165 spinlock_t files_lock; /* lock the files for this card */ 166 166 int shutdown; /* this card is going down */ 167 167 wait_queue_head_t shutdown_sleep; ··· 198 196 up(&card->power_lock); 199 197 } 200 198 201 201 - int snd_power_wait(snd_card_t *card, unsigned int power_state, struct file *file); 202 202 - 203 199 static inline unsigned int snd_power_get_state(snd_card_t *card) 204 200 { 205 201 return card->power_state; ··· 208 208 card->power_state = state; 209 209 wake_up(&card->power_sleep); 210 210 } 211 211 + 212 212 + /* init.c */ 213 213 + int snd_power_wait(snd_card_t *card, unsigned int power_state, struct file *file); 214 214 + 211 215 int snd_card_set_pm_callback(snd_card_t *card, 212 216 int (*suspend)(snd_card_t *, pm_message_t), 213 217 int (*resume)(snd_card_t *), ··· 242 238 243 239 #endif /* CONFIG_PM */ 244 240 245 245 - /* device.c */ 246 246 - 247 241 struct _snd_minor { 248 242 struct list_head list; /* list of all minors per card */ 249 243 int number; /* minor number */ 250 244 int device; /* device number */ 251 245 const char *comment; /* for /proc/asound/devices */ 252 246 struct file_operations *f_ops; /* file operations */ 253 253 - char name[0]; /* device name (keep at the end of structure) */ 247 247 + char name[0]; /* device name (keep at the end of 248 248 + structure) */ 254 249 }; 255 250 256 251 typedef struct _snd_minor snd_minor_t; ··· 290 287 void snd_memory_done(void); 291 288 int snd_memory_info_init(void); 292 289 int snd_memory_info_done(void); 293 293 - void *snd_hidden_kmalloc(size_t size, int flags); 294 294 - void *snd_hidden_kcalloc(size_t n, size_t size, int flags); 290 290 + void *snd_hidden_kmalloc(size_t size, unsigned int __nocast flags); 291 291 + void *snd_hidden_kcalloc(size_t n, size_t size, unsigned int __nocast flags); 295 292 void snd_hidden_kfree(const void *obj); 296 293 void *snd_hidden_vmalloc(unsigned long size); 297 294 void snd_hidden_vfree(void *obj); 298 298 - char *snd_hidden_kstrdup(const char *s, int flags); 295 295 + char *snd_hidden_kstrdup(const char *s, unsigned int __nocast flags); 299 296 #define kmalloc(size, flags) snd_hidden_kmalloc(size, flags) 300 297 #define kcalloc(n, size, flags) snd_hidden_kcalloc(n, size, flags) 301 298 #define kfree(obj) snd_hidden_kfree(obj) ··· 414 411 printk(fmt ,##args) 415 412 #endif 416 413 /** 417 417 - * snd_assert - run-time assersion macro 414 414 + * snd_assert - run-time assertion macro 418 415 * @expr: expression 419 416 * @args...: the action 420 417 * ··· 430 427 }\ 431 428 } while (0) 432 429 /** 433 433 - * snd_runtime_check - run-time assersion macro 430 430 + * snd_runtime_check - run-time assertion macro 434 431 * @expr: expression 435 432 * @args...: the action 436 433 *

+1 -1

include/sound/driver.h

reviewed

··· 51 51 #ifdef CONFIG_SND_DEBUG_MEMORY 52 52 #include <linux/slab.h> 53 53 #include <linux/vmalloc.h> 54 54 - void *snd_wrapper_kmalloc(size_t, int); 54 54 + void *snd_wrapper_kmalloc(size_t, unsigned int __nocast); 55 55 #undef kmalloc 56 56 void snd_wrapper_kfree(const void *); 57 57 #undef kfree

+1

include/sound/emu10k1.h

reviewed

··· 1167 1167 unsigned short extout_mask, 1168 1168 long max_cache_bytes, 1169 1169 int enable_ir, 1170 1170 + uint subsystem, 1170 1171 emu10k1_t ** remu); 1171 1172 1172 1173 int snd_emu10k1_pcm(emu10k1_t * emu, int device, snd_pcm_t ** rpcm);

+2 -2

include/sound/version.h

reviewed

··· 1 1 /* include/version.h. Generated by configure. */ 2 2 - #define CONFIG_SND_VERSION "1.0.9" 3 3 - #define CONFIG_SND_DATE " (Sun May 29 07:31:02 2005 UTC)" 2 2 + #define CONFIG_SND_VERSION "1.0.9b" 3 3 + #define CONFIG_SND_DATE " (Thu Jul 28 12:20:13 2005 UTC)"

+13 -1

sound/arm/Kconfig

reviewed

··· 20 20 select SND_PCM 21 21 select SND_AC97_CODEC 22 22 23 23 - endmenu 23 23 + config SND_PXA2XX_PCM 24 24 + tristate 25 25 + select SND_PCM 24 26 27 27 + config SND_PXA2XX_AC97 28 28 + tristate "AC97 driver for the Intel PXA2xx chip" 29 29 + depends on ARCH_PXA && SND 30 30 + select SND_PXA2XX_PCM 31 31 + select SND_AC97_CODEC 32 32 + help 33 33 + Say Y or M if you want to support any AC97 codec attached to 34 34 + the PXA2xx AC97 interface. 35 35 + 36 36 + endmenu

+7 -5

sound/arm/Makefile

reviewed

··· 3 3 # 4 4 5 5 snd-sa11xx-uda1341-objs := sa11xx-uda1341.o 6 6 - 7 7 - # Toplevel Module Dependency 8 8 - obj-$(CONFIG_SND_SA11XX_UDA1341) += snd-sa11xx-uda1341.o 9 9 - 10 10 - obj-$(CONFIG_SND_ARMAACI) += snd-aaci.o 11 6 snd-aaci-objs := aaci.o devdma.o 7 7 + snd-pxa2xx-pcm-objs := pxa2xx-pcm.o 8 8 + snd-pxa2xx-ac97-objs := pxa2xx-ac97.o 9 9 + 10 10 + obj-$(CONFIG_SND_SA11XX_UDA1341) += snd-sa11xx-uda1341.o 11 11 + obj-$(CONFIG_SND_ARMAACI) += snd-aaci.o 12 12 + obj-$(CONFIG_SND_PXA2XX_PCM) += snd-pxa2xx-pcm.o 13 13 + obj-$(CONFIG_SND_PXA2XX_AC97) += snd-pxa2xx-ac97.o

+410

sound/arm/pxa2xx-ac97.c

reviewed

··· 1 1 + /* 2 2 + * linux/sound/pxa2xx-ac97.c -- AC97 support for the Intel PXA2xx chip. 3 3 + * 4 4 + * Author: Nicolas Pitre 5 5 + * Created: Dec 02, 2004 6 6 + * Copyright: MontaVista Software Inc. 7 7 + * 8 8 + * This program is free software; you can redistribute it and/or modify 9 9 + * it under the terms of the GNU General Public License version 2 as 10 10 + * published by the Free Software Foundation. 11 11 + */ 12 12 + 13 13 + #include <linux/init.h> 14 14 + #include <linux/module.h> 15 15 + #include <linux/kernel.h> 16 16 + #include <linux/device.h> 17 17 + #include <linux/interrupt.h> 18 18 + #include <linux/wait.h> 19 19 + #include <linux/delay.h> 20 20 + 21 21 + #include <sound/driver.h> 22 22 + #include <sound/core.h> 23 23 + #include <sound/pcm.h> 24 24 + #include <sound/ac97_codec.h> 25 25 + #include <sound/initval.h> 26 26 + 27 27 + #include <asm/irq.h> 28 28 + #include <asm/semaphore.h> 29 29 + #include <asm/hardware.h> 30 30 + #include <asm/arch/pxa-regs.h> 31 31 + #include <asm/arch/audio.h> 32 32 + 33 33 + #include "pxa2xx-pcm.h" 34 34 + 35 35 + 36 36 + static DECLARE_MUTEX(car_mutex); 37 37 + static DECLARE_WAIT_QUEUE_HEAD(gsr_wq); 38 38 + static volatile long gsr_bits; 39 39 + 40 40 + static unsigned short pxa2xx_ac97_read(ac97_t *ac97, unsigned short reg) 41 41 + { 42 42 + unsigned short val = -1; 43 43 + volatile u32 *reg_addr; 44 44 + 45 45 + down(&car_mutex); 46 46 + if (CAR & CAR_CAIP) { 47 47 + printk(KERN_CRIT"%s: CAR_CAIP already set\n", __FUNCTION__); 48 48 + goto out; 49 49 + } 50 50 + 51 51 + /* set up primary or secondary codec space */ 52 52 + reg_addr = (ac97->num & 1) ? &SAC_REG_BASE : &PAC_REG_BASE; 53 53 + reg_addr += (reg >> 1); 54 54 + 55 55 + /* start read access across the ac97 link */ 56 56 + gsr_bits = 0; 57 57 + val = *reg_addr; 58 58 + if (reg == AC97_GPIO_STATUS) 59 59 + goto out; 60 60 + wait_event_timeout(gsr_wq, gsr_bits & GSR_SDONE, 1); 61 61 + if (!gsr_bits & GSR_SDONE) { 62 62 + printk(KERN_ERR "%s: read error (ac97_reg=%d GSR=%#lx)\n", 63 63 + __FUNCTION__, reg, gsr_bits); 64 64 + val = -1; 65 65 + goto out; 66 66 + } 67 67 + 68 68 + /* valid data now */ 69 69 + gsr_bits = 0; 70 70 + val = *reg_addr; 71 71 + /* but we've just started another cycle... */ 72 72 + wait_event_timeout(gsr_wq, gsr_bits & GSR_SDONE, 1); 73 73 + 74 74 + out: up(&car_mutex); 75 75 + return val; 76 76 + } 77 77 + 78 78 + static void pxa2xx_ac97_write(ac97_t *ac97, unsigned short reg, unsigned short val) 79 79 + { 80 80 + volatile u32 *reg_addr; 81 81 + 82 82 + down(&car_mutex); 83 83 + 84 84 + if (CAR & CAR_CAIP) { 85 85 + printk(KERN_CRIT "%s: CAR_CAIP already set\n", __FUNCTION__); 86 86 + goto out; 87 87 + } 88 88 + 89 89 + /* set up primary or secondary codec space */ 90 90 + reg_addr = (ac97->num & 1) ? &SAC_REG_BASE : &PAC_REG_BASE; 91 91 + reg_addr += (reg >> 1); 92 92 + gsr_bits = 0; 93 93 + *reg_addr = val; 94 94 + wait_event_timeout(gsr_wq, gsr_bits & GSR_CDONE, 1); 95 95 + if (!gsr_bits & GSR_SDONE) 96 96 + printk(KERN_ERR "%s: write error (ac97_reg=%d GSR=%#lx)\n", 97 97 + __FUNCTION__, reg, gsr_bits); 98 98 + 99 99 + out: up(&car_mutex); 100 100 + } 101 101 + 102 102 + static void pxa2xx_ac97_reset(ac97_t *ac97) 103 103 + { 104 104 + /* First, try cold reset */ 105 105 + GCR &= GCR_COLD_RST; /* clear everything but nCRST */ 106 106 + GCR &= ~GCR_COLD_RST; /* then assert nCRST */ 107 107 + 108 108 + gsr_bits = 0; 109 109 + #ifdef CONFIG_PXA27x 110 110 + /* PXA27x Developers Manual section 13.5.2.2.1 */ 111 111 + pxa_set_cken(1 << 31, 1); 112 112 + udelay(5); 113 113 + pxa_set_cken(1 << 31, 0); 114 114 + GCR = GCR_COLD_RST; 115 115 + udelay(50); 116 116 + #else 117 117 + GCR = GCR_COLD_RST; 118 118 + GCR |= GCR_CDONE_IE|GCR_SDONE_IE; 119 119 + wait_event_timeout(gsr_wq, gsr_bits & (GSR_PCR | GSR_SCR), 1); 120 120 + #endif 121 121 + 122 122 + if (!((GSR | gsr_bits) & (GSR_PCR | GSR_SCR))) { 123 123 + printk(KERN_INFO "%s: cold reset timeout (GSR=%#lx)\n", 124 124 + __FUNCTION__, gsr_bits); 125 125 + 126 126 + /* let's try warm reset */ 127 127 + gsr_bits = 0; 128 128 + #ifdef CONFIG_PXA27x 129 129 + /* warm reset broken on Bulverde, 130 130 + so manually keep AC97 reset high */ 131 131 + pxa_gpio_mode(113 | GPIO_OUT | GPIO_DFLT_HIGH); 132 132 + udelay(10); 133 133 + GCR |= GCR_WARM_RST; 134 134 + pxa_gpio_mode(113 | GPIO_ALT_FN_2_OUT); 135 135 + udelay(50); 136 136 + #else 137 137 + GCR |= GCR_WARM_RST|GCR_PRIRDY_IEN|GCR_SECRDY_IEN;; 138 138 + wait_event_timeout(gsr_wq, gsr_bits & (GSR_PCR | GSR_SCR), 1); 139 139 + #endif 140 140 + 141 141 + if (!((GSR | gsr_bits) & (GSR_PCR | GSR_SCR))) 142 142 + printk(KERN_INFO "%s: warm reset timeout (GSR=%#lx)\n", 143 143 + __FUNCTION__, gsr_bits); 144 144 + } 145 145 + 146 146 + GCR &= ~(GCR_PRIRDY_IEN|GCR_SECRDY_IEN); 147 147 + GCR |= GCR_SDONE_IE|GCR_CDONE_IE; 148 148 + } 149 149 + 150 150 + static irqreturn_t pxa2xx_ac97_irq(int irq, void *dev_id, struct pt_regs *regs) 151 151 + { 152 152 + long status; 153 153 + 154 154 + status = GSR; 155 155 + if (status) { 156 156 + GSR = status; 157 157 + gsr_bits |= status; 158 158 + wake_up(&gsr_wq); 159 159 + 160 160 + #ifdef CONFIG_PXA27x 161 161 + /* Although we don't use those we still need to clear them 162 162 + since they tend to spuriously trigger when MMC is used 163 163 + (hardware bug? go figure)... */ 164 164 + MISR = MISR_EOC; 165 165 + PISR = PISR_EOC; 166 166 + MCSR = MCSR_EOC; 167 167 + #endif 168 168 + 169 169 + return IRQ_HANDLED; 170 170 + } 171 171 + 172 172 + return IRQ_NONE; 173 173 + } 174 174 + 175 175 + static ac97_bus_ops_t pxa2xx_ac97_ops = { 176 176 + .read = pxa2xx_ac97_read, 177 177 + .write = pxa2xx_ac97_write, 178 178 + .reset = pxa2xx_ac97_reset, 179 179 + }; 180 180 + 181 181 + static pxa2xx_pcm_dma_params_t pxa2xx_ac97_pcm_out = { 182 182 + .name = "AC97 PCM out", 183 183 + .dev_addr = __PREG(PCDR), 184 184 + .drcmr = &DRCMRTXPCDR, 185 185 + .dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG | 186 186 + DCMD_BURST32 | DCMD_WIDTH4, 187 187 + }; 188 188 + 189 189 + static pxa2xx_pcm_dma_params_t pxa2xx_ac97_pcm_in = { 190 190 + .name = "AC97 PCM in", 191 191 + .dev_addr = __PREG(PCDR), 192 192 + .drcmr = &DRCMRRXPCDR, 193 193 + .dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC | 194 194 + DCMD_BURST32 | DCMD_WIDTH4, 195 195 + }; 196 196 + 197 197 + static snd_pcm_t *pxa2xx_ac97_pcm; 198 198 + static ac97_t *pxa2xx_ac97_ac97; 199 199 + 200 200 + static int pxa2xx_ac97_pcm_startup(snd_pcm_substream_t *substream) 201 201 + { 202 202 + snd_pcm_runtime_t *runtime = substream->runtime; 203 203 + pxa2xx_audio_ops_t *platform_ops; 204 204 + int r; 205 205 + 206 206 + runtime->hw.channels_min = 2; 207 207 + runtime->hw.channels_max = 2; 208 208 + 209 209 + r = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ? 210 210 + AC97_RATES_FRONT_DAC : AC97_RATES_ADC; 211 211 + runtime->hw.rates = pxa2xx_ac97_ac97->rates[r]; 212 212 + snd_pcm_limit_hw_rates(runtime); 213 213 + 214 214 + platform_ops = substream->pcm->card->dev->platform_data; 215 215 + if (platform_ops && platform_ops->startup) 216 216 + return platform_ops->startup(substream, platform_ops->priv); 217 217 + else 218 218 + return 0; 219 219 + } 220 220 + 221 221 + static void pxa2xx_ac97_pcm_shutdown(snd_pcm_substream_t *substream) 222 222 + { 223 223 + pxa2xx_audio_ops_t *platform_ops; 224 224 + 225 225 + platform_ops = substream->pcm->card->dev->platform_data; 226 226 + if (platform_ops && platform_ops->shutdown) 227 227 + platform_ops->shutdown(substream, platform_ops->priv); 228 228 + } 229 229 + 230 230 + static int pxa2xx_ac97_pcm_prepare(snd_pcm_substream_t *substream) 231 231 + { 232 232 + snd_pcm_runtime_t *runtime = substream->runtime; 233 233 + int reg = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ? 234 234 + AC97_PCM_FRONT_DAC_RATE : AC97_PCM_LR_ADC_RATE; 235 235 + return snd_ac97_set_rate(pxa2xx_ac97_ac97, reg, runtime->rate); 236 236 + } 237 237 + 238 238 + static pxa2xx_pcm_client_t pxa2xx_ac97_pcm_client = { 239 239 + .playback_params = &pxa2xx_ac97_pcm_out, 240 240 + .capture_params = &pxa2xx_ac97_pcm_in, 241 241 + .startup = pxa2xx_ac97_pcm_startup, 242 242 + .shutdown = pxa2xx_ac97_pcm_shutdown, 243 243 + .prepare = pxa2xx_ac97_pcm_prepare, 244 244 + }; 245 245 + 246 246 + #ifdef CONFIG_PM 247 247 + 248 248 + static int pxa2xx_ac97_do_suspend(snd_card_t *card, unsigned int state) 249 249 + { 250 250 + if (card->power_state != SNDRV_CTL_POWER_D3cold) { 251 251 + pxa2xx_audio_ops_t *platform_ops = card->dev->platform_data; 252 252 + snd_pcm_suspend_all(pxa2xx_ac97_pcm); 253 253 + snd_ac97_suspend(pxa2xx_ac97_ac97); 254 254 + snd_power_change_state(card, SNDRV_CTL_POWER_D3cold); 255 255 + if (platform_ops && platform_ops->suspend) 256 256 + platform_ops->suspend(platform_ops->priv); 257 257 + GCR |= GCR_ACLINK_OFF; 258 258 + pxa_set_cken(CKEN2_AC97, 0); 259 259 + } 260 260 + 261 261 + return 0; 262 262 + } 263 263 + 264 264 + static int pxa2xx_ac97_do_resume(snd_card_t *card, unsigned int state) 265 265 + { 266 266 + if (card->power_state != SNDRV_CTL_POWER_D0) { 267 267 + pxa2xx_audio_ops_t *platform_ops = card->dev->platform_data; 268 268 + pxa_set_cken(CKEN2_AC97, 1); 269 269 + if (platform_ops && platform_ops->resume) 270 270 + platform_ops->resume(platform_ops->priv); 271 271 + snd_ac97_resume(pxa2xx_ac97_ac97); 272 272 + snd_power_change_state(card, SNDRV_CTL_POWER_D0); 273 273 + } 274 274 + 275 275 + return 0; 276 276 + } 277 277 + 278 278 + static int pxa2xx_ac97_suspend(struct device *_dev, u32 state, u32 level) 279 279 + { 280 280 + snd_card_t *card = dev_get_drvdata(_dev); 281 281 + int ret = 0; 282 282 + 283 283 + if (card && level == SUSPEND_DISABLE) 284 284 + ret = pxa2xx_ac97_do_suspend(card, SNDRV_CTL_POWER_D3cold); 285 285 + 286 286 + return ret; 287 287 + } 288 288 + 289 289 + static int pxa2xx_ac97_resume(struct device *_dev, u32 level) 290 290 + { 291 291 + snd_card_t *card = dev_get_drvdata(_dev); 292 292 + int ret = 0; 293 293 + 294 294 + if (card && level == RESUME_ENABLE) 295 295 + ret = pxa2xx_ac97_do_resume(card, SNDRV_CTL_POWER_D0); 296 296 + 297 297 + return ret; 298 298 + } 299 299 + 300 300 + #else 301 301 + #define pxa2xx_ac97_suspend NULL 302 302 + #define pxa2xx_ac97_resume NULL 303 303 + #endif 304 304 + 305 305 + static int pxa2xx_ac97_probe(struct device *dev) 306 306 + { 307 307 + snd_card_t *card; 308 308 + ac97_bus_t *ac97_bus; 309 309 + ac97_template_t ac97_template; 310 310 + int ret; 311 311 + 312 312 + ret = -ENOMEM; 313 313 + card = snd_card_new(SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1, 314 314 + THIS_MODULE, 0); 315 315 + if (!card) 316 316 + goto err; 317 317 + 318 318 + card->dev = dev; 319 319 + strncpy(card->driver, dev->driver->name, sizeof(card->driver)); 320 320 + 321 321 + ret = pxa2xx_pcm_new(card, &pxa2xx_ac97_pcm_client, &pxa2xx_ac97_pcm); 322 322 + if (ret) 323 323 + goto err; 324 324 + 325 325 + ret = request_irq(IRQ_AC97, pxa2xx_ac97_irq, 0, "AC97", NULL); 326 326 + if (ret < 0) 327 327 + goto err; 328 328 + 329 329 + pxa_gpio_mode(GPIO31_SYNC_AC97_MD); 330 330 + pxa_gpio_mode(GPIO30_SDATA_OUT_AC97_MD); 331 331 + pxa_gpio_mode(GPIO28_BITCLK_AC97_MD); 332 332 + pxa_gpio_mode(GPIO29_SDATA_IN_AC97_MD); 333 333 + #ifdef CONFIG_PXA27x 334 334 + /* Use GPIO 113 as AC97 Reset on Bulverde */ 335 335 + pxa_gpio_mode(113 | GPIO_ALT_FN_2_OUT); 336 336 + #endif 337 337 + pxa_set_cken(CKEN2_AC97, 1); 338 338 + 339 339 + ret = snd_ac97_bus(card, 0, &pxa2xx_ac97_ops, NULL, &ac97_bus); 340 340 + if (ret) 341 341 + goto err; 342 342 + memset(&ac97_template, 0, sizeof(ac97_template)); 343 343 + ret = snd_ac97_mixer(ac97_bus, &ac97_template, &pxa2xx_ac97_ac97); 344 344 + if (ret) 345 345 + goto err; 346 346 + 347 347 + snprintf(card->shortname, sizeof(card->shortname), 348 348 + "%s", snd_ac97_get_short_name(pxa2xx_ac97_ac97)); 349 349 + snprintf(card->longname, sizeof(card->longname), 350 350 + "%s (%s)", dev->driver->name, card->mixername); 351 351 + 352 352 + snd_card_set_pm_callback(card, pxa2xx_ac97_do_suspend, 353 353 + pxa2xx_ac97_do_resume, NULL); 354 354 + ret = snd_card_register(card); 355 355 + if (ret == 0) { 356 356 + dev_set_drvdata(dev, card); 357 357 + return 0; 358 358 + } 359 359 + 360 360 + err: 361 361 + if (card) 362 362 + snd_card_free(card); 363 363 + if (CKEN & CKEN2_AC97) { 364 364 + GCR |= GCR_ACLINK_OFF; 365 365 + free_irq(IRQ_AC97, NULL); 366 366 + pxa_set_cken(CKEN2_AC97, 0); 367 367 + } 368 368 + return ret; 369 369 + } 370 370 + 371 371 + static int pxa2xx_ac97_remove(struct device *dev) 372 372 + { 373 373 + snd_card_t *card = dev_get_drvdata(dev); 374 374 + 375 375 + if (card) { 376 376 + snd_card_free(card); 377 377 + dev_set_drvdata(dev, NULL); 378 378 + GCR |= GCR_ACLINK_OFF; 379 379 + free_irq(IRQ_AC97, NULL); 380 380 + pxa_set_cken(CKEN2_AC97, 0); 381 381 + } 382 382 + 383 383 + return 0; 384 384 + } 385 385 + 386 386 + static struct device_driver pxa2xx_ac97_driver = { 387 387 + .name = "pxa2xx-ac97", 388 388 + .bus = &platform_bus_type, 389 389 + .probe = pxa2xx_ac97_probe, 390 390 + .remove = pxa2xx_ac97_remove, 391 391 + .suspend = pxa2xx_ac97_suspend, 392 392 + .resume = pxa2xx_ac97_resume, 393 393 + }; 394 394 + 395 395 + static int __init pxa2xx_ac97_init(void) 396 396 + { 397 397 + return driver_register(&pxa2xx_ac97_driver); 398 398 + } 399 399 + 400 400 + static void __exit pxa2xx_ac97_exit(void) 401 401 + { 402 402 + driver_unregister(&pxa2xx_ac97_driver); 403 403 + } 404 404 + 405 405 + module_init(pxa2xx_ac97_init); 406 406 + module_exit(pxa2xx_ac97_exit); 407 407 + 408 408 + MODULE_AUTHOR("Nicolas Pitre"); 409 409 + MODULE_DESCRIPTION("AC97 driver for the Intel PXA2xx chip"); 410 410 + MODULE_LICENSE("GPL");

+367

sound/arm/pxa2xx-pcm.c

reviewed

··· 1 1 + /* 2 2 + * linux/sound/arm/pxa2xx-pcm.c -- ALSA PCM interface for the Intel PXA2xx chip 3 3 + * 4 4 + * Author: Nicolas Pitre 5 5 + * Created: Nov 30, 2004 6 6 + * Copyright: (C) 2004 MontaVista Software, Inc. 7 7 + * 8 8 + * This program is free software; you can redistribute it and/or modify 9 9 + * it under the terms of the GNU General Public License version 2 as 10 10 + * published by the Free Software Foundation. 11 11 + */ 12 12 + 13 13 + #include <linux/module.h> 14 14 + #include <linux/init.h> 15 15 + #include <linux/device.h> 16 16 + #include <linux/slab.h> 17 17 + #include <linux/dma-mapping.h> 18 18 + 19 19 + #include <sound/driver.h> 20 20 + #include <sound/core.h> 21 21 + #include <sound/pcm.h> 22 22 + #include <sound/pcm_params.h> 23 23 + 24 24 + #include <asm/dma.h> 25 25 + #include <asm/hardware.h> 26 26 + #include <asm/arch/pxa-regs.h> 27 27 + 28 28 + #include "pxa2xx-pcm.h" 29 29 + 30 30 + 31 31 + static const snd_pcm_hardware_t pxa2xx_pcm_hardware = { 32 32 + .info = SNDRV_PCM_INFO_MMAP | 33 33 + SNDRV_PCM_INFO_MMAP_VALID | 34 34 + SNDRV_PCM_INFO_INTERLEAVED | 35 35 + SNDRV_PCM_INFO_PAUSE, 36 36 + .formats = SNDRV_PCM_FMTBIT_S16_LE, 37 37 + .period_bytes_min = 32, 38 38 + .period_bytes_max = 8192 - 32, 39 39 + .periods_min = 1, 40 40 + .periods_max = PAGE_SIZE/sizeof(pxa_dma_desc), 41 41 + .buffer_bytes_max = 128 * 1024, 42 42 + .fifo_size = 32, 43 43 + }; 44 44 + 45 45 + struct pxa2xx_runtime_data { 46 46 + int dma_ch; 47 47 + pxa2xx_pcm_dma_params_t *params; 48 48 + pxa_dma_desc *dma_desc_array; 49 49 + dma_addr_t dma_desc_array_phys; 50 50 + }; 51 51 + 52 52 + static int pxa2xx_pcm_hw_params(snd_pcm_substream_t *substream, 53 53 + snd_pcm_hw_params_t *params) 54 54 + { 55 55 + snd_pcm_runtime_t *runtime = substream->runtime; 56 56 + struct pxa2xx_runtime_data *rtd = runtime->private_data; 57 57 + size_t totsize = params_buffer_bytes(params); 58 58 + size_t period = params_period_bytes(params); 59 59 + pxa_dma_desc *dma_desc; 60 60 + dma_addr_t dma_buff_phys, next_desc_phys; 61 61 + 62 62 + snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer); 63 63 + runtime->dma_bytes = totsize; 64 64 + 65 65 + dma_desc = rtd->dma_desc_array; 66 66 + next_desc_phys = rtd->dma_desc_array_phys; 67 67 + dma_buff_phys = runtime->dma_addr; 68 68 + do { 69 69 + next_desc_phys += sizeof(pxa_dma_desc); 70 70 + dma_desc->ddadr = next_desc_phys; 71 71 + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 72 72 + dma_desc->dsadr = dma_buff_phys; 73 73 + dma_desc->dtadr = rtd->params->dev_addr; 74 74 + } else { 75 75 + dma_desc->dsadr = rtd->params->dev_addr; 76 76 + dma_desc->dtadr = dma_buff_phys; 77 77 + } 78 78 + if (period > totsize) 79 79 + period = totsize; 80 80 + dma_desc->dcmd = rtd->params->dcmd | period | DCMD_ENDIRQEN; 81 81 + dma_desc++; 82 82 + dma_buff_phys += period; 83 83 + } while (totsize -= period); 84 84 + dma_desc[-1].ddadr = rtd->dma_desc_array_phys; 85 85 + 86 86 + return 0; 87 87 + } 88 88 + 89 89 + static int pxa2xx_pcm_hw_free(snd_pcm_substream_t *substream) 90 90 + { 91 91 + struct pxa2xx_runtime_data *rtd = substream->runtime->private_data; 92 92 + 93 93 + *rtd->params->drcmr = 0; 94 94 + snd_pcm_set_runtime_buffer(substream, NULL); 95 95 + return 0; 96 96 + } 97 97 + 98 98 + static int pxa2xx_pcm_prepare(snd_pcm_substream_t *substream) 99 99 + { 100 100 + pxa2xx_pcm_client_t *client = substream->private_data; 101 101 + snd_pcm_runtime_t *runtime = substream->runtime; 102 102 + struct pxa2xx_runtime_data *rtd = runtime->private_data; 103 103 + 104 104 + DCSR(rtd->dma_ch) &= ~DCSR_RUN; 105 105 + DCSR(rtd->dma_ch) = 0; 106 106 + DCMD(rtd->dma_ch) = 0; 107 107 + *rtd->params->drcmr = rtd->dma_ch | DRCMR_MAPVLD; 108 108 + 109 109 + return client->prepare(substream); 110 110 + } 111 111 + 112 112 + static int pxa2xx_pcm_trigger(snd_pcm_substream_t *substream, int cmd) 113 113 + { 114 114 + struct pxa2xx_runtime_data *rtd = substream->runtime->private_data; 115 115 + int ret = 0; 116 116 + 117 117 + switch (cmd) { 118 118 + case SNDRV_PCM_TRIGGER_START: 119 119 + DDADR(rtd->dma_ch) = rtd->dma_desc_array_phys; 120 120 + DCSR(rtd->dma_ch) = DCSR_RUN; 121 121 + break; 122 122 + 123 123 + case SNDRV_PCM_TRIGGER_STOP: 124 124 + case SNDRV_PCM_TRIGGER_SUSPEND: 125 125 + case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 126 126 + DCSR(rtd->dma_ch) &= ~DCSR_RUN; 127 127 + break; 128 128 + 129 129 + case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 130 130 + DCSR(rtd->dma_ch) |= DCSR_RUN; 131 131 + break; 132 132 + 133 133 + default: 134 134 + ret = -EINVAL; 135 135 + } 136 136 + 137 137 + return ret; 138 138 + } 139 139 + 140 140 + static void pxa2xx_pcm_dma_irq(int dma_ch, void *dev_id, struct pt_regs *regs) 141 141 + { 142 142 + snd_pcm_substream_t *substream = dev_id; 143 143 + struct pxa2xx_runtime_data *rtd = substream->runtime->private_data; 144 144 + int dcsr; 145 145 + 146 146 + dcsr = DCSR(dma_ch); 147 147 + DCSR(dma_ch) = dcsr & ~DCSR_STOPIRQEN; 148 148 + 149 149 + if (dcsr & DCSR_ENDINTR) { 150 150 + snd_pcm_period_elapsed(substream); 151 151 + } else { 152 152 + printk( KERN_ERR "%s: DMA error on channel %d (DCSR=%#x)\n", 153 153 + rtd->params->name, dma_ch, dcsr ); 154 154 + snd_pcm_stop(substream, SNDRV_PCM_STATE_XRUN); 155 155 + } 156 156 + } 157 157 + 158 158 + static snd_pcm_uframes_t pxa2xx_pcm_pointer(snd_pcm_substream_t *substream) 159 159 + { 160 160 + snd_pcm_runtime_t *runtime = substream->runtime; 161 161 + struct pxa2xx_runtime_data *rtd = runtime->private_data; 162 162 + dma_addr_t ptr = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ? 163 163 + DSADR(rtd->dma_ch) : DTADR(rtd->dma_ch); 164 164 + snd_pcm_uframes_t x = bytes_to_frames(runtime, ptr - runtime->dma_addr); 165 165 + if (x == runtime->buffer_size) 166 166 + x = 0; 167 167 + return x; 168 168 + } 169 169 + 170 170 + static int 171 171 + pxa2xx_pcm_hw_rule_mult32(snd_pcm_hw_params_t *params, snd_pcm_hw_rule_t *rule) 172 172 + { 173 173 + snd_interval_t *i = hw_param_interval(params, rule->var); 174 174 + int changed = 0; 175 175 + 176 176 + if (i->min & 31) { 177 177 + i->min = (i->min & ~31) + 32; 178 178 + i->openmin = 0; 179 179 + changed = 1; 180 180 + } 181 181 + 182 182 + if (i->max & 31) { 183 183 + i->max &= ~31; 184 184 + i->openmax = 0; 185 185 + changed = 1; 186 186 + } 187 187 + 188 188 + return changed; 189 189 + } 190 190 + 191 191 + static int pxa2xx_pcm_open(snd_pcm_substream_t *substream) 192 192 + { 193 193 + pxa2xx_pcm_client_t *client = substream->private_data; 194 194 + snd_pcm_runtime_t *runtime = substream->runtime; 195 195 + struct pxa2xx_runtime_data *rtd; 196 196 + int ret; 197 197 + 198 198 + runtime->hw = pxa2xx_pcm_hardware; 199 199 + 200 200 + /* 201 201 + * For mysterious reasons (and despite what the manual says) 202 202 + * playback samples are lost if the DMA count is not a multiple 203 203 + * of the DMA burst size. Let's add a rule to enforce that. 204 204 + */ 205 205 + ret = snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 206 206 + pxa2xx_pcm_hw_rule_mult32, NULL, 207 207 + SNDRV_PCM_HW_PARAM_PERIOD_BYTES, -1); 208 208 + if (ret) 209 209 + goto out; 210 210 + ret = snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES, 211 211 + pxa2xx_pcm_hw_rule_mult32, NULL, 212 212 + SNDRV_PCM_HW_PARAM_BUFFER_BYTES, -1); 213 213 + if (ret) 214 214 + goto out; 215 215 + 216 216 + ret = -ENOMEM; 217 217 + rtd = kmalloc(sizeof(*rtd), GFP_KERNEL); 218 218 + if (!rtd) 219 219 + goto out; 220 220 + rtd->dma_desc_array = 221 221 + dma_alloc_writecombine(substream->pcm->card->dev, PAGE_SIZE, 222 222 + &rtd->dma_desc_array_phys, GFP_KERNEL); 223 223 + if (!rtd->dma_desc_array) 224 224 + goto err1; 225 225 + 226 226 + rtd->params = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ? 227 227 + client->playback_params : client->capture_params; 228 228 + ret = pxa_request_dma(rtd->params->name, DMA_PRIO_LOW, 229 229 + pxa2xx_pcm_dma_irq, substream); 230 230 + if (ret < 0) 231 231 + goto err2; 232 232 + rtd->dma_ch = ret; 233 233 + 234 234 + runtime->private_data = rtd; 235 235 + ret = client->startup(substream); 236 236 + if (!ret) 237 237 + goto out; 238 238 + 239 239 + pxa_free_dma(rtd->dma_ch); 240 240 + err2: 241 241 + dma_free_writecombine(substream->pcm->card->dev, PAGE_SIZE, 242 242 + rtd->dma_desc_array, rtd->dma_desc_array_phys); 243 243 + err1: 244 244 + kfree(rtd); 245 245 + out: 246 246 + return ret; 247 247 + } 248 248 + 249 249 + static int pxa2xx_pcm_close(snd_pcm_substream_t *substream) 250 250 + { 251 251 + pxa2xx_pcm_client_t *client = substream->private_data; 252 252 + struct pxa2xx_runtime_data *rtd = substream->runtime->private_data; 253 253 + 254 254 + pxa_free_dma(rtd->dma_ch); 255 255 + client->shutdown(substream); 256 256 + dma_free_writecombine(substream->pcm->card->dev, PAGE_SIZE, 257 257 + rtd->dma_desc_array, rtd->dma_desc_array_phys); 258 258 + kfree(rtd); 259 259 + return 0; 260 260 + } 261 261 + 262 262 + static int 263 263 + pxa2xx_pcm_mmap(snd_pcm_substream_t *substream, struct vm_area_struct *vma) 264 264 + { 265 265 + snd_pcm_runtime_t *runtime = substream->runtime; 266 266 + return dma_mmap_writecombine(substream->pcm->card->dev, vma, 267 267 + runtime->dma_area, 268 268 + runtime->dma_addr, 269 269 + runtime->dma_bytes); 270 270 + } 271 271 + 272 272 + static snd_pcm_ops_t pxa2xx_pcm_ops = { 273 273 + .open = pxa2xx_pcm_open, 274 274 + .close = pxa2xx_pcm_close, 275 275 + .ioctl = snd_pcm_lib_ioctl, 276 276 + .hw_params = pxa2xx_pcm_hw_params, 277 277 + .hw_free = pxa2xx_pcm_hw_free, 278 278 + .prepare = pxa2xx_pcm_prepare, 279 279 + .trigger = pxa2xx_pcm_trigger, 280 280 + .pointer = pxa2xx_pcm_pointer, 281 281 + .mmap = pxa2xx_pcm_mmap, 282 282 + }; 283 283 + 284 284 + static int pxa2xx_pcm_preallocate_dma_buffer(snd_pcm_t *pcm, int stream) 285 285 + { 286 286 + snd_pcm_substream_t *substream = pcm->streams[stream].substream; 287 287 + struct snd_dma_buffer *buf = &substream->dma_buffer; 288 288 + size_t size = pxa2xx_pcm_hardware.buffer_bytes_max; 289 289 + buf->dev.type = SNDRV_DMA_TYPE_DEV; 290 290 + buf->dev.dev = pcm->card->dev; 291 291 + buf->private_data = NULL; 292 292 + buf->area = dma_alloc_writecombine(pcm->card->dev, size, 293 293 + &buf->addr, GFP_KERNEL); 294 294 + if (!buf->area) 295 295 + return -ENOMEM; 296 296 + buf->bytes = size; 297 297 + return 0; 298 298 + } 299 299 + 300 300 + static void pxa2xx_pcm_free_dma_buffers(snd_pcm_t *pcm) 301 301 + { 302 302 + snd_pcm_substream_t *substream; 303 303 + struct snd_dma_buffer *buf; 304 304 + int stream; 305 305 + 306 306 + for (stream = 0; stream < 2; stream++) { 307 307 + substream = pcm->streams[stream].substream; 308 308 + if (!substream) 309 309 + continue; 310 310 + buf = &substream->dma_buffer; 311 311 + if (!buf->area) 312 312 + continue; 313 313 + dma_free_writecombine(pcm->card->dev, buf->bytes, 314 314 + buf->area, buf->addr); 315 315 + buf->area = NULL; 316 316 + } 317 317 + } 318 318 + 319 319 + static u64 pxa2xx_pcm_dmamask = 0xffffffff; 320 320 + 321 321 + int pxa2xx_pcm_new(snd_card_t *card, pxa2xx_pcm_client_t *client, snd_pcm_t **rpcm) 322 322 + { 323 323 + snd_pcm_t *pcm; 324 324 + int play = client->playback_params ? 1 : 0; 325 325 + int capt = client->capture_params ? 1 : 0; 326 326 + int ret; 327 327 + 328 328 + ret = snd_pcm_new(card, "PXA2xx-PCM", 0, play, capt, &pcm); 329 329 + if (ret) 330 330 + goto out; 331 331 + 332 332 + pcm->private_data = client; 333 333 + pcm->private_free = pxa2xx_pcm_free_dma_buffers; 334 334 + 335 335 + if (!card->dev->dma_mask) 336 336 + card->dev->dma_mask = &pxa2xx_pcm_dmamask; 337 337 + if (!card->dev->coherent_dma_mask) 338 338 + card->dev->coherent_dma_mask = 0xffffffff; 339 339 + 340 340 + if (play) { 341 341 + int stream = SNDRV_PCM_STREAM_PLAYBACK; 342 342 + snd_pcm_set_ops(pcm, stream, &pxa2xx_pcm_ops); 343 343 + ret = pxa2xx_pcm_preallocate_dma_buffer(pcm, stream); 344 344 + if (ret) 345 345 + goto out; 346 346 + } 347 347 + if (capt) { 348 348 + int stream = SNDRV_PCM_STREAM_CAPTURE; 349 349 + snd_pcm_set_ops(pcm, stream, &pxa2xx_pcm_ops); 350 350 + ret = pxa2xx_pcm_preallocate_dma_buffer(pcm, stream); 351 351 + if (ret) 352 352 + goto out; 353 353 + } 354 354 + 355 355 + if (rpcm) 356 356 + *rpcm = pcm; 357 357 + ret = 0; 358 358 + 359 359 + out: 360 360 + return ret; 361 361 + } 362 362 + 363 363 + EXPORT_SYMBOL(pxa2xx_pcm_new); 364 364 + 365 365 + MODULE_AUTHOR("Nicolas Pitre"); 366 366 + MODULE_DESCRIPTION("Intel PXA2xx PCM DMA module"); 367 367 + MODULE_LICENSE("GPL");

+29

sound/arm/pxa2xx-pcm.h

reviewed

··· 1 1 + /* 2 2 + * linux/sound/arm/pxa2xx-pcm.h -- ALSA PCM interface for the Intel PXA2xx chip 3 3 + * 4 4 + * Author: Nicolas Pitre 5 5 + * Created: Nov 30, 2004 6 6 + * Copyright: MontaVista Software, Inc. 7 7 + * 8 8 + * This program is free software; you can redistribute it and/or modify 9 9 + * it under the terms of the GNU General Public License version 2 as 10 10 + * published by the Free Software Foundation. 11 11 + */ 12 12 + 13 13 + typedef struct { 14 14 + char *name; /* stream identifier */ 15 15 + u32 dcmd; /* DMA descriptor dcmd field */ 16 16 + volatile u32 *drcmr; /* the DMA request channel to use */ 17 17 + u32 dev_addr; /* device physical address for DMA */ 18 18 + } pxa2xx_pcm_dma_params_t; 19 19 + 20 20 + typedef struct { 21 21 + pxa2xx_pcm_dma_params_t *playback_params; 22 22 + pxa2xx_pcm_dma_params_t *capture_params; 23 23 + int (*startup)(snd_pcm_substream_t *); 24 24 + void (*shutdown)(snd_pcm_substream_t *); 25 25 + int (*prepare)(snd_pcm_substream_t *); 26 26 + } pxa2xx_pcm_client_t; 27 27 + 28 28 + extern int pxa2xx_pcm_new(snd_card_t *, pxa2xx_pcm_client_t *, snd_pcm_t **); 29 29 +

+9 -6

sound/core/device.c

reviewed

··· 28 28 /** 29 29 * snd_device_new - create an ALSA device component 30 30 * @card: the card instance 31 31 - * @type: the device type, SNDRV_DEV_TYPE_XXX 31 31 + * @type: the device type, SNDRV_DEV_XXX 32 32 * @device_data: the data pointer of this device 33 33 * @ops: the operator table 34 34 * ··· 46 46 { 47 47 snd_device_t *dev; 48 48 49 49 - snd_assert(card != NULL && device_data != NULL && ops != NULL, return -ENXIO); 49 49 + snd_assert(card != NULL, return -ENXIO); 50 50 + snd_assert(device_data != NULL, return -ENXIO); 51 51 + snd_assert(ops != NULL, return -ENXIO); 50 52 dev = kcalloc(1, sizeof(*dev), GFP_KERNEL); 51 53 if (dev == NULL) 52 54 return -ENOMEM; ··· 104 102 } 105 103 106 104 /** 107 107 - * snd_device_free - disconnect the device 105 105 + * snd_device_disconnect - disconnect the device 108 106 * @card: the card instance 109 107 * @device_data: the data pointer to disconnect 110 108 * ··· 120 118 { 121 119 struct list_head *list; 122 120 snd_device_t *dev; 123 123 - 121 121 + 124 122 snd_assert(card != NULL, return -ENXIO); 125 123 snd_assert(device_data != NULL, return -ENXIO); 126 124 list_for_each(list, &card->devices) { ··· 156 154 struct list_head *list; 157 155 snd_device_t *dev; 158 156 int err; 159 159 - 160 160 - snd_assert(card != NULL && device_data != NULL, return -ENXIO); 157 157 + 158 158 + snd_assert(card != NULL, return -ENXIO); 159 159 + snd_assert(device_data != NULL, return -ENXIO); 161 160 list_for_each(list, &card->devices) { 162 161 dev = snd_device(list); 163 162 if (dev->device_data != device_data)

+3 -2

sound/core/info.c

reviewed

··· 702 702 } 703 703 704 704 /** 705 705 - * snd_info_get_line - parse a string token 705 705 + * snd_info_get_str - parse a string token 706 706 * @dest: the buffer to store the string token 707 707 * @src: the original string 708 708 * @len: the max. length of token - 1 ··· 939 939 { 940 940 struct proc_dir_entry *root; 941 941 942 942 - snd_assert(entry != NULL && entry->p != NULL, return -ENXIO); 942 942 + snd_assert(entry != NULL, return -ENXIO); 943 943 + snd_assert(entry->p != NULL, return -ENXIO); 943 944 root = entry->parent == NULL ? snd_proc_root : entry->parent->p; 944 945 snd_assert(root, return -ENXIO); 945 946 down(&info_mutex);

+2 -1

sound/core/memalloc.c

reviewed

··· 105 105 */ 106 106 107 107 static void *snd_dma_hack_alloc_coherent(struct device *dev, size_t size, 108 108 - dma_addr_t *dma_handle, int flags) 108 108 + dma_addr_t *dma_handle, 109 109 + unsigned int __nocast flags) 109 110 { 110 111 void *ret; 111 112 u64 dma_mask, coherent_dma_mask;

+4 -4

sound/core/memory.c

reviewed

··· 89 89 } 90 90 } 91 91 92 92 - static void *__snd_kmalloc(size_t size, int flags, void *caller) 92 92 + static void *__snd_kmalloc(size_t size, unsigned int __nocast flags, void *caller) 93 93 { 94 94 unsigned long cpu_flags; 95 95 struct snd_alloc_track *t; ··· 111 111 } 112 112 113 113 #define _snd_kmalloc(size, flags) __snd_kmalloc((size), (flags), __builtin_return_address(0)); 114 114 - void *snd_hidden_kmalloc(size_t size, int flags) 114 114 + void *snd_hidden_kmalloc(size_t size, unsigned int __nocast flags) 115 115 { 116 116 return _snd_kmalloc(size, flags); 117 117 } 118 118 119 119 - void *snd_hidden_kcalloc(size_t n, size_t size, int flags) 119 119 + void *snd_hidden_kcalloc(size_t n, size_t size, unsigned int __nocast flags) 120 120 { 121 121 void *ret = NULL; 122 122 if (n != 0 && size > INT_MAX / n) ··· 184 184 snd_wrapper_vfree(obj); 185 185 } 186 186 187 187 - char *snd_hidden_kstrdup(const char *s, int flags) 187 187 + char *snd_hidden_kstrdup(const char *s, unsigned int __nocast flags) 188 188 { 189 189 int len; 190 190 char *buf;

+1 -1

sound/core/seq/Makefile

reviewed

··· 38 38 obj-$(call sequencer,$(CONFIG_SND_RAWMIDI)) += snd-seq-midi.o snd-seq-midi-event.o 39 39 obj-$(call sequencer,$(CONFIG_SND_OPL3_LIB)) += snd-seq-midi-event.o snd-seq-midi-emul.o snd-seq-instr.o 40 40 obj-$(call sequencer,$(CONFIG_SND_OPL4_LIB)) += snd-seq-midi-event.o snd-seq-midi-emul.o snd-seq-instr.o 41 41 - obj-$(call sequencer,$(CONFIG_SND_GUS_SYNTH)) += snd-seq-instr.o 41 41 + obj-$(call sequencer,$(CONFIG_SND_GUS_SYNTH)) += snd-seq-midi-emul.o snd-seq-instr.o 42 42 obj-$(call sequencer,$(CONFIG_SND_SBAWE)) += snd-seq-midi-emul.o snd-seq-virmidi.o 43 43 obj-$(call sequencer,$(CONFIG_SND_EMU10K1)) += snd-seq-midi-emul.o snd-seq-virmidi.o 44 44 obj-$(call sequencer,$(CONFIG_SND_TRIDENT)) += snd-seq-midi-emul.o snd-seq-instr.o

+2 -1

sound/core/seq/instr/ainstr_gf1.c

reviewed

··· 50 50 { 51 51 gf1_wave_t *wp, *prev; 52 52 gf1_xwave_t xp; 53 53 - int err, gfp_mask; 53 53 + int err; 54 54 + unsigned int gfp_mask; 54 55 unsigned int real_size; 55 56 56 57 gfp_mask = atomic ? GFP_ATOMIC : GFP_KERNEL;

+5 -3

sound/core/seq/instr/ainstr_iw.c

reviewed

··· 58 58 iwffff_xenv_t *ex, 59 59 char __user **data, 60 60 long *len, 61 61 - int gfp_mask) 61 61 + unsigned int __nocast gfp_mask) 62 62 { 63 63 __u32 stype; 64 64 iwffff_env_record_t *rp, *rp_last; ··· 128 128 { 129 129 iwffff_wave_t *wp, *prev; 130 130 iwffff_xwave_t xp; 131 131 - int err, gfp_mask; 131 131 + int err; 132 132 + unsigned int gfp_mask; 132 133 unsigned int real_size; 133 134 134 135 gfp_mask = atomic ? GFP_ATOMIC : GFP_KERNEL; ··· 235 234 iwffff_xinstrument_t ix; 236 235 iwffff_layer_t *lp, *prev_lp; 237 236 iwffff_xlayer_t lx; 238 238 - int err, gfp_mask; 237 237 + int err; 238 238 + unsigned int gfp_mask; 239 239 240 240 if (cmd != SNDRV_SEQ_INSTR_PUT_CMD_CREATE) 241 241 return -EINVAL;

+6 -10

sound/core/seq/seq_midi.c

reviewed

··· 134 134 seq_midisynth_t *msynth = (seq_midisynth_t *) private_data; 135 135 unsigned char msg[10]; /* buffer for constructing midi messages */ 136 136 snd_rawmidi_substream_t *substream; 137 137 - int res; 137 137 + int len; 138 138 139 139 snd_assert(msynth != NULL, return -EINVAL); 140 140 substream = msynth->output_rfile.output; ··· 146 146 snd_printd("seq_midi: invalid sysex event flags = 0x%x\n", ev->flags); 147 147 return 0; 148 148 } 149 149 - res = snd_seq_dump_var_event(ev, (snd_seq_dump_func_t)dump_midi, substream); 149 149 + snd_seq_dump_var_event(ev, (snd_seq_dump_func_t)dump_midi, substream); 150 150 snd_midi_event_reset_decode(msynth->parser); 151 151 - if (res < 0) 152 152 - return res; 153 151 } else { 154 152 if (msynth->parser == NULL) 155 153 return -EIO; 156 156 - res = snd_midi_event_decode(msynth->parser, msg, sizeof(msg), ev); 157 157 - if (res < 0) 158 158 - return res; 159 159 - if ((res = dump_midi(substream, msg, res)) < 0) { 154 154 + len = snd_midi_event_decode(msynth->parser, msg, sizeof(msg), ev); 155 155 + if (len < 0) 156 156 + return 0; 157 157 + if (dump_midi(substream, msg, len) < 0) 160 158 snd_midi_event_reset_decode(msynth->parser); 161 161 - return res; 162 162 - } 163 159 } 164 160 return 0; 165 161 }

+1 -1

sound/core/wrappers.c

reviewed

··· 27 27 #include <linux/fs.h> 28 28 29 29 #ifdef CONFIG_SND_DEBUG_MEMORY 30 30 - void *snd_wrapper_kmalloc(size_t size, int flags) 30 30 + void *snd_wrapper_kmalloc(size_t size, unsigned int __nocast flags) 31 31 { 32 32 return kmalloc(size, flags); 33 33 }

+17 -27

sound/drivers/vx/vx_uer.c

reviewed

··· 162 162 163 163 static int vx_calc_clock_from_freq(vx_core_t *chip, int freq) 164 164 { 165 165 - #define XX_FECH48000 0x0000004B 166 166 - #define XX_FECH32000 0x00000171 167 167 - #define XX_FECH24000 0x0000024B 168 168 - #define XX_FECH16000 0x00000371 169 169 - #define XX_FECH12000 0x0000044B 170 170 - #define XX_FECH8000 0x00000571 171 171 - #define XX_FECH44100 0x0000007F 172 172 - #define XX_FECH29400 0x0000016F 173 173 - #define XX_FECH22050 0x0000027F 174 174 - #define XX_FECH14000 0x000003EF 175 175 - #define XX_FECH11025 0x0000047F 176 176 - #define XX_FECH7350 0x000005BF 165 165 + int hexfreq; 177 166 178 178 - switch (freq) { 179 179 - case 48000: return XX_FECH48000; 180 180 - case 44100: return XX_FECH44100; 181 181 - case 32000: return XX_FECH32000; 182 182 - case 29400: return XX_FECH29400; 183 183 - case 24000: return XX_FECH24000; 184 184 - case 22050: return XX_FECH22050; 185 185 - case 16000: return XX_FECH16000; 186 186 - case 14000: return XX_FECH14000; 187 187 - case 12000: return XX_FECH12000; 188 188 - case 11025: return XX_FECH11025; 189 189 - case 8000: return XX_FECH8000; 190 190 - case 7350: return XX_FECH7350; 191 191 - default: return freq; /* The value is already correct */ 192 192 - } 167 167 + snd_assert(freq > 0, return 0); 168 168 + 169 169 + hexfreq = (28224000 * 10) / freq; 170 170 + hexfreq = (hexfreq + 5) / 10; 171 171 + 172 172 + /* max freq = 55125 Hz */ 173 173 + snd_assert(hexfreq > 0x00000200, return 0); 174 174 + 175 175 + if (hexfreq <= 0x03ff) 176 176 + return hexfreq - 0x00000201; 177 177 + if (hexfreq <= 0x07ff) 178 178 + return (hexfreq / 2) - 1; 179 179 + if (hexfreq <= 0x0fff) 180 180 + return (hexfreq / 4) + 0x000001ff; 181 181 + 182 182 + return 0x5fe; /* min freq = 6893 Hz */ 193 183 } 194 184 195 185

-1

sound/i2c/other/ak4114.c

reviewed

··· 554 554 if (snd_pcm_running(ak4114->capture_substream)) { 555 555 // printk("rate changed (%i <- %i)\n", runtime->rate, res); 556 556 snd_pcm_stop(ak4114->capture_substream, SNDRV_PCM_STATE_DRAINING); 557 557 - wake_up(&runtime->sleep); 558 557 res = 1; 559 558 } 560 559 snd_pcm_stream_unlock_irqrestore(ak4114->capture_substream, _flags);

+2

sound/isa/gus/gus_main.c

reviewed

··· 417 417 return 0; 418 418 } 419 419 420 420 + #if defined(CONFIG_SND_SEQUENCER) || (defined(MODULE) && defined(CONFIG_SND_SEQUENCER_MODULE)) 420 421 static void snd_gus_seq_dev_free(snd_seq_device_t *seq_dev) 421 422 { 422 423 snd_gus_card_t *gus = seq_dev->private_data; 423 424 gus->seq_dev = NULL; 424 425 } 426 426 + #endif 425 427 426 428 int snd_gus_initialize(snd_gus_card_t *gus) 427 429 {

+17 -17

sound/isa/wavefront/wavefront_fx.c

reviewed

··· 34 34 35 35 /* weird stuff, derived from port I/O tracing with dosemu */ 36 36 37 37 - unsigned char page_zero[] __initdata = { 37 37 + static unsigned char page_zero[] __initdata = { 38 38 0x01, 0x7c, 0x00, 0x1e, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf5, 0x00, 39 39 0x11, 0x00, 0x20, 0x00, 0x32, 0x00, 0x40, 0x00, 0x13, 0x00, 0x00, 40 40 0x00, 0x14, 0x02, 0x76, 0x00, 0x60, 0x00, 0x80, 0x02, 0x00, 0x00, ··· 61 61 0x1d, 0x02, 0xdf 62 62 }; 63 63 64 64 - unsigned char page_one[] __initdata = { 64 64 + static unsigned char page_one[] __initdata = { 65 65 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x19, 0x00, 66 66 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0xd8, 0x00, 0x00, 67 67 0x02, 0x20, 0x00, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x01, ··· 88 88 0x60, 0x00, 0x1b 89 89 }; 90 90 91 91 - unsigned char page_two[] __initdata = { 91 91 + static unsigned char page_two[] __initdata = { 92 92 0xc4, 0x00, 0x44, 0x07, 0x44, 0x00, 0x40, 0x25, 0x01, 0x06, 0xc4, 93 93 0x07, 0x40, 0x25, 0x01, 0x00, 0x46, 0x46, 0x00, 0x00, 0x00, 0x00, 94 94 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ··· 103 103 0x46, 0x05, 0x46, 0x07, 0x46, 0x07, 0x44 104 104 }; 105 105 106 106 - unsigned char page_three[] __initdata = { 106 106 + static unsigned char page_three[] __initdata = { 107 107 0x07, 0x40, 0x00, 0x00, 0x00, 0x47, 0x00, 0x40, 0x00, 0x40, 0x06, 108 108 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 109 109 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ··· 118 118 0x02, 0x00, 0x42, 0x00, 0xc0, 0x00, 0x40 119 119 }; 120 120 121 121 - unsigned char page_four[] __initdata = { 121 121 + static unsigned char page_four[] __initdata = { 122 122 0x63, 0x03, 0x26, 0x02, 0x2c, 0x00, 0x24, 0x00, 0x2e, 0x02, 0x02, 123 123 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 124 124 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ··· 133 133 0x02, 0x62, 0x02, 0x20, 0x01, 0x21, 0x01 134 134 }; 135 135 136 136 - unsigned char page_six[] __initdata = { 136 136 + static unsigned char page_six[] __initdata = { 137 137 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x04, 0x00, 0x00, 0x06, 0x00, 138 138 0x00, 0x08, 0x00, 0x00, 0x0a, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x0e, 139 139 0x00, 0x00, 0x10, 0x00, 0x00, 0x12, 0x00, 0x00, 0x14, 0x00, 0x00, ··· 154 154 0x80, 0x00, 0x7e, 0x80, 0x80 155 155 }; 156 156 157 157 - unsigned char page_seven[] __initdata = { 157 157 + static unsigned char page_seven[] __initdata = { 158 158 0x0f, 0xff, 0x00, 0x00, 0x08, 0x00, 0x08, 0x00, 0x02, 0x00, 0x00, 159 159 0x00, 0x00, 0x00, 0x0f, 0xff, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 160 160 0x08, 0x00, 0x00, 0x00, 0x0f, 0xff, 0x00, 0x00, 0x00, 0x00, 0x0f, ··· 181 181 0x00, 0x02, 0x00 182 182 }; 183 183 184 184 - unsigned char page_zero_v2[] __initdata = { 184 184 + static unsigned char page_zero_v2[] __initdata = { 185 185 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 186 186 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 187 187 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ··· 193 193 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 194 194 }; 195 195 196 196 - unsigned char page_one_v2[] __initdata = { 196 196 + static unsigned char page_one_v2[] __initdata = { 197 197 0x01, 0xc0, 0x01, 0xfa, 0x00, 0x1a, 0x00, 0x00, 0x00, 0x00, 0x00, 198 198 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 199 199 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ··· 205 205 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 206 206 }; 207 207 208 208 - unsigned char page_two_v2[] __initdata = { 208 208 + static unsigned char page_two_v2[] __initdata = { 209 209 0x46, 0x46, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 210 210 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 211 211 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 212 212 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 213 213 0x00, 0x00, 0x00, 0x00 214 214 }; 215 215 - unsigned char page_three_v2[] __initdata = { 215 215 + static unsigned char page_three_v2[] __initdata = { 216 216 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 217 217 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 218 218 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 219 219 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 220 220 0x00, 0x00, 0x00, 0x00 221 221 }; 222 222 - unsigned char page_four_v2[] __initdata = { 222 222 + static unsigned char page_four_v2[] __initdata = { 223 223 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 224 224 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 225 225 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ··· 227 227 0x00, 0x00, 0x00, 0x00 228 228 }; 229 229 230 230 - unsigned char page_seven_v2[] __initdata = { 230 230 + static unsigned char page_seven_v2[] __initdata = { 231 231 0x0f, 0xff, 0x0f, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 232 232 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 233 233 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ··· 239 239 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 240 240 }; 241 241 242 242 - unsigned char mod_v2[] __initdata = { 242 242 + static unsigned char mod_v2[] __initdata = { 243 243 0x01, 0x00, 0x02, 0x00, 0x01, 0x01, 0x02, 0x00, 0x01, 0x02, 0x02, 244 244 0x00, 0x01, 0x03, 0x02, 0x00, 0x01, 0x04, 0x02, 0x00, 0x01, 0x05, 245 245 0x02, 0x00, 0x01, 0x06, 0x02, 0x00, 0x01, 0x07, 0x02, 0x00, 0xb0, ··· 269 269 0x02, 0x01, 0x01, 0x04, 0x02, 0x01, 0x01, 0x05, 0x02, 0x01, 0x01, 270 270 0x06, 0x02, 0x01, 0x01, 0x07, 0x02, 0x01 271 271 }; 272 272 - unsigned char coefficients[] __initdata = { 272 272 + static unsigned char coefficients[] __initdata = { 273 273 0x07, 0x46, 0x00, 0x00, 0x07, 0x49, 0x00, 0x00, 0x00, 0x4b, 0x03, 274 274 0x11, 0x00, 0x4d, 0x01, 0x32, 0x07, 0x46, 0x00, 0x00, 0x07, 0x49, 275 275 0x00, 0x00, 0x07, 0x40, 0x00, 0x00, 0x07, 0x41, 0x00, 0x00, 0x01, ··· 305 305 0x06, 0x6c, 0x4c, 0x6c, 0x06, 0x50, 0x52, 0xe2, 0x06, 0x42, 0x02, 306 306 0xba 307 307 }; 308 308 - unsigned char coefficients2[] __initdata = { 308 308 + static unsigned char coefficients2[] __initdata = { 309 309 0x07, 0x46, 0x00, 0x00, 0x07, 0x49, 0x00, 0x00, 0x07, 0x45, 0x0f, 310 310 0xff, 0x07, 0x48, 0x0f, 0xff, 0x07, 0x7b, 0x04, 0xcc, 0x07, 0x7d, 311 311 0x04, 0xcc, 0x07, 0x7c, 0x00, 0x00, 0x07, 0x7e, 0x00, 0x00, 0x07, 312 312 0x46, 0x00, 0x00, 0x07, 0x49, 0x00, 0x00, 0x07, 0x47, 0x00, 0x00, 313 313 0x07, 0x4a, 0x00, 0x00, 0x07, 0x4c, 0x00, 0x00, 0x07, 0x4e, 0x00, 0x00 314 314 }; 315 315 - unsigned char coefficients3[] __initdata = { 315 315 + static unsigned char coefficients3[] __initdata = { 316 316 0x00, 0x00, 0x00, 0x00, 0x00, 0x28, 0x00, 0x28, 0x00, 0x51, 0x00, 317 317 0x51, 0x00, 0x7a, 0x00, 0x7a, 0x00, 0xa3, 0x00, 0xa3, 0x00, 0xcc, 318 318 0x00, 0xcc, 0x00, 0xf5, 0x00, 0xf5, 0x01, 0x1e, 0x01, 0x1e, 0x01,

+16 -9

sound/pci/ac97/ac97_codec.c

reviewed

··· 367 367 ac97->regs[reg] = value; 368 368 ac97->bus->ops->write(ac97, reg, value); 369 369 } 370 370 + set_bit(reg, ac97->reg_accessed); 370 371 up(&ac97->reg_mutex); 371 372 return change; 372 373 } ··· 411 410 ac97->regs[reg] = new; 412 411 ac97->bus->ops->write(ac97, reg, new); 413 412 } 413 413 + set_bit(reg, ac97->reg_accessed); 414 414 return change; 415 415 } 416 416 ··· 1078 1076 for (i = 0 ; i < ARRAY_SIZE(cbit); i++) { 1079 1077 unsigned short val; 1080 1078 snd_ac97_write(ac97, reg, 0x8080 | cbit[i] | (cbit[i] << 8)); 1079 1079 + /* Do the read twice due to buffers on some ac97 codecs. 1080 1080 + * e.g. The STAC9704 returns exactly what you wrote the the register 1081 1081 + * if you read it immediately. This causes the detect routine to fail. 1082 1082 + */ 1083 1083 + val = snd_ac97_read(ac97, reg); 1081 1084 val = snd_ac97_read(ac97, reg); 1082 1085 if (! *lo_max && (val & 0x7f) == cbit[i]) 1083 1086 *lo_max = max[i]; ··· 2231 2224 */ 2232 2225 void snd_ac97_resume(ac97_t *ac97) 2233 2226 { 2234 2234 - int i; 2227 2227 + unsigned long end_time; 2235 2228 2236 2229 if (ac97->bus->ops->reset) { 2237 2230 ac97->bus->ops->reset(ac97); ··· 2249 2242 snd_ac97_write(ac97, AC97_POWERDOWN, ac97->regs[AC97_POWERDOWN]); 2250 2243 if (ac97_is_audio(ac97)) { 2251 2244 ac97->bus->ops->write(ac97, AC97_MASTER, 0x8101); 2252 2252 - for (i = HZ/10; i >= 0; i--) { 2245 2245 + end_time = jiffies + msecs_to_jiffies(100); 2246 2246 + do { 2253 2247 if (snd_ac97_read(ac97, AC97_MASTER) == 0x8101) 2254 2248 break; 2255 2249 set_current_state(TASK_UNINTERRUPTIBLE); 2256 2250 schedule_timeout(1); 2257 2257 - } 2251 2251 + } while (time_after_eq(end_time, jiffies)); 2258 2252 /* FIXME: extra delay */ 2259 2253 ac97->bus->ops->write(ac97, AC97_MASTER, 0x8000); 2260 2260 - if (snd_ac97_read(ac97, AC97_MASTER) != 0x8000) { 2261 2261 - set_current_state(TASK_UNINTERRUPTIBLE); 2262 2262 - schedule_timeout(HZ/4); 2263 2263 - } 2254 2254 + if (snd_ac97_read(ac97, AC97_MASTER) != 0x8000) 2255 2255 + msleep(250); 2264 2256 } else { 2265 2265 - for (i = HZ/10; i >= 0; i--) { 2257 2257 + end_time = jiffies + msecs_to_jiffies(100); 2258 2258 + do { 2266 2259 unsigned short val = snd_ac97_read(ac97, AC97_EXTENDED_MID); 2267 2260 if (val != 0xffff && (val & 1) != 0) 2268 2261 break; 2269 2262 set_current_state(TASK_UNINTERRUPTIBLE); 2270 2263 schedule_timeout(1); 2271 2271 - } 2264 2264 + } while (time_after_eq(end_time, jiffies)); 2272 2265 } 2273 2266 __reset_ready: 2274 2267

+3

sound/pci/ac97/ac97_patch.c

reviewed

··· 1528 1528 }, 1529 1529 AC97_SURROUND_JACK_MODE_CTL, 1530 1530 AC97_CHANNEL_MODE_CTL, 1531 1531 + 1532 1532 + AC97_SINGLE("Headphone Jack Sense", AC97_AD_JACK_SPDIF, 10, 1, 0), 1533 1533 + AC97_SINGLE("Line Jack Sense", AC97_AD_JACK_SPDIF, 12, 1, 0), 1531 1534 }; 1532 1535 1533 1536 static int patch_ad1888_specific(ac97_t *ac97)

+2 -2

sound/pci/ali5451/ali5451.c

reviewed

··· 399 399 unsigned long end_time; 400 400 unsigned int res; 401 401 402 402 - end_time = jiffies + 10 * (HZ >> 2); 402 402 + end_time = jiffies + 10 * msecs_to_jiffies(250); 403 403 do { 404 404 res = snd_ali_5451_peek(codec,port); 405 405 if (! (res & 0x8000)) ··· 422 422 dwChk1 = snd_ali_5451_peek(codec, ALI_STIMER); 423 423 dwChk2 = snd_ali_5451_peek(codec, ALI_STIMER); 424 424 425 425 - end_time = jiffies + 10 * (HZ >> 2); 425 425 + end_time = jiffies + 10 * msecs_to_jiffies(250); 426 426 do { 427 427 dwChk2 = snd_ali_5451_peek(codec, ALI_STIMER); 428 428 if (dwChk2 != dwChk1)

+1

sound/pci/atiixp_modem.c

reviewed

··· 265 265 */ 266 266 static struct pci_device_id snd_atiixp_ids[] = { 267 267 { 0x1002, 0x434d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* SB200 */ 268 268 + { 0x1002, 0x4378, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* SB400 */ 268 269 { 0, } 269 270 }; 270 271

+7 -2

sound/pci/cmipci.c

reviewed

··· 306 306 #define CM_REG_FM_PCI 0x50 307 307 308 308 /* 309 309 - * for CMI-8338 .. this is not valid for CMI-8738. 309 309 + * access from SB-mixer port 310 310 */ 311 311 #define CM_REG_EXTENT_IND 0xf0 312 312 #define CM_VPHONE_MASK 0xe0 /* Phone volume control (0-3) << 5 */ ··· 315 315 #define CM_VSPKM 0x08 /* Speaker mute control, default high */ 316 316 #define CM_RLOOPREN 0x04 /* Rec. R-channel enable */ 317 317 #define CM_RLOOPLEN 0x02 /* Rec. L-channel enable */ 318 318 + #define CM_VADMIC3 0x01 /* Mic record boost */ 318 319 319 320 /* 320 321 * CMI-8338 spec ver 0.5 (this is not valid for CMI-8738): ··· 2136 2135 CMIPCI_MIXER_VOL_STEREO("Aux Playback Volume", CM_REG_AUX_VOL, 4, 0, 15), 2137 2136 CMIPCI_MIXER_SW_STEREO("Aux Playback Switch", CM_REG_MIXER2, CM_VAUXLM_SHIFT, CM_VAUXRM_SHIFT, 0), 2138 2137 CMIPCI_MIXER_SW_STEREO("Aux Capture Switch", CM_REG_MIXER2, CM_RAUXLEN_SHIFT, CM_RAUXREN_SHIFT, 0), 2139 2139 - CMIPCI_MIXER_SW_MONO("Mic Boost", CM_REG_MIXER2, CM_MICGAINZ_SHIFT, 1), 2138 2138 + CMIPCI_MIXER_SW_MONO("Mic Boost Playback Switch", CM_REG_MIXER2, CM_MICGAINZ_SHIFT, 1), 2140 2139 CMIPCI_MIXER_VOL_MONO("Mic Capture Volume", CM_REG_MIXER2, CM_VADMIC_SHIFT, 7), 2140 2140 + CMIPCI_SB_VOL_MONO("Phone Playback Volume", CM_REG_EXTENT_IND, 5, 7), 2141 2141 + CMIPCI_DOUBLE("Phone Playback Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 4, 4, 1, 0, 0), 2142 2142 + CMIPCI_DOUBLE("PC Speaker Playnack Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 3, 3, 1, 0, 0), 2143 2143 + CMIPCI_DOUBLE("Mic Boost Capture Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 0, 0, 1, 0, 0), 2141 2144 }; 2142 2145 2143 2146 /*

+5 -10

sound/pci/cs46xx/cs46xx_lib.c

reviewed

··· 2400 2400 if ((err = snd_ac97_read(ac97, AC97_REC_GAIN)) == 0x8a05) 2401 2401 return; 2402 2402 2403 2403 - set_current_state(TASK_UNINTERRUPTIBLE); 2404 2404 - schedule_timeout(HZ/100); 2403 2403 + msleep(10); 2405 2404 } while (time_after_eq(end_time, jiffies)); 2406 2405 2407 2406 snd_printk("CS46xx secondary codec dont respond!\n"); ··· 2434 2435 err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97[codec]); 2435 2436 return err; 2436 2437 } 2437 2437 - set_current_state(TASK_INTERRUPTIBLE); 2438 2438 - schedule_timeout(HZ/100); 2438 2438 + msleep(10); 2439 2439 } 2440 2440 snd_printdd("snd_cs46xx: codec %d detection timeout\n", codec); 2441 2441 return -ENXIO; ··· 3016 3018 /* 3017 3019 * Wait until the PLL has stabilized. 3018 3020 */ 3019 3019 - set_current_state(TASK_UNINTERRUPTIBLE); 3020 3020 - schedule_timeout(HZ/10); /* 100ms */ 3021 3021 + msleep(100); 3021 3022 3022 3023 /* 3023 3024 * Turn on clocking of the core so that we can setup the serial ports. ··· 3069 3072 */ 3070 3073 if (snd_cs46xx_peekBA0(chip, BA0_ACSTS) & ACSTS_CRDY) 3071 3074 goto ok1; 3072 3072 - set_current_state(TASK_UNINTERRUPTIBLE); 3073 3073 - schedule_timeout((HZ+99)/100); 3075 3075 + msleep(10); 3074 3076 } 3075 3077 3076 3078 ··· 3118 3122 */ 3119 3123 if ((snd_cs46xx_peekBA0(chip, BA0_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) == (ACISV_ISV3 | ACISV_ISV4)) 3120 3124 goto ok2; 3121 3121 - set_current_state(TASK_UNINTERRUPTIBLE); 3122 3122 - schedule_timeout((HZ+99)/100); 3125 3125 + msleep(10); 3123 3126 } 3124 3127 3125 3128 #ifndef CONFIG_SND_CS46XX_NEW_DSP

+6 -4

sound/pci/emu10k1/emu10k1.c

reviewed

··· 52 52 static int max_synth_voices[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 64}; 53 53 static int max_buffer_size[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 128}; 54 54 static int enable_ir[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 0}; 55 55 + static uint subsystem[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 0}; /* Force card subsystem model */ 55 56 56 57 module_param_array(index, int, NULL, 0444); 57 58 MODULE_PARM_DESC(index, "Index value for the EMU10K1 soundcard."); ··· 72 71 MODULE_PARM_DESC(max_buffer_size, "Maximum sample buffer size in MB."); 73 72 module_param_array(enable_ir, bool, NULL, 0444); 74 73 MODULE_PARM_DESC(enable_ir, "Enable IR."); 75 75 - 74 74 + module_param_array(subsystem, uint, NULL, 0444); 75 75 + MODULE_PARM_DESC(subsystem, "Force card subsystem model."); 76 76 /* 77 77 * Class 0401: 1102:0008 (rev 00) Subsystem: 1102:1001 -> Audigy2 Value Model:SB0400 78 78 */ ··· 124 122 max_buffer_size[dev] = 1024; 125 123 if ((err = snd_emu10k1_create(card, pci, extin[dev], extout[dev], 126 124 (long)max_buffer_size[dev] * 1024 * 1024, 127 127 - enable_ir[dev], 125 125 + enable_ir[dev], subsystem[dev], 128 126 &emu)) < 0) { 129 127 snd_card_free(card); 130 128 return err; ··· 142 140 return err; 143 141 } 144 142 /* This stores the periods table. */ 145 145 - if (emu->audigy && emu->revision == 4) { /* P16V */ 143 143 + if (emu->card_capabilities->ca0151_chip) { /* P16V */ 146 144 if(snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci), 1024, &emu->p16v_buffer) < 0) { 147 145 snd_p16v_free(emu); 148 146 return -ENOMEM; ··· 163 161 snd_card_free(card); 164 162 return err; 165 163 } 166 166 - if (emu->audigy && emu->revision == 4) { /* P16V */ 164 164 + if (emu->card_capabilities->ca0151_chip) { /* P16V */ 167 165 if ((err = snd_p16v_pcm(emu, 4, NULL)) < 0) { 168 166 snd_card_free(card); 169 167 return err;

+126 -109

sound/pci/emu10k1/emu10k1_main.c

reviewed

··· 191 191 /* Set playback routing. */ 192 192 snd_emu10k1_ptr20_write(emu, CAPTURE_P16V_SOURCE, 0, 0x78e4); 193 193 } 194 194 - if (emu->audigy && (emu->serial == 0x10011102) ) { /* audigy2 Value */ 194 194 + if (emu->card_capabilities->ca0108_chip) { /* audigy2 Value */ 195 195 /* Hacks for Alice3 to work independent of haP16V driver */ 196 196 u32 tmp; 197 197 ··· 253 253 HCFG_AUTOMUTE | HCFG_JOYENABLE, emu->port + HCFG); 254 254 else 255 255 outl(HCFG_AUTOMUTE | HCFG_JOYENABLE, emu->port + HCFG); 256 256 + /* FIXME: Remove all these emu->model and replace it with a card recognition parameter, 257 257 + * e.g. card_capabilities->joystick */ 256 258 } else if (emu->model == 0x20 || 257 259 emu->model == 0xc400 || 258 260 (emu->model == 0x21 && emu->revision < 6)) ··· 301 299 if (emu->audigy) { 302 300 outl(inl(emu->port + A_IOCFG) & ~0x44, emu->port + A_IOCFG); 303 301 304 304 - if (emu->revision == 4) { /* audigy2 */ 302 302 + if (emu->card_capabilities->ca0151_chip) { /* audigy2 */ 305 303 /* Unmute Analog now. Set GPO6 to 1 for Apollo. 306 304 * This has to be done after init ALice3 I2SOut beyond 48KHz. 307 305 * So, sequence is important. */ 308 306 outl(inl(emu->port + A_IOCFG) | 0x0040, emu->port + A_IOCFG); 309 309 - } else if (emu->serial == 0x10011102) { /* audigy2 value */ 307 307 + } else if (emu->card_capabilities->ca0108_chip) { /* audigy2 value */ 310 308 /* Unmute Analog now. */ 311 309 outl(inl(emu->port + A_IOCFG) | 0x0060, emu->port + A_IOCFG); 312 310 } else { ··· 616 614 617 615 static emu_chip_details_t emu_chip_details[] = { 618 616 /* Audigy 2 Value AC3 out does not work yet. Need to find out how to turn off interpolators.*/ 617 617 + /* Tested by James@superbug.co.uk 3rd July 2005 */ 619 618 {.vendor = 0x1102, .device = 0x0008, .subsystem = 0x10011102, 620 619 .driver = "Audigy2", .name = "Audigy 2 Value [SB0400]", 621 620 .id = "Audigy2", ··· 630 627 .emu10k2_chip = 1, 631 628 .ca0108_chip = 1, 632 629 .ac97_chip = 1} , 630 630 + /* Tested by James@superbug.co.uk 8th July 2005. No sound available yet. */ 631 631 + {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x40011102, 632 632 + .driver = "Audigy2", .name = "E-mu 1212m [4001]", 633 633 + .id = "EMU1212m", 634 634 + .emu10k2_chip = 1, 635 635 + .ca0102_chip = 1, 636 636 + .ecard = 1} , 637 637 + /* Tested by James@superbug.co.uk 3rd July 2005 */ 633 638 {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x20071102, 634 639 .driver = "Audigy2", .name = "Audigy 4 PRO [SB0380]", 635 640 .id = "Audigy2", ··· 698 687 .ca0151_chip = 1, 699 688 .spdif_bug = 1, 700 689 .ac97_chip = 1} , 701 701 - {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x10020052, 702 702 - .driver = "Audigy", .name = "Audigy 1 ES [SB0160]", 703 703 - .id = "Audigy", 704 704 - .emu10k2_chip = 1, 705 705 - .ca0102_chip = 1, 706 706 - .spdif_bug = 1, 707 707 - .ac97_chip = 1} , 708 690 {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x00531102, 709 691 .driver = "Audigy", .name = "Audigy 1 [SB0090]", 710 692 .id = "Audigy", 711 693 .emu10k2_chip = 1, 712 694 .ca0102_chip = 1, 695 695 + .ac97_chip = 1} , 696 696 + {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x00521102, 697 697 + .driver = "Audigy", .name = "Audigy 1 ES [SB0160]", 698 698 + .id = "Audigy", 699 699 + .emu10k2_chip = 1, 700 700 + .ca0102_chip = 1, 701 701 + .spdif_bug = 1, 713 702 .ac97_chip = 1} , 714 703 {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x00511102, 715 704 .driver = "Audigy", .name = "Audigy 1 [SB0090]", ··· 723 712 .emu10k2_chip = 1, 724 713 .ca0102_chip = 1, 725 714 .ac97_chip = 1} , 726 726 - {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x40011102, 727 727 - .driver = "EMU10K1", .name = "E-mu APS [4001]", 728 728 - .id = "APS", 729 729 - .emu10k1_chip = 1, 730 730 - .ecard = 1} , 731 731 - {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80611102, 732 732 - .driver = "EMU10K1", .name = "SBLive! Player 5.1 [SB0060]", 733 733 - .id = "Live", 734 734 - .emu10k1_chip = 1, 735 735 - .ac97_chip = 1, 736 736 - .sblive51 = 1} , 737 737 - {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80641102, 738 738 - .driver = "EMU10K1", .name = "SB Live 5.1", 739 739 - .id = "Live", 740 740 - .emu10k1_chip = 1, 741 741 - .ac97_chip = 1, 742 742 - .sblive51 = 1} , 743 743 - {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80401102, 744 744 - .driver = "EMU10K1", .name = "SBLive! Platinum [CT4760P]", 745 745 - .id = "Live", 746 746 - .emu10k1_chip = 1, 747 747 - .ac97_chip = 1} , 748 748 - {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x00211102, 749 749 - .driver = "EMU10K1", .name = "SBLive! [CT4620]", 750 750 - .id = "Live", 751 751 - .emu10k1_chip = 1, 752 752 - .ac97_chip = 1, 753 753 - .sblive51 = 1} , 754 754 - {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x00201102, 755 755 - .driver = "EMU10K1", .name = "SBLive! Value [CT4670]", 756 756 - .id = "Live", 757 757 - .emu10k1_chip = 1, 758 758 - .ac97_chip = 1, 759 759 - .sblive51 = 1} , 760 760 - {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80221102, 761 761 - .driver = "EMU10K1", .name = "SBLive! Value [CT4780]", 762 762 - .id = "Live", 763 763 - .emu10k1_chip = 1, 764 764 - .ac97_chip = 1, 765 765 - .sblive51 = 1} , 766 766 - {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80231102, 767 767 - .driver = "EMU10K1", .name = "SB PCI512 [CT4790]", 768 768 - .id = "Live", 769 769 - .emu10k1_chip = 1, 770 770 - .ac97_chip = 1, 771 771 - .sblive51 = 1} , 772 772 - {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80261102, 773 773 - .driver = "EMU10K1", .name = "SBLive! Value [CT4830]", 774 774 - .id = "Live", 775 775 - .emu10k1_chip = 1, 776 776 - .ac97_chip = 1, 777 777 - .sblive51 = 1} , 778 778 - {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80311102, 779 779 - .driver = "EMU10K1", .name = "SBLive! Value [CT4831]", 780 780 - .id = "Live", 781 781 - .emu10k1_chip = 1, 782 782 - .ac97_chip = 1, 783 783 - .sblive51 = 1} , 784 784 - {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80271102, 785 785 - .driver = "EMU10K1", .name = "SBLive! Value [CT4832]", 786 786 - .id = "Live", 787 787 - .emu10k1_chip = 1, 788 788 - .ac97_chip = 1, 789 789 - .sblive51 = 1} , 790 790 - {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80511102, 791 791 - .driver = "EMU10K1", .name = "SBLive! Value [CT4850]", 792 792 - .id = "Live", 793 793 - .emu10k1_chip = 1, 794 794 - .ac97_chip = 1, 795 795 - .sblive51 = 1} , 796 796 - {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80281102, 797 797 - .driver = "EMU10K1", .name = "SBLive! Value [CT4870]", 798 798 - .id = "Live", 799 799 - .emu10k1_chip = 1, 800 800 - .ac97_chip = 1, 801 801 - .sblive51 = 1} , 802 802 - {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80321102, 803 803 - .driver = "EMU10K1", .name = "SBLive! Value [CT4871]", 804 804 - .id = "Live", 805 805 - .emu10k1_chip = 1, 806 806 - .ac97_chip = 1, 807 807 - .sblive51 = 1} , 808 808 - {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80611102, 809 809 - .driver = "EMU10K1", .name = "SBLive! Value [SB0060]", 810 810 - .id = "Live", 811 811 - .emu10k1_chip = 1, 812 812 - .ac97_chip = 1, 813 813 - .sblive51 = 1} , 814 814 - {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80691102, 815 815 - .driver = "EMU10K1", .name = "SBLive! Value [SB0101]", 715 715 + {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x806B1102, 716 716 + .driver = "EMU10K1", .name = "SBLive! [SB0105]", 816 717 .id = "Live", 817 718 .emu10k1_chip = 1, 818 719 .ac97_chip = 1, ··· 735 812 .emu10k1_chip = 1, 736 813 .ac97_chip = 1, 737 814 .sblive51 = 1} , 738 738 - {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x806B1102, 739 739 - .driver = "EMU10K1", .name = "SBLive! [SB0105]", 815 815 + {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80691102, 816 816 + .driver = "EMU10K1", .name = "SBLive! Value [SB0101]", 817 817 + .id = "Live", 818 818 + .emu10k1_chip = 1, 819 819 + .ac97_chip = 1, 820 820 + .sblive51 = 1} , 821 821 + {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80641102, 822 822 + .driver = "EMU10K1", .name = "SB Live 5.1", 823 823 + .id = "Live", 824 824 + .emu10k1_chip = 1, 825 825 + .ac97_chip = 1, 826 826 + .sblive51 = 1} , 827 827 + {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80611102, 828 828 + .driver = "EMU10K1", .name = "SBLive! Player 5.1 [SB0060]", 829 829 + .id = "Live", 830 830 + .emu10k1_chip = 1, 831 831 + .ac97_chip = 1, 832 832 + .sblive51 = 1} , 833 833 + {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80511102, 834 834 + .driver = "EMU10K1", .name = "SBLive! Value [CT4850]", 835 835 + .id = "Live", 836 836 + .emu10k1_chip = 1, 837 837 + .ac97_chip = 1, 838 838 + .sblive51 = 1} , 839 839 + {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80401102, 840 840 + .driver = "EMU10K1", .name = "SBLive! Platinum [CT4760P]", 841 841 + .id = "Live", 842 842 + .emu10k1_chip = 1, 843 843 + .ac97_chip = 1} , 844 844 + {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80321102, 845 845 + .driver = "EMU10K1", .name = "SBLive! Value [CT4871]", 846 846 + .id = "Live", 847 847 + .emu10k1_chip = 1, 848 848 + .ac97_chip = 1, 849 849 + .sblive51 = 1} , 850 850 + {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80311102, 851 851 + .driver = "EMU10K1", .name = "SBLive! Value [CT4831]", 852 852 + .id = "Live", 853 853 + .emu10k1_chip = 1, 854 854 + .ac97_chip = 1, 855 855 + .sblive51 = 1} , 856 856 + {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80281102, 857 857 + .driver = "EMU10K1", .name = "SBLive! Value [CT4870]", 858 858 + .id = "Live", 859 859 + .emu10k1_chip = 1, 860 860 + .ac97_chip = 1, 861 861 + .sblive51 = 1} , 862 862 + /* Tested by James@superbug.co.uk 3rd July 2005 */ 863 863 + {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80271102, 864 864 + .driver = "EMU10K1", .name = "SBLive! Value [CT4832]", 865 865 + .id = "Live", 866 866 + .emu10k1_chip = 1, 867 867 + .ac97_chip = 1, 868 868 + .sblive51 = 1} , 869 869 + {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80261102, 870 870 + .driver = "EMU10K1", .name = "SBLive! Value [CT4830]", 871 871 + .id = "Live", 872 872 + .emu10k1_chip = 1, 873 873 + .ac97_chip = 1, 874 874 + .sblive51 = 1} , 875 875 + {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80231102, 876 876 + .driver = "EMU10K1", .name = "SB PCI512 [CT4790]", 877 877 + .id = "Live", 878 878 + .emu10k1_chip = 1, 879 879 + .ac97_chip = 1, 880 880 + .sblive51 = 1} , 881 881 + {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80221102, 882 882 + .driver = "EMU10K1", .name = "SBLive! Value [CT4780]", 883 883 + .id = "Live", 884 884 + .emu10k1_chip = 1, 885 885 + .ac97_chip = 1, 886 886 + .sblive51 = 1} , 887 887 + {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x40011102, 888 888 + .driver = "EMU10K1", .name = "E-mu APS [4001]", 889 889 + .id = "APS", 890 890 + .emu10k1_chip = 1, 891 891 + .ecard = 1} , 892 892 + {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x00211102, 893 893 + .driver = "EMU10K1", .name = "SBLive! [CT4620]", 894 894 + .id = "Live", 895 895 + .emu10k1_chip = 1, 896 896 + .ac97_chip = 1, 897 897 + .sblive51 = 1} , 898 898 + {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x00201102, 899 899 + .driver = "EMU10K1", .name = "SBLive! Value [CT4670]", 740 900 .id = "Live", 741 901 .emu10k1_chip = 1, 742 902 .ac97_chip = 1, ··· 839 833 unsigned short extout_mask, 840 834 long max_cache_bytes, 841 835 int enable_ir, 836 836 + uint subsystem, 842 837 emu10k1_t ** remu) 843 838 { 844 839 emu10k1_t *emu; ··· 885 878 886 879 for (c = emu_chip_details; c->vendor; c++) { 887 880 if (c->vendor == pci->vendor && c->device == pci->device) { 888 888 - if (c->subsystem && c->subsystem != emu->serial) 889 889 - continue; 890 890 - if (c->revision && c->revision != emu->revision) 891 891 - continue; 881 881 + if (subsystem) { 882 882 + if (c->subsystem && (c->subsystem == subsystem) ) { 883 883 + break; 884 884 + } else continue; 885 885 + } else { 886 886 + if (c->subsystem && (c->subsystem != emu->serial) ) 887 887 + continue; 888 888 + if (c->revision && c->revision != emu->revision) 889 889 + continue; 890 890 + } 892 891 break; 893 892 } 894 893 } ··· 905 892 return -ENOENT; 906 893 } 907 894 emu->card_capabilities = c; 908 908 - if (c->subsystem != 0) 895 895 + if (c->subsystem && !subsystem) 909 896 snd_printdd("Sound card name=%s\n", c->name); 910 910 - else 911 911 - snd_printdd("Sound card name=%s, vendor=0x%x, device=0x%x, subsystem=0x%x\n", c->name, pci->vendor, pci->device, emu->serial); 897 897 + else if (subsystem) 898 898 + snd_printdd("Sound card name=%s, vendor=0x%x, device=0x%x, subsystem=0x%x. Forced to subsytem=0x%x\n", 899 899 + c->name, pci->vendor, pci->device, emu->serial, c->subsystem); 900 900 + else 901 901 + snd_printdd("Sound card name=%s, vendor=0x%x, device=0x%x, subsystem=0x%x.\n", 902 902 + c->name, pci->vendor, pci->device, emu->serial); 912 903 913 904 if (!*card->id && c->id) { 914 905 int i, n = 0;

+10 -10

sound/pci/emu10k1/p16v.c

reviewed

··· 822 822 static snd_kcontrol_new_t snd_p16v_volume_control_analog_front = 823 823 { 824 824 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 825 825 - .name = "HD Analog Front Volume", 825 825 + .name = "HD Analog Front Playback Volume", 826 826 .info = snd_p16v_volume_info, 827 827 .get = snd_p16v_volume_get_analog_front, 828 828 .put = snd_p16v_volume_put_analog_front ··· 831 831 static snd_kcontrol_new_t snd_p16v_volume_control_analog_center_lfe = 832 832 { 833 833 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 834 834 - .name = "HD Analog Center/LFE Volume", 834 834 + .name = "HD Analog Center/LFE Playback Volume", 835 835 .info = snd_p16v_volume_info, 836 836 .get = snd_p16v_volume_get_analog_center_lfe, 837 837 .put = snd_p16v_volume_put_analog_center_lfe ··· 840 840 static snd_kcontrol_new_t snd_p16v_volume_control_analog_unknown = 841 841 { 842 842 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 843 843 - .name = "HD Analog Unknown Volume", 843 843 + .name = "HD Analog Unknown Playback Volume", 844 844 .info = snd_p16v_volume_info, 845 845 .get = snd_p16v_volume_get_analog_unknown, 846 846 .put = snd_p16v_volume_put_analog_unknown ··· 849 849 static snd_kcontrol_new_t snd_p16v_volume_control_analog_rear = 850 850 { 851 851 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 852 852 - .name = "HD Analog Rear Volume", 852 852 + .name = "HD Analog Rear Playback Volume", 853 853 .info = snd_p16v_volume_info, 854 854 .get = snd_p16v_volume_get_analog_rear, 855 855 .put = snd_p16v_volume_put_analog_rear ··· 858 858 static snd_kcontrol_new_t snd_p16v_volume_control_spdif_front = 859 859 { 860 860 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 861 861 - .name = "HD SPDIF Front Volume", 861 861 + .name = "HD SPDIF Front Playback Volume", 862 862 .info = snd_p16v_volume_info, 863 863 .get = snd_p16v_volume_get_spdif_front, 864 864 .put = snd_p16v_volume_put_spdif_front ··· 867 867 static snd_kcontrol_new_t snd_p16v_volume_control_spdif_center_lfe = 868 868 { 869 869 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 870 870 - .name = "HD SPDIF Center/LFE Volume", 870 870 + .name = "HD SPDIF Center/LFE Playback Volume", 871 871 .info = snd_p16v_volume_info, 872 872 .get = snd_p16v_volume_get_spdif_center_lfe, 873 873 .put = snd_p16v_volume_put_spdif_center_lfe ··· 876 876 static snd_kcontrol_new_t snd_p16v_volume_control_spdif_unknown = 877 877 { 878 878 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 879 879 - .name = "HD SPDIF Unknown Volume", 879 879 + .name = "HD SPDIF Unknown Playback Volume", 880 880 .info = snd_p16v_volume_info, 881 881 .get = snd_p16v_volume_get_spdif_unknown, 882 882 .put = snd_p16v_volume_put_spdif_unknown ··· 885 885 static snd_kcontrol_new_t snd_p16v_volume_control_spdif_rear = 886 886 { 887 887 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 888 888 - .name = "HD SPDIF Rear Volume", 888 888 + .name = "HD SPDIF Rear Playback Volume", 889 889 .info = snd_p16v_volume_info, 890 890 .get = snd_p16v_volume_get_spdif_rear, 891 891 .put = snd_p16v_volume_put_spdif_rear ··· 936 936 static snd_kcontrol_new_t snd_p16v_capture_source __devinitdata = 937 937 { 938 938 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 939 939 - .name = "HD Capture source", 939 939 + .name = "HD source Capture", 940 940 .info = snd_p16v_capture_source_info, 941 941 .get = snd_p16v_capture_source_get, 942 942 .put = snd_p16v_capture_source_put ··· 985 985 static snd_kcontrol_new_t snd_p16v_capture_channel __devinitdata = 986 986 { 987 987 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 988 988 - .name = "HD Capture channel", 988 988 + .name = "HD channel Capture", 989 989 .info = snd_p16v_capture_channel_info, 990 990 .get = snd_p16v_capture_channel_get, 991 991 .put = snd_p16v_capture_channel_put

+11 -11

sound/pci/ens1370.c

reviewed

··· 685 685 return 0; 686 686 } 687 687 688 688 + static void snd_es1371_codec_wait(ac97_t *ac97) 689 689 + { 690 690 + msleep(750); 691 691 + snd_es1371_codec_read(ac97, AC97_RESET); 692 692 + snd_es1371_codec_read(ac97, AC97_VENDOR_ID1); 693 693 + snd_es1371_codec_read(ac97, AC97_VENDOR_ID2); 694 694 + msleep(50); 695 695 + } 696 696 + 688 697 static void snd_es1371_adc_rate(ensoniq_t * ensoniq, unsigned int rate) 689 698 { 690 699 unsigned int n, truncm, freq, result; ··· 1594 1585 static ac97_bus_ops_t ops = { 1595 1586 .write = snd_es1371_codec_write, 1596 1587 .read = snd_es1371_codec_read, 1588 1588 + .wait = snd_es1371_codec_wait, 1597 1589 }; 1598 1590 1599 1591 if ((err = snd_ac97_bus(card, 0, &ops, NULL, &pbus)) < 0) ··· 2018 2008 if (pci->vendor == es1371_ac97_reset_hack[idx].vid && 2019 2009 pci->device == es1371_ac97_reset_hack[idx].did && 2020 2010 ensoniq->rev == es1371_ac97_reset_hack[idx].rev) { 2021 2021 - unsigned long tmo; 2022 2022 - signed long tmo2; 2023 2023 - 2024 2011 ensoniq->cssr |= ES_1371_ST_AC97_RST; 2025 2012 outl(ensoniq->cssr, ES_REG(ensoniq, STATUS)); 2026 2013 /* need to delay around 20ms(bleech) to give 2027 2014 some CODECs enough time to wakeup */ 2028 2028 - tmo = jiffies + (HZ / 50) + 1; 2029 2029 - while (1) { 2030 2030 - tmo2 = tmo - jiffies; 2031 2031 - if (tmo2 <= 0) 2032 2032 - break; 2033 2033 - set_current_state(TASK_UNINTERRUPTIBLE); 2034 2034 - schedule_timeout(tmo2); 2035 2035 - } 2015 2015 + msleep(20); 2036 2016 break; 2037 2017 } 2038 2018 /* AC'97 warm reset to start the bitclk */

+4 -10

sound/pci/es1968.c

reviewed

··· 664 664 return result; 665 665 } 666 666 667 667 - #define big_mdelay(msec) do {\ 668 668 - set_current_state(TASK_UNINTERRUPTIBLE);\ 669 669 - schedule_timeout(((msec) * HZ + 999) / 1000);\ 670 670 - } while (0) 671 671 - 672 667 /* Wait for the codec bus to be free */ 673 668 static int snd_es1968_ac97_wait(es1968_t *chip) 674 669 { ··· 1804 1809 snd_es1968_trigger_apu(chip, apu, ESM_APU_16BITLINEAR); 1805 1810 do_gettimeofday(&start_time); 1806 1811 spin_unlock_irq(&chip->reg_lock); 1807 1807 - set_current_state(TASK_UNINTERRUPTIBLE); 1808 1808 - schedule_timeout(HZ / 20); /* 50 msec */ 1812 1812 + msleep(50); 1809 1813 spin_lock_irq(&chip->reg_lock); 1810 1814 offset = __apu_get_register(chip, apu, 5); 1811 1815 do_gettimeofday(&stop_time); ··· 2087 2093 outw(0x0000, ioaddr + 0x60); /* write 0 to gpio 0 */ 2088 2094 udelay(20); 2089 2095 outw(0x0001, ioaddr + 0x60); /* write 1 to gpio 1 */ 2090 2090 - big_mdelay(20); 2096 2096 + msleep(20); 2091 2097 2092 2098 outw(save_68 | 0x1, ioaddr + 0x68); /* now restore .. */ 2093 2099 outw((inw(ioaddr + 0x38) & 0xfffc) | 0x1, ioaddr + 0x38); ··· 2103 2109 outw(0x0001, ioaddr + 0x60); /* write 1 to gpio */ 2104 2110 udelay(20); 2105 2111 outw(0x0009, ioaddr + 0x60); /* write 9 to gpio */ 2106 2106 - big_mdelay(500); 2112 2112 + msleep(500); 2107 2113 //outw(inw(ioaddr + 0x38) & 0xfffc, ioaddr + 0x38); 2108 2114 outw(inw(ioaddr + 0x3a) & 0xfffc, ioaddr + 0x3a); 2109 2115 outw(inw(ioaddr + 0x3c) & 0xfffc, ioaddr + 0x3c); ··· 2129 2135 2130 2136 if (w > 10000) { 2131 2137 outb(inb(ioaddr + 0x37) | 0x08, ioaddr + 0x37); /* do a software reset */ 2132 2132 - big_mdelay(500); /* oh my.. */ 2138 2138 + msleep(500); /* oh my.. */ 2133 2139 outb(inb(ioaddr + 0x37) & ~0x08, 2134 2140 ioaddr + 0x37); 2135 2141 udelay(1);

+3

sound/pci/hda/hda_codec.h

reviewed

··· 262 262 #define AC_PINCTL_OUT_EN (1<<6) 263 263 #define AC_PINCTL_HP_EN (1<<7) 264 264 265 265 + /* Unsolicited response - 8bit */ 266 266 + #define AC_USRSP_EN (1<<7) 267 267 + 265 268 /* configuration default - 32bit */ 266 269 #define AC_DEFCFG_SEQUENCE (0xf<<0) 267 270 #define AC_DEFCFG_DEF_ASSOC (0xf<<4)

+6

sound/pci/hda/hda_intel.c

reviewed

··· 178 178 #define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */ 179 179 #define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */ 180 180 181 181 + /* GCTL unsolicited response enable bit */ 182 182 + #define ICH6_GCTL_UREN (1<<8) 183 183 + 181 184 /* GCTL reset bit */ 182 185 #define ICH6_GCTL_RESET (1<<0) 183 186 ··· 564 561 snd_printd("azx_reset: controller not ready!\n"); 565 562 return -EBUSY; 566 563 } 564 564 + 565 565 + /* Accept unsolicited responses */ 566 566 + azx_writel(chip, GCTL, azx_readl(chip, GCTL) | ICH6_GCTL_UREN); 567 567 568 568 /* detect codecs */ 569 569 if (! chip->codec_mask) {

+2 -3

sound/pci/hda/patch_cmedia.c

reviewed

··· 408 408 /* search for an empty channel */ 409 409 for (j = 0; j < cfg->line_outs; j++) { 410 410 if (! assigned[j]) { 411 411 - spec->dac_nids[i] = i + 0x03; 411 411 + spec->dac_nids[i] = j + 0x03; 412 412 assigned[j] = 1; 413 413 break; 414 414 } ··· 444 444 len = snd_hda_get_connections(codec, nid, conn, 4); 445 445 for (k = 0; k < len; k++) 446 446 if (conn[k] == spec->dac_nids[i]) { 447 447 - spec->multi_init[j].param = j; 447 447 + spec->multi_init[j].param = k; 448 448 break; 449 449 } 450 450 j++; 451 451 - break; 452 451 } 453 452 } 454 453 return 0;

+22 -6

sound/pci/hda/patch_realtek.c

reviewed

··· 40 40 ALC880_W810, 41 41 ALC880_Z71V, 42 42 ALC880_AUTO, 43 43 + ALC880_6ST, 43 44 ALC880_6ST_DIG, 44 45 ALC880_F1734, 45 46 ALC880_ASUS, ··· 120 119 unsigned int num_kctl_alloc, num_kctl_used; 121 120 snd_kcontrol_new_t *kctl_alloc; 122 121 struct hda_input_mux private_imux; 122 122 + hda_nid_t private_dac_nids[4]; 123 123 }; 124 124 125 125 ··· 1549 1547 { .pci_subvendor = 0x8086, .pci_subdevice = 0xa100, .config = ALC880_5ST_DIG }, 1550 1548 { .pci_subvendor = 0x1565, .pci_subdevice = 0x8202, .config = ALC880_5ST_DIG }, 1551 1549 { .pci_subvendor = 0x1019, .pci_subdevice = 0xa880, .config = ALC880_5ST_DIG }, 1552 1552 - { .pci_subvendor = 0x1019, .pci_subdevice = 0xa884, .config = ALC880_5ST_DIG }, 1550 1550 + /* { .pci_subvendor = 0x1019, .pci_subdevice = 0xa884, .config = ALC880_5ST_DIG }, */ /* conflict with 6stack */ 1553 1551 { .pci_subvendor = 0x1695, .pci_subdevice = 0x400d, .config = ALC880_5ST_DIG }, 1554 1554 - { .pci_subvendor = 0x0000, .pci_subdevice = 0x8086, .config = ALC880_5ST_DIG }, 1552 1552 + /* note subvendor = 0 below */ 1553 1553 + /* { .pci_subvendor = 0x0000, .pci_subdevice = 0x8086, .config = ALC880_5ST_DIG }, */ 1555 1554 1556 1555 { .modelname = "w810", .config = ALC880_W810 }, 1557 1556 { .pci_subvendor = 0x161f, .pci_subdevice = 0x203d, .config = ALC880_W810 }, ··· 1560 1557 { .modelname = "z71v", .config = ALC880_Z71V }, 1561 1558 { .pci_subvendor = 0x1043, .pci_subdevice = 0x1964, .config = ALC880_Z71V }, 1562 1559 1563 1563 - { .modelname = "6statack-digout", .config = ALC880_6ST_DIG }, 1560 1560 + { .modelname = "6stack", .config = ALC880_6ST }, 1561 1561 + { .pci_subvendor = 0x1019, .pci_subdevice = 0xa884, .config = ALC880_6ST }, /* Acer APFV */ 1562 1562 + 1563 1563 + { .modelname = "6stack-digout", .config = ALC880_6ST_DIG }, 1564 1564 { .pci_subvendor = 0x2668, .pci_subdevice = 0x8086, .config = ALC880_6ST_DIG }, 1565 1565 { .pci_subvendor = 0x8086, .pci_subdevice = 0x2668, .config = ALC880_6ST_DIG }, 1566 1566 { .pci_subvendor = 0x1462, .pci_subdevice = 0x1150, .config = ALC880_6ST_DIG }, ··· 1650 1644 .channel_mode = alc880_fivestack_modes, 1651 1645 .input_mux = &alc880_capture_source, 1652 1646 }, 1647 1647 + [ALC880_6ST] = { 1648 1648 + .mixers = { alc880_six_stack_mixer }, 1649 1649 + .init_verbs = { alc880_volume_init_verbs, alc880_pin_6stack_init_verbs }, 1650 1650 + .num_dacs = ARRAY_SIZE(alc880_6st_dac_nids), 1651 1651 + .dac_nids = alc880_6st_dac_nids, 1652 1652 + .num_channel_mode = ARRAY_SIZE(alc880_sixstack_modes), 1653 1653 + .channel_mode = alc880_sixstack_modes, 1654 1654 + .input_mux = &alc880_6stack_capture_source, 1655 1655 + }, 1653 1656 [ALC880_6ST_DIG] = { 1654 1657 .mixers = { alc880_six_stack_mixer }, 1655 1658 .init_verbs = { alc880_volume_init_verbs, alc880_pin_6stack_init_verbs }, ··· 1671 1656 }, 1672 1657 [ALC880_W810] = { 1673 1658 .mixers = { alc880_w810_base_mixer }, 1674 1674 - .init_verbs = { alc880_volume_init_verbs, alc880_pin_w810_init_verbs }, 1659 1659 + .init_verbs = { alc880_volume_init_verbs, alc880_pin_w810_init_verbs, 1660 1660 + alc880_gpio2_init_verbs }, 1675 1661 .num_dacs = ARRAY_SIZE(alc880_w810_dac_nids), 1676 1662 .dac_nids = alc880_w810_dac_nids, 1677 1663 .dig_out_nid = ALC880_DIGOUT_NID, ··· 1682 1666 }, 1683 1667 [ALC880_Z71V] = { 1684 1668 .mixers = { alc880_z71v_mixer }, 1685 1685 - .init_verbs = { alc880_volume_init_verbs, alc880_pin_z71v_init_verbs, 1686 1686 - alc880_gpio2_init_verbs }, 1669 1669 + .init_verbs = { alc880_volume_init_verbs, alc880_pin_z71v_init_verbs }, 1687 1670 .num_dacs = ARRAY_SIZE(alc880_z71v_dac_nids), 1688 1671 .dac_nids = alc880_z71v_dac_nids, 1689 1672 .dig_out_nid = ALC880_DIGOUT_NID, ··· 1824 1809 int i, j; 1825 1810 1826 1811 memset(assigned, 0, sizeof(assigned)); 1812 1812 + spec->multiout.dac_nids = spec->private_dac_nids; 1827 1813 1828 1814 /* check the pins hardwired to audio widget */ 1829 1815 for (i = 0; i < cfg->line_outs; i++) {

+578 -240

sound/pci/hda/patch_sigmatel.c

reviewed

··· 30 30 #include <linux/slab.h> 31 31 #include <linux/pci.h> 32 32 #include <sound/core.h> 33 33 + #include <sound/asoundef.h> 33 34 #include "hda_codec.h" 34 35 #include "hda_local.h" 35 36 36 37 #undef STAC_TEST 37 38 39 39 + #define NUM_CONTROL_ALLOC 32 40 40 + #define STAC_HP_EVENT 0x37 41 41 + #define STAC_UNSOL_ENABLE (AC_USRSP_EN | STAC_HP_EVENT) 42 42 + 38 43 struct sigmatel_spec { 44 44 + snd_kcontrol_new_t *mixers[4]; 45 45 + unsigned int num_mixers; 46 46 + 47 47 + unsigned int surr_switch: 1; 48 48 + 39 49 /* playback */ 40 50 struct hda_multi_out multiout; 41 41 - hda_nid_t playback_nid; 51 51 + hda_nid_t dac_nids[4]; 42 52 43 53 /* capture */ 44 54 hda_nid_t *adc_nids; 45 55 unsigned int num_adcs; 46 56 hda_nid_t *mux_nids; 47 57 unsigned int num_muxes; 48 48 - hda_nid_t capture_nid; 49 58 hda_nid_t dig_in_nid; 50 59 51 51 - /* power management*/ 52 52 - hda_nid_t *pstate_nids; 53 53 - unsigned int num_pstates; 54 54 - 60 60 + #ifdef STAC_TEST 55 61 /* pin widgets */ 56 62 hda_nid_t *pin_nids; 57 63 unsigned int num_pins; 58 58 - #ifdef STAC_TEST 59 64 unsigned int *pin_configs; 60 65 #endif 61 66 ··· 69 64 snd_kcontrol_new_t *mixer; 70 65 71 66 /* capture source */ 72 72 - struct hda_input_mux input_mux; 73 73 - char input_labels[HDA_MAX_NUM_INPUTS][16]; 67 67 + struct hda_input_mux *input_mux; 74 68 unsigned int cur_mux[2]; 75 69 76 70 /* channel mode */ 77 71 unsigned int num_ch_modes; 78 72 unsigned int cur_ch_mode; 79 79 - const struct sigmatel_channel_mode *channel_modes; 80 73 81 81 - struct hda_pcm pcm_rec[1]; /* PCM information */ 74 74 + struct hda_pcm pcm_rec[2]; /* PCM information */ 75 75 + 76 76 + /* dynamic controls and input_mux */ 77 77 + struct auto_pin_cfg autocfg; 78 78 + unsigned int num_kctl_alloc, num_kctl_used; 79 79 + snd_kcontrol_new_t *kctl_alloc; 80 80 + struct hda_input_mux private_imux; 82 81 }; 83 82 84 83 static hda_nid_t stac9200_adc_nids[1] = { ··· 97 88 0x02, 98 89 }; 99 90 100 100 - static hda_nid_t stac9200_pstate_nids[3] = { 101 101 - 0x01, 0x02, 0x03, 102 102 - }; 103 103 - 104 104 - static hda_nid_t stac9200_pin_nids[8] = { 105 105 - 0x08, 0x09, 0x0d, 0x0e, 0x0f, 0x10, 0x11, 0x12, 106 106 - }; 107 107 - 108 91 static hda_nid_t stac922x_adc_nids[2] = { 109 92 0x06, 0x07, 110 93 }; ··· 105 104 0x12, 0x13, 106 105 }; 107 106 108 108 - static hda_nid_t stac922x_dac_nids[4] = { 109 109 - 0x02, 0x03, 0x04, 0x05, 110 110 - }; 111 111 - 112 112 - static hda_nid_t stac922x_pstate_nids[8] = { 113 113 - 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x11, 107 107 + #ifdef STAC_TEST 108 108 + static hda_nid_t stac9200_pin_nids[8] = { 109 109 + 0x08, 0x09, 0x0d, 0x0e, 0x0f, 0x10, 0x11, 0x12, 114 110 }; 115 111 116 112 static hda_nid_t stac922x_pin_nids[10] = { 117 113 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 118 114 0x0f, 0x10, 0x11, 0x15, 0x1b, 119 115 }; 116 116 + #endif 120 117 121 118 static int stac92xx_mux_enum_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t *uinfo) 122 119 { 123 120 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 124 121 struct sigmatel_spec *spec = codec->spec; 125 125 - return snd_hda_input_mux_info(&spec->input_mux, uinfo); 122 122 + return snd_hda_input_mux_info(spec->input_mux, uinfo); 126 123 } 127 124 128 125 static int stac92xx_mux_enum_get(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol) ··· 139 140 struct sigmatel_spec *spec = codec->spec; 140 141 unsigned int adc_idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id); 141 142 142 142 - return snd_hda_input_mux_put(codec, &spec->input_mux, ucontrol, 143 143 + return snd_hda_input_mux_put(codec, spec->input_mux, ucontrol, 143 144 spec->mux_nids[adc_idx], &spec->cur_mux[adc_idx]); 144 145 } 145 146 146 146 - static struct hda_verb stac9200_ch2_init[] = { 147 147 + static struct hda_verb stac9200_core_init[] = { 147 148 /* set dac0mux for dac converter */ 148 148 - { 0x07, 0x701, 0x00}, 149 149 + { 0x07, AC_VERB_SET_CONNECT_SEL, 0x00}, 149 150 {} 150 151 }; 151 152 152 152 - static struct hda_verb stac922x_ch2_init[] = { 153 153 + static struct hda_verb stac922x_core_init[] = { 153 154 /* set master volume and direct control */ 154 154 - { 0x16, 0x70f, 0xff}, 155 155 + { 0x16, AC_VERB_SET_VOLUME_KNOB_CONTROL, 0xff}, 155 156 {} 156 157 }; 157 158 158 158 - struct sigmatel_channel_mode { 159 159 - unsigned int channels; 160 160 - const struct hda_verb *sequence; 161 161 - }; 159 159 + static int stac922x_channel_modes[3] = {2, 6, 8}; 160 160 + 161 161 + static int stac922x_ch_mode_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t *uinfo) 162 162 + { 163 163 + struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 164 164 + struct sigmatel_spec *spec = codec->spec; 165 165 + 166 166 + uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 167 167 + uinfo->count = 1; 168 168 + uinfo->value.enumerated.items = spec->num_ch_modes; 169 169 + if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) 170 170 + uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1; 171 171 + sprintf(uinfo->value.enumerated.name, "%dch", 172 172 + stac922x_channel_modes[uinfo->value.enumerated.item]); 173 173 + return 0; 174 174 + } 175 175 + 176 176 + static int stac922x_ch_mode_get(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol) 177 177 + { 178 178 + struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 179 179 + struct sigmatel_spec *spec = codec->spec; 180 180 + 181 181 + ucontrol->value.enumerated.item[0] = spec->cur_ch_mode; 182 182 + return 0; 183 183 + } 184 184 + 185 185 + static int stac922x_ch_mode_put(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol) 186 186 + { 187 187 + struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 188 188 + struct sigmatel_spec *spec = codec->spec; 189 189 + 190 190 + if (ucontrol->value.enumerated.item[0] >= spec->num_ch_modes) 191 191 + ucontrol->value.enumerated.item[0] = spec->num_ch_modes; 192 192 + if (ucontrol->value.enumerated.item[0] == spec->cur_ch_mode && 193 193 + ! codec->in_resume) 194 194 + return 0; 195 195 + 196 196 + spec->cur_ch_mode = ucontrol->value.enumerated.item[0]; 197 197 + spec->multiout.max_channels = stac922x_channel_modes[spec->cur_ch_mode]; 198 198 + 199 199 + return 1; 200 200 + } 162 201 163 202 static snd_kcontrol_new_t stac9200_mixer[] = { 164 203 HDA_CODEC_VOLUME("Master Playback Volume", 0xb, 0, HDA_OUTPUT), ··· 211 174 }, 212 175 HDA_CODEC_VOLUME("Capture Volume", 0x0a, 0, HDA_OUTPUT), 213 176 HDA_CODEC_MUTE("Capture Switch", 0x0a, 0, HDA_OUTPUT), 214 214 - HDA_CODEC_VOLUME("Input Mux Volume", 0x0c, 0, HDA_OUTPUT), 177 177 + HDA_CODEC_VOLUME("Capture Mux Volume", 0x0c, 0, HDA_OUTPUT), 215 178 { } /* end */ 216 179 }; 217 180 181 181 + /* This needs to be generated dynamically based on sequence */ 218 182 static snd_kcontrol_new_t stac922x_mixer[] = { 219 219 - HDA_CODEC_VOLUME("PCM Playback Volume", 0x2, 0x0, HDA_OUTPUT), 220 220 - HDA_CODEC_MUTE("PCM Playback Switch", 0x2, 0x0, HDA_OUTPUT), 221 183 { 222 184 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 223 185 .name = "Input Source", ··· 231 195 { } /* end */ 232 196 }; 233 197 198 198 + static snd_kcontrol_new_t stac922x_ch_mode_mixer[] = { 199 199 + { 200 200 + .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 201 201 + .name = "Channel Mode", 202 202 + .info = stac922x_ch_mode_info, 203 203 + .get = stac922x_ch_mode_get, 204 204 + .put = stac922x_ch_mode_put, 205 205 + }, 206 206 + { } /* end */ 207 207 + }; 208 208 + 234 209 static int stac92xx_build_controls(struct hda_codec *codec) 235 210 { 236 211 struct sigmatel_spec *spec = codec->spec; 237 212 int err; 213 213 + int i; 238 214 239 215 err = snd_hda_add_new_ctls(codec, spec->mixer); 240 216 if (err < 0) 241 217 return err; 218 218 + 219 219 + for (i = 0; i < spec->num_mixers; i++) { 220 220 + err = snd_hda_add_new_ctls(codec, spec->mixers[i]); 221 221 + if (err < 0) 222 222 + return err; 223 223 + } 224 224 + 225 225 + if (spec->surr_switch) { 226 226 + err = snd_hda_add_new_ctls(codec, stac922x_ch_mode_mixer); 227 227 + if (err < 0) 228 228 + return err; 229 229 + } 242 230 if (spec->multiout.dig_out_nid) { 243 231 err = snd_hda_create_spdif_out_ctls(codec, spec->multiout.dig_out_nid); 244 232 if (err < 0) ··· 282 222 0x02a19020, 0x01a19021, 0x90100140, 0x01813122, 283 223 }; 284 224 285 285 - static unsigned int stac922x_pin_configs[14] = { 286 286 - 0x40000100, 0x40000100, 0x40000100, 0x01114010, 287 287 - 0x01813122, 0x40000100, 0x01447010, 0x01c47010, 225 225 + static unsigned int stac922x_pin_configs[10] = { 226 226 + 0x01014010, 0x01014011, 0x01014012, 0x0221401f, 227 227 + 0x01813122, 0x01014014, 0x01441030, 0x01c41030, 288 228 0x40000100, 0x40000100, 289 229 }; 290 230 ··· 315 255 } 316 256 #endif 317 257 318 318 - static int stac92xx_set_pinctl(struct hda_codec *codec, hda_nid_t nid, unsigned int value) 319 319 - { 320 320 - unsigned int pin_ctl; 321 321 - 322 322 - pin_ctl = snd_hda_codec_read(codec, nid, 0, 323 323 - AC_VERB_GET_PIN_WIDGET_CONTROL, 324 324 - 0x00); 325 325 - snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_PIN_WIDGET_CONTROL, 326 326 - pin_ctl | value); 327 327 - 328 328 - return 0; 329 329 - } 330 330 - 331 331 - static int stac92xx_set_vref(struct hda_codec *codec, hda_nid_t nid) 332 332 - { 333 333 - unsigned int vref_caps = snd_hda_param_read(codec, nid, AC_PAR_PIN_CAP) >> AC_PINCAP_VREF_SHIFT; 334 334 - unsigned int vref_ctl = AC_PINCTL_VREF_HIZ; 335 335 - 336 336 - if (vref_caps & AC_PINCAP_VREF_100) 337 337 - vref_ctl = AC_PINCTL_VREF_100; 338 338 - else if (vref_caps & AC_PINCAP_VREF_80) 339 339 - vref_ctl = AC_PINCTL_VREF_80; 340 340 - else if (vref_caps & AC_PINCAP_VREF_50) 341 341 - vref_ctl = AC_PINCTL_VREF_50; 342 342 - else if (vref_caps & AC_PINCAP_VREF_GRD) 343 343 - vref_ctl = AC_PINCTL_VREF_GRD; 344 344 - 345 345 - stac92xx_set_pinctl(codec, nid, vref_ctl); 346 346 - 347 347 - return 0; 348 348 - } 349 349 - 350 350 - /* 351 351 - * retrieve the default device type from the default config value 352 352 - */ 353 353 - #define get_defcfg_type(cfg) ((cfg & AC_DEFCFG_DEVICE) >> AC_DEFCFG_DEVICE_SHIFT) 354 354 - #define get_defcfg_location(cfg) ((cfg & AC_DEFCFG_LOCATION) >> AC_DEFCFG_LOCATION_SHIFT) 355 355 - 356 356 - static int stac92xx_config_pin(struct hda_codec *codec, hda_nid_t nid, unsigned int pin_cfg) 357 357 - { 358 358 - struct sigmatel_spec *spec = codec->spec; 359 359 - u32 location = get_defcfg_location(pin_cfg); 360 360 - char *label; 361 361 - const char *type = NULL; 362 362 - int ainput = 0; 363 363 - 364 364 - switch(get_defcfg_type(pin_cfg)) { 365 365 - case AC_JACK_HP_OUT: 366 366 - /* Enable HP amp */ 367 367 - stac92xx_set_pinctl(codec, nid, AC_PINCTL_HP_EN); 368 368 - /* Fall through */ 369 369 - case AC_JACK_SPDIF_OUT: 370 370 - case AC_JACK_LINE_OUT: 371 371 - case AC_JACK_SPEAKER: 372 372 - /* Enable output */ 373 373 - stac92xx_set_pinctl(codec, nid, AC_PINCTL_OUT_EN); 374 374 - break; 375 375 - case AC_JACK_SPDIF_IN: 376 376 - stac92xx_set_pinctl(codec, nid, AC_PINCTL_IN_EN); 377 377 - break; 378 378 - case AC_JACK_MIC_IN: 379 379 - if ((location & 0x0f) == AC_JACK_LOC_FRONT) 380 380 - type = "Front Mic"; 381 381 - else 382 382 - type = "Mic"; 383 383 - ainput = 1; 384 384 - /* Set vref */ 385 385 - stac92xx_set_vref(codec, nid); 386 386 - stac92xx_set_pinctl(codec, nid, AC_PINCTL_IN_EN); 387 387 - break; 388 388 - case AC_JACK_CD: 389 389 - type = "CD"; 390 390 - ainput = 1; 391 391 - stac92xx_set_pinctl(codec, nid, AC_PINCTL_IN_EN); 392 392 - break; 393 393 - case AC_JACK_LINE_IN: 394 394 - if ((location & 0x0f) == AC_JACK_LOC_FRONT) 395 395 - type = "Front Line"; 396 396 - else 397 397 - type = "Line"; 398 398 - ainput = 1; 399 399 - stac92xx_set_pinctl(codec, nid, AC_PINCTL_IN_EN); 400 400 - break; 401 401 - case AC_JACK_AUX: 402 402 - if ((location & 0x0f) == AC_JACK_LOC_FRONT) 403 403 - type = "Front Aux"; 404 404 - else 405 405 - type = "Aux"; 406 406 - ainput = 1; 407 407 - stac92xx_set_pinctl(codec, nid, AC_PINCTL_IN_EN); 408 408 - break; 409 409 - } 410 410 - 411 411 - if (ainput) { 412 412 - hda_nid_t con_lst[HDA_MAX_NUM_INPUTS]; 413 413 - int i, j, num_cons, index = -1; 414 414 - if (!type) 415 415 - type = "Input"; 416 416 - label = spec->input_labels[spec->input_mux.num_items]; 417 417 - strcpy(label, type); 418 418 - spec->input_mux.items[spec->input_mux.num_items].label = label; 419 419 - for (i=0; i<spec->num_muxes; i++) { 420 420 - num_cons = snd_hda_get_connections(codec, spec->mux_nids[i], con_lst, HDA_MAX_NUM_INPUTS); 421 421 - for (j=0; j<num_cons; j++) 422 422 - if (con_lst[j] == nid) { 423 423 - index = j; 424 424 - break; 425 425 - } 426 426 - if (index >= 0) 427 427 - break; 428 428 - } 429 429 - spec->input_mux.items[spec->input_mux.num_items].index = index; 430 430 - spec->input_mux.num_items++; 431 431 - } 432 432 - 433 433 - return 0; 434 434 - } 435 435 - 436 436 - static int stac92xx_config_pins(struct hda_codec *codec) 437 437 - { 438 438 - struct sigmatel_spec *spec = codec->spec; 439 439 - int i; 440 440 - unsigned int pin_cfg; 441 441 - 442 442 - for (i=0; i < spec->num_pins; i++) { 443 443 - /* Default to disabled */ 444 444 - snd_hda_codec_write(codec, spec->pin_nids[i], 0, 445 445 - AC_VERB_SET_PIN_WIDGET_CONTROL, 446 446 - 0x00); 447 447 - 448 448 - pin_cfg = snd_hda_codec_read(codec, spec->pin_nids[i], 0, 449 449 - AC_VERB_GET_CONFIG_DEFAULT, 450 450 - 0x00); 451 451 - if (((pin_cfg & AC_DEFCFG_PORT_CONN) >> AC_DEFCFG_PORT_CONN_SHIFT) == AC_JACK_PORT_NONE) 452 452 - continue; /* Move on */ 453 453 - 454 454 - stac92xx_config_pin(codec, spec->pin_nids[i], pin_cfg); 455 455 - } 456 456 - 457 457 - return 0; 458 458 - } 459 459 - 460 460 - static int stac92xx_init(struct hda_codec *codec) 461 461 - { 462 462 - struct sigmatel_spec *spec = codec->spec; 463 463 - int i; 464 464 - 465 465 - for (i=0; i < spec->num_pstates; i++) 466 466 - snd_hda_codec_write(codec, spec->pstate_nids[i], 0, 467 467 - AC_VERB_SET_POWER_STATE, 0x00); 468 468 - 469 469 - mdelay(100); 470 470 - 471 471 - snd_hda_sequence_write(codec, spec->init); 472 472 - 473 473 - #ifdef STAC_TEST 474 474 - stac92xx_set_config_regs(codec); 475 475 - #endif 476 476 - 477 477 - stac92xx_config_pins(codec); 478 478 - 479 479 - return 0; 480 480 - } 481 481 - 482 258 /* 483 259 * Analog playback callbacks 484 260 */ ··· 326 430 return snd_hda_multi_out_analog_open(codec, &spec->multiout, substream); 327 431 } 328 432 433 433 + /* 434 434 + * set up the i/o for analog out 435 435 + * when the digital out is available, copy the front out to digital out, too. 436 436 + */ 437 437 + static int stac92xx_multi_out_analog_prepare(struct hda_codec *codec, struct hda_multi_out *mout, 438 438 + unsigned int stream_tag, 439 439 + unsigned int format, 440 440 + snd_pcm_substream_t *substream) 441 441 + { 442 442 + hda_nid_t *nids = mout->dac_nids; 443 443 + int chs = substream->runtime->channels; 444 444 + int i; 445 445 + 446 446 + down(&codec->spdif_mutex); 447 447 + if (mout->dig_out_nid && mout->dig_out_used != HDA_DIG_EXCLUSIVE) { 448 448 + if (chs == 2 && 449 449 + snd_hda_is_supported_format(codec, mout->dig_out_nid, format) && 450 450 + ! (codec->spdif_status & IEC958_AES0_NONAUDIO)) { 451 451 + mout->dig_out_used = HDA_DIG_ANALOG_DUP; 452 452 + /* setup digital receiver */ 453 453 + snd_hda_codec_setup_stream(codec, mout->dig_out_nid, 454 454 + stream_tag, 0, format); 455 455 + } else { 456 456 + mout->dig_out_used = 0; 457 457 + snd_hda_codec_setup_stream(codec, mout->dig_out_nid, 0, 0, 0); 458 458 + } 459 459 + } 460 460 + up(&codec->spdif_mutex); 461 461 + 462 462 + /* front */ 463 463 + snd_hda_codec_setup_stream(codec, nids[HDA_FRONT], stream_tag, 0, format); 464 464 + if (mout->hp_nid) 465 465 + /* headphone out will just decode front left/right (stereo) */ 466 466 + snd_hda_codec_setup_stream(codec, mout->hp_nid, stream_tag, 0, format); 467 467 + /* surrounds */ 468 468 + if (mout->max_channels > 2) 469 469 + for (i = 1; i < mout->num_dacs; i++) { 470 470 + if ((mout->max_channels == 6) && (i == 3)) 471 471 + break; 472 472 + if (chs >= (i + 1) * 2) /* independent out */ 473 473 + snd_hda_codec_setup_stream(codec, nids[i], stream_tag, i * 2, 474 474 + format); 475 475 + else /* copy front */ 476 476 + snd_hda_codec_setup_stream(codec, nids[i], stream_tag, 0, 477 477 + format); 478 478 + } 479 479 + return 0; 480 480 + } 481 481 + 482 482 + 329 483 static int stac92xx_playback_pcm_prepare(struct hda_pcm_stream *hinfo, 330 484 struct hda_codec *codec, 331 485 unsigned int stream_tag, ··· 383 437 snd_pcm_substream_t *substream) 384 438 { 385 439 struct sigmatel_spec *spec = codec->spec; 386 386 - return snd_hda_multi_out_analog_prepare(codec, &spec->multiout, stream_tag, 440 440 + return stac92xx_multi_out_analog_prepare(codec, &spec->multiout, stream_tag, 387 441 format, substream); 388 442 } 389 443 ··· 462 516 static struct hda_pcm_stream stac92xx_pcm_analog_playback = { 463 517 .substreams = 1, 464 518 .channels_min = 2, 465 465 - .channels_max = 2, 519 519 + .channels_max = 8, 466 520 .nid = 0x02, /* NID to query formats and rates */ 467 521 .ops = { 468 522 .open = stac92xx_playback_pcm_open, ··· 490 544 codec->num_pcms = 1; 491 545 codec->pcm_info = info; 492 546 493 493 - info->name = "STAC92xx"; 547 547 + info->name = "STAC92xx Analog"; 494 548 info->stream[SNDRV_PCM_STREAM_PLAYBACK] = stac92xx_pcm_analog_playback; 495 495 - info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->playback_nid; 496 549 info->stream[SNDRV_PCM_STREAM_CAPTURE] = stac92xx_pcm_analog_capture; 497 497 - info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->capture_nid; 498 550 499 551 if (spec->multiout.dig_out_nid || spec->dig_in_nid) { 500 552 codec->num_pcms++; ··· 511 567 return 0; 512 568 } 513 569 570 570 + enum { 571 571 + STAC_CTL_WIDGET_VOL, 572 572 + STAC_CTL_WIDGET_MUTE, 573 573 + }; 574 574 + 575 575 + static snd_kcontrol_new_t stac92xx_control_templates[] = { 576 576 + HDA_CODEC_VOLUME(NULL, 0, 0, 0), 577 577 + HDA_CODEC_MUTE(NULL, 0, 0, 0), 578 578 + }; 579 579 + 580 580 + /* add dynamic controls */ 581 581 + static int stac92xx_add_control(struct sigmatel_spec *spec, int type, const char *name, unsigned long val) 582 582 + { 583 583 + snd_kcontrol_new_t *knew; 584 584 + 585 585 + if (spec->num_kctl_used >= spec->num_kctl_alloc) { 586 586 + int num = spec->num_kctl_alloc + NUM_CONTROL_ALLOC; 587 587 + 588 588 + knew = kcalloc(num + 1, sizeof(*knew), GFP_KERNEL); /* array + terminator */ 589 589 + if (! knew) 590 590 + return -ENOMEM; 591 591 + if (spec->kctl_alloc) { 592 592 + memcpy(knew, spec->kctl_alloc, sizeof(*knew) * spec->num_kctl_alloc); 593 593 + kfree(spec->kctl_alloc); 594 594 + } 595 595 + spec->kctl_alloc = knew; 596 596 + spec->num_kctl_alloc = num; 597 597 + } 598 598 + 599 599 + knew = &spec->kctl_alloc[spec->num_kctl_used]; 600 600 + *knew = stac92xx_control_templates[type]; 601 601 + knew->name = kstrdup(name, GFP_KERNEL); 602 602 + if (! knew->name) 603 603 + return -ENOMEM; 604 604 + knew->private_value = val; 605 605 + spec->num_kctl_used++; 606 606 + return 0; 607 607 + } 608 608 + 609 609 + /* fill in the dac_nids table from the parsed pin configuration */ 610 610 + static int stac92xx_auto_fill_dac_nids(struct hda_codec *codec, const struct auto_pin_cfg *cfg) 611 611 + { 612 612 + struct sigmatel_spec *spec = codec->spec; 613 613 + hda_nid_t nid; 614 614 + int i; 615 615 + 616 616 + /* check the pins hardwired to audio widget */ 617 617 + for (i = 0; i < cfg->line_outs; i++) { 618 618 + nid = cfg->line_out_pins[i]; 619 619 + spec->multiout.dac_nids[i] = snd_hda_codec_read(codec, nid, 0, 620 620 + AC_VERB_GET_CONNECT_LIST, 0) & 0xff; 621 621 + } 622 622 + 623 623 + spec->multiout.num_dacs = cfg->line_outs; 624 624 + 625 625 + return 0; 626 626 + } 627 627 + 628 628 + /* add playback controls from the parsed DAC table */ 629 629 + static int stac92xx_auto_create_multi_out_ctls(struct sigmatel_spec *spec, const struct auto_pin_cfg *cfg) 630 630 + { 631 631 + char name[32]; 632 632 + static const char *chname[4] = { "Front", "Surround", NULL /*CLFE*/, "Side" }; 633 633 + hda_nid_t nid; 634 634 + int i, err; 635 635 + 636 636 + for (i = 0; i < cfg->line_outs; i++) { 637 637 + if (! spec->multiout.dac_nids[i]) 638 638 + continue; 639 639 + 640 640 + nid = spec->multiout.dac_nids[i]; 641 641 + 642 642 + if (i == 2) { 643 643 + /* Center/LFE */ 644 644 + if ((err = stac92xx_add_control(spec, STAC_CTL_WIDGET_VOL, "Center Playback Volume", 645 645 + HDA_COMPOSE_AMP_VAL(nid, 1, 0, HDA_OUTPUT))) < 0) 646 646 + return err; 647 647 + if ((err = stac92xx_add_control(spec, STAC_CTL_WIDGET_VOL, "LFE Playback Volume", 648 648 + HDA_COMPOSE_AMP_VAL(nid, 2, 0, HDA_OUTPUT))) < 0) 649 649 + return err; 650 650 + if ((err = stac92xx_add_control(spec, STAC_CTL_WIDGET_MUTE, "Center Playback Switch", 651 651 + HDA_COMPOSE_AMP_VAL(nid, 1, 0, HDA_OUTPUT))) < 0) 652 652 + return err; 653 653 + if ((err = stac92xx_add_control(spec, STAC_CTL_WIDGET_MUTE, "LFE Playback Switch", 654 654 + HDA_COMPOSE_AMP_VAL(nid, 2, 0, HDA_OUTPUT))) < 0) 655 655 + return err; 656 656 + } else { 657 657 + sprintf(name, "%s Playback Volume", chname[i]); 658 658 + if ((err = stac92xx_add_control(spec, STAC_CTL_WIDGET_VOL, name, 659 659 + HDA_COMPOSE_AMP_VAL(nid, 3, 0, HDA_OUTPUT))) < 0) 660 660 + return err; 661 661 + sprintf(name, "%s Playback Switch", chname[i]); 662 662 + if ((err = stac92xx_add_control(spec, STAC_CTL_WIDGET_MUTE, name, 663 663 + HDA_COMPOSE_AMP_VAL(nid, 3, 0, HDA_OUTPUT))) < 0) 664 664 + return err; 665 665 + } 666 666 + } 667 667 + 668 668 + return 0; 669 669 + } 670 670 + 671 671 + /* add playback controls for HP output */ 672 672 + static int stac92xx_auto_create_hp_ctls(struct hda_codec *codec, struct auto_pin_cfg *cfg) 673 673 + { 674 674 + struct sigmatel_spec *spec = codec->spec; 675 675 + hda_nid_t pin = cfg->hp_pin; 676 676 + hda_nid_t nid; 677 677 + int i, err; 678 678 + unsigned int wid_caps; 679 679 + 680 680 + if (! pin) 681 681 + return 0; 682 682 + 683 683 + wid_caps = snd_hda_param_read(codec, pin, AC_PAR_AUDIO_WIDGET_CAP); 684 684 + if (wid_caps & AC_WCAP_UNSOL_CAP) 685 685 + /* Enable unsolicited responses on the HP widget */ 686 686 + snd_hda_codec_write(codec, pin, 0, 687 687 + AC_VERB_SET_UNSOLICITED_ENABLE, 688 688 + STAC_UNSOL_ENABLE); 689 689 + 690 690 + nid = snd_hda_codec_read(codec, pin, 0, AC_VERB_GET_CONNECT_LIST, 0) & 0xff; 691 691 + for (i = 0; i < cfg->line_outs; i++) { 692 692 + if (! spec->multiout.dac_nids[i]) 693 693 + continue; 694 694 + if (spec->multiout.dac_nids[i] == nid) 695 695 + return 0; 696 696 + } 697 697 + 698 698 + spec->multiout.hp_nid = nid; 699 699 + 700 700 + /* control HP volume/switch on the output mixer amp */ 701 701 + if ((err = stac92xx_add_control(spec, STAC_CTL_WIDGET_VOL, "Headphone Playback Volume", 702 702 + HDA_COMPOSE_AMP_VAL(nid, 3, 0, HDA_OUTPUT))) < 0) 703 703 + return err; 704 704 + if ((err = stac92xx_add_control(spec, STAC_CTL_WIDGET_MUTE, "Headphone Playback Switch", 705 705 + HDA_COMPOSE_AMP_VAL(nid, 3, 0, HDA_OUTPUT))) < 0) 706 706 + return err; 707 707 + 708 708 + return 0; 709 709 + } 710 710 + 711 711 + /* create playback/capture controls for input pins */ 712 712 + static int stac92xx_auto_create_analog_input_ctls(struct hda_codec *codec, const struct auto_pin_cfg *cfg) 713 713 + { 714 714 + struct sigmatel_spec *spec = codec->spec; 715 715 + static char *labels[AUTO_PIN_LAST] = { 716 716 + "Mic", "Front Mic", "Line", "Front Line", "CD", "Aux" 717 717 + }; 718 718 + struct hda_input_mux *imux = &spec->private_imux; 719 719 + hda_nid_t con_lst[HDA_MAX_NUM_INPUTS]; 720 720 + int i, j, k; 721 721 + 722 722 + for (i = 0; i < AUTO_PIN_LAST; i++) { 723 723 + int index = -1; 724 724 + if (cfg->input_pins[i]) { 725 725 + imux->items[imux->num_items].label = labels[i]; 726 726 + 727 727 + for (j=0; j<spec->num_muxes; j++) { 728 728 + int num_cons = snd_hda_get_connections(codec, spec->mux_nids[j], con_lst, HDA_MAX_NUM_INPUTS); 729 729 + for (k=0; k<num_cons; k++) 730 730 + if (con_lst[k] == cfg->input_pins[i]) { 731 731 + index = k; 732 732 + break; 733 733 + } 734 734 + if (index >= 0) 735 735 + break; 736 736 + } 737 737 + imux->items[imux->num_items].index = index; 738 738 + imux->num_items++; 739 739 + } 740 740 + } 741 741 + 742 742 + return 0; 743 743 + } 744 744 + 745 745 + static void stac92xx_auto_set_pinctl(struct hda_codec *codec, hda_nid_t nid, int pin_type) 746 746 + 747 747 + { 748 748 + snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_PIN_WIDGET_CONTROL, pin_type); 749 749 + } 750 750 + 751 751 + static void stac92xx_auto_init_multi_out(struct hda_codec *codec) 752 752 + { 753 753 + struct sigmatel_spec *spec = codec->spec; 754 754 + int i; 755 755 + 756 756 + for (i = 0; i < spec->autocfg.line_outs; i++) { 757 757 + hda_nid_t nid = spec->autocfg.line_out_pins[i]; 758 758 + stac92xx_auto_set_pinctl(codec, nid, AC_PINCTL_OUT_EN); 759 759 + } 760 760 + } 761 761 + 762 762 + static void stac92xx_auto_init_hp_out(struct hda_codec *codec) 763 763 + { 764 764 + struct sigmatel_spec *spec = codec->spec; 765 765 + hda_nid_t pin; 766 766 + 767 767 + pin = spec->autocfg.hp_pin; 768 768 + if (pin) /* connect to front */ 769 769 + stac92xx_auto_set_pinctl(codec, pin, AC_PINCTL_OUT_EN | AC_PINCTL_HP_EN); 770 770 + } 771 771 + 772 772 + static int stac922x_parse_auto_config(struct hda_codec *codec) 773 773 + { 774 774 + struct sigmatel_spec *spec = codec->spec; 775 775 + int err; 776 776 + 777 777 + if ((err = snd_hda_parse_pin_def_config(codec, &spec->autocfg)) < 0) 778 778 + return err; 779 779 + if ((err = stac92xx_auto_fill_dac_nids(codec, &spec->autocfg)) < 0) 780 780 + return err; 781 781 + if (! spec->autocfg.line_outs && ! spec->autocfg.hp_pin) 782 782 + return 0; /* can't find valid pin config */ 783 783 + 784 784 + if ((err = stac92xx_auto_create_multi_out_ctls(spec, &spec->autocfg)) < 0 || 785 785 + (err = stac92xx_auto_create_hp_ctls(codec, &spec->autocfg)) < 0 || 786 786 + (err = stac92xx_auto_create_analog_input_ctls(codec, &spec->autocfg)) < 0) 787 787 + return err; 788 788 + 789 789 + spec->multiout.max_channels = spec->multiout.num_dacs * 2; 790 790 + if (spec->multiout.max_channels > 2) { 791 791 + spec->surr_switch = 1; 792 792 + spec->cur_ch_mode = 1; 793 793 + spec->num_ch_modes = 2; 794 794 + if (spec->multiout.max_channels == 8) { 795 795 + spec->cur_ch_mode++; 796 796 + spec->num_ch_modes++; 797 797 + } 798 798 + } 799 799 + 800 800 + if (spec->autocfg.dig_out_pin) { 801 801 + spec->multiout.dig_out_nid = 0x08; 802 802 + stac92xx_auto_set_pinctl(codec, spec->autocfg.dig_out_pin, AC_PINCTL_OUT_EN); 803 803 + } 804 804 + if (spec->autocfg.dig_in_pin) { 805 805 + spec->dig_in_nid = 0x09; 806 806 + stac92xx_auto_set_pinctl(codec, spec->autocfg.dig_in_pin, AC_PINCTL_IN_EN); 807 807 + } 808 808 + 809 809 + if (spec->kctl_alloc) 810 810 + spec->mixers[spec->num_mixers++] = spec->kctl_alloc; 811 811 + 812 812 + spec->input_mux = &spec->private_imux; 813 813 + 814 814 + return 1; 815 815 + } 816 816 + 817 817 + static int stac9200_parse_auto_config(struct hda_codec *codec) 818 818 + { 819 819 + struct sigmatel_spec *spec = codec->spec; 820 820 + int err; 821 821 + 822 822 + if ((err = snd_hda_parse_pin_def_config(codec, &spec->autocfg)) < 0) 823 823 + return err; 824 824 + 825 825 + if ((err = stac92xx_auto_create_analog_input_ctls(codec, &spec->autocfg)) < 0) 826 826 + return err; 827 827 + 828 828 + if (spec->autocfg.dig_out_pin) { 829 829 + spec->multiout.dig_out_nid = 0x05; 830 830 + stac92xx_auto_set_pinctl(codec, spec->autocfg.dig_out_pin, AC_PINCTL_OUT_EN); 831 831 + } 832 832 + if (spec->autocfg.dig_in_pin) { 833 833 + spec->dig_in_nid = 0x04; 834 834 + stac92xx_auto_set_pinctl(codec, spec->autocfg.dig_in_pin, AC_PINCTL_IN_EN); 835 835 + } 836 836 + 837 837 + if (spec->kctl_alloc) 838 838 + spec->mixers[spec->num_mixers++] = spec->kctl_alloc; 839 839 + 840 840 + spec->input_mux = &spec->private_imux; 841 841 + 842 842 + return 1; 843 843 + } 844 844 + 845 845 + static int stac92xx_init_pstate(struct hda_codec *codec) 846 846 + { 847 847 + hda_nid_t nid, nid_start; 848 848 + int nodes; 849 849 + 850 850 + snd_hda_codec_write(codec, 0x01, 0, AC_VERB_SET_POWER_STATE, 0x00); 851 851 + 852 852 + nodes = snd_hda_get_sub_nodes(codec, codec->afg, &nid_start); 853 853 + for (nid = nid_start; nid < nodes + nid_start; nid++) { 854 854 + unsigned int wid_caps = snd_hda_param_read(codec, nid, 855 855 + AC_PAR_AUDIO_WIDGET_CAP); 856 856 + if (wid_caps & AC_WCAP_POWER) 857 857 + snd_hda_codec_write(codec, nid, 0, 858 858 + AC_VERB_SET_POWER_STATE, 0x00); 859 859 + } 860 860 + 861 861 + mdelay(100); 862 862 + 863 863 + return 0; 864 864 + } 865 865 + 866 866 + static int stac92xx_init(struct hda_codec *codec) 867 867 + { 868 868 + struct sigmatel_spec *spec = codec->spec; 869 869 + 870 870 + stac92xx_init_pstate(codec); 871 871 + 872 872 + snd_hda_sequence_write(codec, spec->init); 873 873 + 874 874 + stac92xx_auto_init_multi_out(codec); 875 875 + stac92xx_auto_init_hp_out(codec); 876 876 + 877 877 + return 0; 878 878 + } 879 879 + 514 880 static void stac92xx_free(struct hda_codec *codec) 515 881 { 516 516 - kfree(codec->spec); 882 882 + struct sigmatel_spec *spec = codec->spec; 883 883 + int i; 884 884 + 885 885 + if (! spec) 886 886 + return; 887 887 + 888 888 + if (spec->kctl_alloc) { 889 889 + for (i = 0; i < spec->num_kctl_used; i++) 890 890 + kfree(spec->kctl_alloc[i].name); 891 891 + kfree(spec->kctl_alloc); 892 892 + } 893 893 + 894 894 + kfree(spec); 517 895 } 896 896 + 897 897 + static void stac92xx_set_pinctl(struct hda_codec *codec, hda_nid_t nid, 898 898 + unsigned int flag) 899 899 + { 900 900 + unsigned int pin_ctl = snd_hda_codec_read(codec, nid, 901 901 + 0, AC_VERB_GET_PIN_WIDGET_CONTROL, 0x00); 902 902 + snd_hda_codec_write(codec, nid, 0, 903 903 + AC_VERB_SET_PIN_WIDGET_CONTROL, 904 904 + pin_ctl | flag); 905 905 + } 906 906 + 907 907 + static void stac92xx_reset_pinctl(struct hda_codec *codec, hda_nid_t nid, 908 908 + unsigned int flag) 909 909 + { 910 910 + unsigned int pin_ctl = snd_hda_codec_read(codec, nid, 911 911 + 0, AC_VERB_GET_PIN_WIDGET_CONTROL, 0x00); 912 912 + snd_hda_codec_write(codec, nid, 0, 913 913 + AC_VERB_SET_PIN_WIDGET_CONTROL, 914 914 + pin_ctl & ~flag); 915 915 + } 916 916 + 917 917 + static void stac92xx_unsol_event(struct hda_codec *codec, unsigned int res) 918 918 + { 919 919 + struct sigmatel_spec *spec = codec->spec; 920 920 + struct auto_pin_cfg *cfg = &spec->autocfg; 921 921 + int i, presence; 922 922 + 923 923 + if ((res >> 26) != STAC_HP_EVENT) 924 924 + return; 925 925 + 926 926 + presence = snd_hda_codec_read(codec, cfg->hp_pin, 0, 927 927 + AC_VERB_GET_PIN_SENSE, 0x00) >> 31; 928 928 + 929 929 + if (presence) { 930 930 + /* disable lineouts, enable hp */ 931 931 + for (i = 0; i < cfg->line_outs; i++) 932 932 + stac92xx_reset_pinctl(codec, cfg->line_out_pins[i], 933 933 + AC_PINCTL_OUT_EN); 934 934 + stac92xx_set_pinctl(codec, cfg->hp_pin, AC_PINCTL_OUT_EN); 935 935 + } else { 936 936 + /* enable lineouts, disable hp */ 937 937 + for (i = 0; i < cfg->line_outs; i++) 938 938 + stac92xx_set_pinctl(codec, cfg->line_out_pins[i], 939 939 + AC_PINCTL_OUT_EN); 940 940 + stac92xx_reset_pinctl(codec, cfg->hp_pin, AC_PINCTL_OUT_EN); 941 941 + } 942 942 + } 943 943 + 944 944 + #ifdef CONFIG_PM 945 945 + static int stac92xx_resume(struct hda_codec *codec) 946 946 + { 947 947 + struct sigmatel_spec *spec = codec->spec; 948 948 + int i; 949 949 + 950 950 + stac92xx_init(codec); 951 951 + for (i = 0; i < spec->num_mixers; i++) 952 952 + snd_hda_resume_ctls(codec, spec->mixers[i]); 953 953 + if (spec->multiout.dig_out_nid) 954 954 + snd_hda_resume_spdif_out(codec); 955 955 + if (spec->dig_in_nid) 956 956 + snd_hda_resume_spdif_in(codec); 957 957 + 958 958 + return 0; 959 959 + } 960 960 + #endif 518 961 519 962 static struct hda_codec_ops stac92xx_patch_ops = { 520 963 .build_controls = stac92xx_build_controls, 521 964 .build_pcms = stac92xx_build_pcms, 522 965 .init = stac92xx_init, 523 966 .free = stac92xx_free, 967 967 + .unsol_event = stac92xx_unsol_event, 968 968 + #ifdef CONFIG_PM 969 969 + .resume = stac92xx_resume, 970 970 + #endif 524 971 }; 525 972 526 973 static int patch_stac9200(struct hda_codec *codec) 527 974 { 528 975 struct sigmatel_spec *spec; 976 976 + int err; 529 977 530 978 spec = kcalloc(1, sizeof(*spec), GFP_KERNEL); 531 979 if (spec == NULL) ··· 925 589 926 590 codec->spec = spec; 927 591 592 592 + #ifdef STAC_TEST 593 593 + spec->pin_nids = stac9200_pin_nids; 594 594 + spec->num_pins = 8; 595 595 + spec->pin_configs = stac9200_pin_configs; 596 596 + stac92xx_set_config_regs(codec); 597 597 + #endif 928 598 spec->multiout.max_channels = 2; 929 599 spec->multiout.num_dacs = 1; 930 600 spec->multiout.dac_nids = stac9200_dac_nids; 931 931 - spec->multiout.dig_out_nid = 0x05; 932 932 - spec->dig_in_nid = 0x04; 933 601 spec->adc_nids = stac9200_adc_nids; 934 602 spec->mux_nids = stac9200_mux_nids; 935 603 spec->num_muxes = 1; 936 936 - spec->input_mux.num_items = 0; 937 937 - spec->pstate_nids = stac9200_pstate_nids; 938 938 - spec->num_pstates = 3; 939 939 - spec->pin_nids = stac9200_pin_nids; 940 940 - #ifdef STAC_TEST 941 941 - spec->pin_configs = stac9200_pin_configs; 942 942 - #endif 943 943 - spec->num_pins = 8; 944 944 - spec->init = stac9200_ch2_init; 604 604 + 605 605 + spec->init = stac9200_core_init; 945 606 spec->mixer = stac9200_mixer; 946 946 - spec->playback_nid = 0x02; 947 947 - spec->capture_nid = 0x03; 607 607 + 608 608 + err = stac9200_parse_auto_config(codec); 609 609 + if (err < 0) { 610 610 + stac92xx_free(codec); 611 611 + return err; 612 612 + } 948 613 949 614 codec->patch_ops = stac92xx_patch_ops; 950 615 ··· 955 618 static int patch_stac922x(struct hda_codec *codec) 956 619 { 957 620 struct sigmatel_spec *spec; 621 621 + int err; 958 622 959 623 spec = kcalloc(1, sizeof(*spec), GFP_KERNEL); 960 624 if (spec == NULL) ··· 963 625 964 626 codec->spec = spec; 965 627 966 966 - spec->multiout.max_channels = 2; 967 967 - spec->multiout.num_dacs = 4; 968 968 - spec->multiout.dac_nids = stac922x_dac_nids; 969 969 - spec->multiout.dig_out_nid = 0x08; 970 970 - spec->dig_in_nid = 0x09; 628 628 + #ifdef STAC_TEST 629 629 + spec->num_pins = 10; 630 630 + spec->pin_nids = stac922x_pin_nids; 631 631 + spec->pin_configs = stac922x_pin_configs; 632 632 + stac92xx_set_config_regs(codec); 633 633 + #endif 971 634 spec->adc_nids = stac922x_adc_nids; 972 635 spec->mux_nids = stac922x_mux_nids; 973 636 spec->num_muxes = 2; 974 974 - spec->input_mux.num_items = 0; 975 975 - spec->pstate_nids = stac922x_pstate_nids; 976 976 - spec->num_pstates = 8; 977 977 - spec->pin_nids = stac922x_pin_nids; 978 978 - #ifdef STAC_TEST 979 979 - spec->pin_configs = stac922x_pin_configs; 980 980 - #endif 981 981 - spec->num_pins = 10; 982 982 - spec->init = stac922x_ch2_init; 637 637 + 638 638 + spec->init = stac922x_core_init; 983 639 spec->mixer = stac922x_mixer; 984 984 - spec->playback_nid = 0x02; 985 985 - spec->capture_nid = 0x06; 640 640 + 641 641 + spec->multiout.dac_nids = spec->dac_nids; 642 642 + 643 643 + err = stac922x_parse_auto_config(codec); 644 644 + if (err < 0) { 645 645 + stac92xx_free(codec); 646 646 + return err; 647 647 + } 986 648 987 649 codec->patch_ops = stac92xx_patch_ops; 988 650

+14 -2

sound/pci/intel8x0.c

reviewed

··· 424 424 unsigned xbox: 1; /* workaround for Xbox AC'97 detection */ 425 425 426 426 int spdif_idx; /* SPDIF BAR index; *_SPBAR or -1 if use PCMOUT */ 427 427 + unsigned int sdm_saved; /* SDM reg value */ 427 428 428 429 ac97_bus_t *ac97_bus; 429 430 ac97_t *ac97[3]; ··· 2374 2373 for (i = 0; i < 3; i++) 2375 2374 if (chip->ac97[i]) 2376 2375 snd_ac97_suspend(chip->ac97[i]); 2376 2376 + if (chip->device_type == DEVICE_INTEL_ICH4) 2377 2377 + chip->sdm_saved = igetbyte(chip, ICHREG(SDM)); 2377 2378 pci_disable_device(chip->pci); 2378 2379 return 0; 2379 2380 } ··· 2388 2385 pci_enable_device(chip->pci); 2389 2386 pci_set_master(chip->pci); 2390 2387 snd_intel8x0_chip_init(chip, 0); 2388 2388 + 2389 2389 + /* re-initialize mixer stuff */ 2390 2390 + if (chip->device_type == DEVICE_INTEL_ICH4) { 2391 2391 + /* enable separate SDINs for ICH4 */ 2392 2392 + iputbyte(chip, ICHREG(SDM), chip->sdm_saved); 2393 2393 + /* use slot 10/11 for SPDIF */ 2394 2394 + iputdword(chip, ICHREG(GLOB_CNT), 2395 2395 + (igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK) | 2396 2396 + ICH_PCM_SPDIF_1011); 2397 2397 + } 2391 2398 2392 2399 /* refill nocache */ 2393 2400 if (chip->fix_nocache) ··· 2464 2451 } 2465 2452 do_gettimeofday(&start_time); 2466 2453 spin_unlock_irq(&chip->reg_lock); 2467 2467 - set_current_state(TASK_UNINTERRUPTIBLE); 2468 2468 - schedule_timeout(HZ / 20); 2454 2454 + msleep(50); 2469 2455 spin_lock_irq(&chip->reg_lock); 2470 2456 /* check the position */ 2471 2457 pos = ichdev->fragsize1;

+13 -13

sound/pci/maestro3.c

reviewed

··· 1050 1050 * lowlevel functions 1051 1051 */ 1052 1052 1053 1053 - #define big_mdelay(msec) do {\ 1054 1054 - set_current_state(TASK_UNINTERRUPTIBLE);\ 1055 1055 - schedule_timeout(((msec) * HZ) / 1000);\ 1056 1056 - } while (0) 1057 1057 - 1058 1053 static inline void snd_m3_outw(m3_t *chip, u16 value, unsigned long reg) 1059 1054 { 1060 1055 outw(value, chip->iobase + reg); ··· 1091 1096 static void snd_m3_assp_halt(m3_t *chip) 1092 1097 { 1093 1098 chip->reset_state = snd_m3_inb(chip, DSP_PORT_CONTROL_REG_B) & ~REGB_STOP_CLOCK; 1094 1094 - big_mdelay(10); 1099 1099 + msleep(10); 1095 1100 snd_m3_outb(chip, chip->reset_state & ~REGB_ENABLE_RESET, DSP_PORT_CONTROL_REG_B); 1096 1101 } 1097 1102 ··· 2103 2108 */ 2104 2109 tmp = inw(io + RING_BUS_CTRL_A); 2105 2110 outw(RAC_SDFS_ENABLE|LAC_SDFS_ENABLE, io + RING_BUS_CTRL_A); 2106 2106 - big_mdelay(20); 2111 2111 + msleep(20); 2107 2112 outw(tmp, io + RING_BUS_CTRL_A); 2108 2108 - big_mdelay(50); 2113 2113 + msleep(50); 2109 2114 #endif 2110 2115 } 2111 2116 ··· 2520 2525 snd_m3_enable_ints(m3_t *chip) 2521 2526 { 2522 2527 unsigned long io = chip->iobase; 2528 2528 + unsigned short val; 2523 2529 2524 2530 /* TODO: MPU401 not supported yet */ 2525 2525 - outw(ASSP_INT_ENABLE | HV_INT_ENABLE /*| MPU401_INT_ENABLE*/, io + HOST_INT_CTRL); 2531 2531 + val = ASSP_INT_ENABLE /*| MPU401_INT_ENABLE*/; 2532 2532 + if (chip->hv_quirk && (chip->hv_quirk->config & HV_CTRL_ENABLE)) 2533 2533 + val |= HV_INT_ENABLE; 2534 2534 + outw(val, io + HOST_INT_CTRL); 2526 2535 outb(inb(io + ASSP_CONTROL_C) | ASSP_HOST_INT_ENABLE, 2527 2536 io + ASSP_CONTROL_C); 2528 2537 } ··· 2588 2589 snd_pcm_suspend_all(chip->pcm); 2589 2590 snd_ac97_suspend(chip->ac97); 2590 2591 2591 2591 - big_mdelay(10); /* give the assp a chance to idle.. */ 2592 2592 + msleep(10); /* give the assp a chance to idle.. */ 2592 2593 2593 2594 snd_m3_assp_halt(chip); 2594 2595 ··· 2696 2697 } 2697 2698 2698 2699 spin_lock_init(&chip->reg_lock); 2700 2700 + spin_lock_init(&chip->ac97_lock); 2701 2701 + 2699 2702 switch (pci->device) { 2700 2703 case PCI_DEVICE_ID_ESS_ALLEGRO: 2701 2704 case PCI_DEVICE_ID_ESS_ALLEGRO_1: ··· 2766 2765 snd_m3_assp_init(chip); 2767 2766 snd_m3_amp_enable(chip, 1); 2768 2767 2768 2768 + tasklet_init(&chip->hwvol_tq, snd_m3_update_hw_volume, (unsigned long)chip); 2769 2769 + 2769 2770 if (request_irq(pci->irq, snd_m3_interrupt, SA_INTERRUPT|SA_SHIRQ, 2770 2771 card->driver, (void *)chip)) { 2771 2772 snd_printk("unable to grab IRQ %d\n", pci->irq); ··· 2788 2785 snd_m3_free(chip); 2789 2786 return err; 2790 2787 } 2791 2791 - 2792 2792 - spin_lock_init(&chip->ac97_lock); 2793 2793 - tasklet_init(&chip->hwvol_tq, snd_m3_update_hw_volume, (unsigned long)chip); 2794 2788 2795 2789 if ((err = snd_m3_mixer(chip)) < 0) 2796 2790 return err;

+2 -2

sound/pci/mixart/mixart.c

reviewed

··· 445 445 446 446 static int mixart_sync_nonblock_events(mixart_mgr_t *mgr) 447 447 { 448 448 - int timeout = HZ; 448 448 + unsigned long timeout = jiffies + HZ; 449 449 while (atomic_read(&mgr->msg_processed) > 0) { 450 450 - if (! timeout--) { 450 450 + if (time_after(jiffies, timeout)) { 451 451 snd_printk(KERN_ERR "mixart: cannot process nonblock events!\n"); 452 452 return -EBUSY; 453 453 }

+55 -13

sound/pci/rme9652/hdsp.c

reviewed

··· 445 445 u32 control2_register; /* cached value */ 446 446 u32 creg_spdif; 447 447 u32 creg_spdif_stream; 448 448 + int clock_source_locked; 448 449 char *card_name; /* digiface/multiface */ 449 450 HDSP_IO_Type io_type; /* ditto, but for code use */ 450 451 unsigned short firmware_rev; ··· 679 678 } 680 679 681 680 if ((1000 / HZ) < 3000) { 682 682 - set_current_state(TASK_UNINTERRUPTIBLE); 683 683 - schedule_timeout((3000 * HZ + 999) / 1000); 681 681 + ssleep(3); 684 682 } else { 685 683 mdelay(3000); 686 684 } ··· 2095 2095 return change; 2096 2096 } 2097 2097 2098 2098 + static int snd_hdsp_info_clock_source_lock(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo) 2099 2099 + { 2100 2100 + uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; 2101 2101 + uinfo->count = 1; 2102 2102 + uinfo->value.integer.min = 0; 2103 2103 + uinfo->value.integer.max = 1; 2104 2104 + return 0; 2105 2105 + } 2106 2106 + 2107 2107 + static int snd_hdsp_get_clock_source_lock(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol) 2108 2108 + { 2109 2109 + hdsp_t *hdsp = snd_kcontrol_chip(kcontrol); 2110 2110 + 2111 2111 + ucontrol->value.integer.value[0] = hdsp->clock_source_locked; 2112 2112 + return 0; 2113 2113 + } 2114 2114 + 2115 2115 + static int snd_hdsp_put_clock_source_lock(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol) 2116 2116 + { 2117 2117 + hdsp_t *hdsp = snd_kcontrol_chip(kcontrol); 2118 2118 + int change; 2119 2119 + 2120 2120 + change = (int)ucontrol->value.integer.value[0] != hdsp->clock_source_locked; 2121 2121 + if (change) 2122 2122 + hdsp->clock_source_locked = ucontrol->value.integer.value[0]; 2123 2123 + return change; 2124 2124 + } 2125 2125 + 2098 2126 #define HDSP_DA_GAIN(xname, xindex) \ 2099 2127 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \ 2100 2128 .name = xname, \ ··· 3145 3117 HDSP_SPDIF_NON_AUDIO("IEC958 Non-audio Bit", 0), 3146 3118 /* 'Sample Clock Source' complies with the alsa control naming scheme */ 3147 3119 HDSP_CLOCK_SOURCE("Sample Clock Source", 0), 3120 3120 + { 3121 3121 + /* FIXME: should be PCM or MIXER? */ 3122 3122 + /* .iface = SNDRV_CTL_ELEM_IFACE_PCM, */ 3123 3123 + .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 3124 3124 + .name = "Sample Clock Source Locking", 3125 3125 + .info = snd_hdsp_info_clock_source_lock, 3126 3126 + .get = snd_hdsp_get_clock_source_lock, 3127 3127 + .put = snd_hdsp_put_clock_source_lock, 3128 3128 + }, 3148 3129 HDSP_SYSTEM_CLOCK_MODE("System Clock Mode", 0), 3149 3130 HDSP_PREF_SYNC_REF("Preferred Sync Reference", 0), 3150 3131 HDSP_AUTOSYNC_REF("AutoSync Reference", 0), ··· 3386 3349 snd_iprintf (buffer, "System Clock Mode: %s\n", system_clock_mode); 3387 3350 3388 3351 snd_iprintf (buffer, "System Clock Frequency: %d\n", hdsp->system_sample_rate); 3352 3352 + snd_iprintf (buffer, "System Clock Locked: %s\n", hdsp->clock_source_locked ? "Yes" : "No"); 3389 3353 3390 3354 snd_iprintf(buffer, "\n"); 3391 3355 ··· 3891 3853 */ 3892 3854 3893 3855 spin_lock_irq(&hdsp->lock); 3894 3894 - if ((err = hdsp_set_rate(hdsp, params_rate(params), 0)) < 0) { 3895 3895 - spin_unlock_irq(&hdsp->lock); 3896 3896 - _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_RATE); 3897 3897 - return err; 3898 3898 - } else { 3899 3899 - spin_unlock_irq(&hdsp->lock); 3856 3856 + if (! hdsp->clock_source_locked) { 3857 3857 + if ((err = hdsp_set_rate(hdsp, params_rate(params), 0)) < 0) { 3858 3858 + spin_unlock_irq(&hdsp->lock); 3859 3859 + _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_RATE); 3860 3860 + return err; 3861 3861 + } 3900 3862 } 3863 3863 + spin_unlock_irq(&hdsp->lock); 3901 3864 3902 3865 if ((err = hdsp_set_interrupt_interval(hdsp, params_period_size(params))) < 0) { 3903 3866 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_PERIOD_SIZE); ··· 4323 4284 4324 4285 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24); 4325 4286 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, &hdsp_hw_constraints_period_sizes); 4326 4326 - if (hdsp->io_type == H9632) { 4327 4327 - runtime->hw.channels_min = hdsp->qs_out_channels; 4328 4328 - runtime->hw.channels_max = hdsp->ss_out_channels; 4287 4287 + if (hdsp->clock_source_locked) { 4288 4288 + runtime->hw.rate_min = runtime->hw.rate_max = hdsp->system_sample_rate; 4289 4289 + } else if (hdsp->io_type == H9632) { 4329 4290 runtime->hw.rate_max = 192000; 4330 4291 runtime->hw.rates = SNDRV_PCM_RATE_KNOT; 4331 4292 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hdsp_hw_constraints_9632_sample_rates); 4332 4293 } 4294 4294 + if (hdsp->io_type == H9632) { 4295 4295 + runtime->hw.channels_min = hdsp->qs_out_channels; 4296 4296 + runtime->hw.channels_max = hdsp->ss_out_channels; 4297 4297 + } 4333 4298 4334 4299 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, 4335 4300 snd_hdsp_hw_rule_out_channels, hdsp, ··· 5079 5036 if (!is_9652 && !is_9632) { 5080 5037 /* we wait 2 seconds to let freshly inserted cardbus cards do their hardware init */ 5081 5038 if ((1000 / HZ) < 2000) { 5082 5082 - set_current_state(TASK_UNINTERRUPTIBLE); 5083 5083 - schedule_timeout((2000 * HZ + 999) / 1000); 5039 5039 + ssleep(2); 5084 5040 } else { 5085 5041 mdelay(2000); 5086 5042 }

+2 -2

sound/pci/trident/trident_main.c

reviewed

··· 472 472 break; 473 473 default: 474 474 snd_BUG(); 475 475 + return; 475 476 } 476 477 477 478 outb(voice->number, TRID_REG(trident, T4D_LFO_GC_CIR)); ··· 3153 3152 switch (mode) { 3154 3153 case GAMEPORT_MODE_COOKED: 3155 3154 outb(GAMEPORT_MODE_ADC, TRID_REG(chip, GAMEPORT_GCR)); 3156 3156 - set_current_state(TASK_UNINTERRUPTIBLE); 3157 3157 - schedule_timeout(1 + 20 * HZ / 1000); /* 20msec */ 3155 3155 + msleep(20); 3158 3156 return 0; 3159 3157 case GAMEPORT_MODE_RAW: 3160 3158 outb(0, TRID_REG(chip, GAMEPORT_GCR));

+8 -8

sound/pci/via82xx.c

reviewed

··· 547 547 int err; 548 548 err = snd_via82xx_codec_ready(chip, ac97->num); 549 549 /* here we need to wait fairly for long time.. */ 550 550 - set_current_state(TASK_UNINTERRUPTIBLE); 551 551 - schedule_timeout(HZ/2); 550 550 + msleep(500); 552 551 } 553 552 554 553 static void snd_via82xx_codec_write(ac97_t *ac97, ··· 1846 1847 static int snd_via82xx_chip_init(via82xx_t *chip) 1847 1848 { 1848 1849 unsigned int val; 1849 1849 - int max_count; 1850 1850 + unsigned long end_time; 1850 1851 unsigned char pval; 1851 1852 1852 1853 #if 0 /* broken on K7M? */ ··· 1888 1889 } 1889 1890 1890 1891 /* wait until codec ready */ 1891 1891 - max_count = ((3 * HZ) / 4) + 1; 1892 1892 + end_time = jiffies + msecs_to_jiffies(750); 1892 1893 do { 1893 1894 pci_read_config_byte(chip->pci, VIA_ACLINK_STAT, &pval); 1894 1895 if (pval & VIA_ACLINK_C00_READY) /* primary codec ready */ 1895 1896 break; 1896 1897 set_current_state(TASK_UNINTERRUPTIBLE); 1897 1898 schedule_timeout(1); 1898 1898 - } while (--max_count > 0); 1899 1899 + } while (time_before(jiffies, end_time)); 1899 1900 1900 1901 if ((val = snd_via82xx_codec_xread(chip)) & VIA_REG_AC97_BUSY) 1901 1902 snd_printk("AC'97 codec is not ready [0x%x]\n", val); ··· 1904 1905 snd_via82xx_codec_xwrite(chip, VIA_REG_AC97_READ | 1905 1906 VIA_REG_AC97_SECONDARY_VALID | 1906 1907 (VIA_REG_AC97_CODEC_ID_SECONDARY << VIA_REG_AC97_CODEC_ID_SHIFT)); 1907 1907 - max_count = ((3 * HZ) / 4) + 1; 1908 1908 + end_time = jiffies + msecs_to_jiffies(750); 1908 1909 snd_via82xx_codec_xwrite(chip, VIA_REG_AC97_READ | 1909 1910 VIA_REG_AC97_SECONDARY_VALID | 1910 1911 (VIA_REG_AC97_CODEC_ID_SECONDARY << VIA_REG_AC97_CODEC_ID_SHIFT)); ··· 1915 1916 } 1916 1917 set_current_state(TASK_INTERRUPTIBLE); 1917 1918 schedule_timeout(1); 1918 1918 - } while (--max_count > 0); 1919 1919 + } while (time_before(jiffies, end_time)); 1919 1920 /* This is ok, the most of motherboards have only one codec */ 1920 1921 1921 1922 __ac97_ok2: ··· 2177 2178 { .subvendor = 0x147b, .subdevice = 0x1413, .action = VIA_DXS_ENABLE }, /* ABIT KV8 Pro */ 2178 2179 { .subvendor = 0x147b, .subdevice = 0x1415, .action = VIA_DXS_NO_VRA }, /* Abit AV8 */ 2179 2180 { .subvendor = 0x14ff, .subdevice = 0x0403, .action = VIA_DXS_ENABLE }, /* Twinhead mobo */ 2180 2180 - { .subvendor = 0x14ff, .subdevice = 0x0408, .action = VIA_DXS_NO_VRA }, /* Twinhead mobo */ 2181 2181 + { .subvendor = 0x14ff, .subdevice = 0x0408, .action = VIA_DXS_SRC }, /* Twinhead laptop */ 2181 2182 { .subvendor = 0x1584, .subdevice = 0x8120, .action = VIA_DXS_ENABLE }, /* Gericom/Targa/Vobis/Uniwill laptop */ 2182 2183 { .subvendor = 0x1584, .subdevice = 0x8123, .action = VIA_DXS_NO_VRA }, /* Uniwill (Targa Visionary XP-210) */ 2183 2184 { .subvendor = 0x161f, .subdevice = 0x202b, .action = VIA_DXS_NO_VRA }, /* Amira Note book */ ··· 2186 2187 { .subvendor = 0x1695, .subdevice = 0x3005, .action = VIA_DXS_ENABLE }, /* EPoX EP-8K9A */ 2187 2188 { .subvendor = 0x1849, .subdevice = 0x3059, .action = VIA_DXS_NO_VRA }, /* ASRock K7VM2 */ 2188 2189 { .subvendor = 0x1919, .subdevice = 0x200a, .action = VIA_DXS_NO_VRA }, /* Soltek SL-K8Tpro-939 */ 2190 2190 + { .subvendor = 0x4005, .subdevice = 0x4710, .action = VIA_DXS_SRC }, /* MSI K7T266 Pro2 (MS-6380 V2.0) BIOS 3.7 */ 2189 2191 { } /* terminator */ 2190 2192 }; 2191 2193 struct dxs_whitelist *w;

+6 -7

sound/pci/via82xx_modem.c

reviewed

··· 408 408 int err; 409 409 err = snd_via82xx_codec_ready(chip, ac97->num); 410 410 /* here we need to wait fairly for long time.. */ 411 411 - set_current_state(TASK_UNINTERRUPTIBLE); 412 412 - schedule_timeout(HZ/2); 411 411 + msleep(500); 413 412 } 414 413 415 414 static void snd_via82xx_codec_write(ac97_t *ac97, ··· 922 923 static int snd_via82xx_chip_init(via82xx_t *chip) 923 924 { 924 925 unsigned int val; 925 925 - int max_count; 926 926 + unsigned long end_time; 926 927 unsigned char pval; 927 928 928 929 pci_read_config_byte(chip->pci, VIA_MC97_CTRL, &pval); ··· 961 962 } 962 963 963 964 /* wait until codec ready */ 964 964 - max_count = ((3 * HZ) / 4) + 1; 965 965 + end_time = jiffies + msecs_to_jiffies(750); 965 966 do { 966 967 pci_read_config_byte(chip->pci, VIA_ACLINK_STAT, &pval); 967 968 if (pval & VIA_ACLINK_C00_READY) /* primary codec ready */ 968 969 break; 969 970 set_current_state(TASK_UNINTERRUPTIBLE); 970 971 schedule_timeout(1); 971 971 - } while (--max_count > 0); 972 972 + } while (time_before(jiffies, end_time)); 972 973 973 974 if ((val = snd_via82xx_codec_xread(chip)) & VIA_REG_AC97_BUSY) 974 975 snd_printk("AC'97 codec is not ready [0x%x]\n", val); ··· 976 977 snd_via82xx_codec_xwrite(chip, VIA_REG_AC97_READ | 977 978 VIA_REG_AC97_SECONDARY_VALID | 978 979 (VIA_REG_AC97_CODEC_ID_SECONDARY << VIA_REG_AC97_CODEC_ID_SHIFT)); 979 979 - max_count = ((3 * HZ) / 4) + 1; 980 980 + end_time = jiffies + msecs_to_jiffies(750); 980 981 snd_via82xx_codec_xwrite(chip, VIA_REG_AC97_READ | 981 982 VIA_REG_AC97_SECONDARY_VALID | 982 983 (VIA_REG_AC97_CODEC_ID_SECONDARY << VIA_REG_AC97_CODEC_ID_SHIFT)); ··· 987 988 } 988 989 set_current_state(TASK_INTERRUPTIBLE); 989 990 schedule_timeout(1); 990 990 - } while (--max_count > 0); 991 991 + } while (time_before(jiffies, end_time)); 991 992 /* This is ok, the most of motherboards have only one codec */ 992 993 993 994 __ac97_ok2:

+3 -3

sound/pci/ymfpci/ymfpci_main.c

reviewed

··· 84 84 85 85 static int snd_ymfpci_codec_ready(ymfpci_t *chip, int secondary) 86 86 { 87 87 - signed long end_time; 87 87 + unsigned long end_time; 88 88 u32 reg = secondary ? YDSXGR_SECSTATUSADR : YDSXGR_PRISTATUSADR; 89 89 90 90 - end_time = (jiffies + ((3 * HZ) / 4)) + 1; 90 90 + end_time = jiffies + msecs_to_jiffies(750); 91 91 do { 92 92 if ((snd_ymfpci_readw(chip, reg) & 0x8000) == 0) 93 93 return 0; 94 94 set_current_state(TASK_UNINTERRUPTIBLE); 95 95 schedule_timeout(1); 96 96 - } while (end_time - (signed long)jiffies >= 0); 96 96 + } while (time_before(jiffies, end_time)); 97 97 snd_printk("codec_ready: codec %i is not ready [0x%x]\n", secondary, snd_ymfpci_readw(chip, reg)); 98 98 return -EBUSY; 99 99 }

+2 -13

sound/pcmcia/Kconfig

reviewed

··· 8 8 depends on SND && PCMCIA && ISA 9 9 select SND_VX_LIB 10 10 help 11 11 - Say Y here to include support for Digigram VXpocket 12 12 - soundcards. 11 11 + Say Y here to include support for Digigram VXpocket and 12 12 + VXpocket 440 soundcards. 13 13 14 14 To compile this driver as a module, choose M here: the module 15 15 will be called snd-vxpocket. 16 16 - 17 17 - config SND_VXP440 18 18 - tristate "Digigram VXpocket 440" 19 19 - depends on SND && PCMCIA && ISA 20 20 - select SND_VX_LIB 21 21 - help 22 22 - Say Y here to include support for Digigram VXpocket 440 23 23 - soundcards. 24 24 - 25 25 - To compile this driver as a module, choose M here: the module 26 26 - will be called snd-vxp440. 27 16 28 17 config SND_PDAUDIOCF 29 18 tristate "Sound Core PDAudioCF"

+2 -5

sound/pcmcia/vx/Makefile

reviewed

··· 3 3 # Copyright (c) 2001 by Jaroslav Kysela <perex@suse.cz> 4 4 # 5 5 6 6 - snd-vx-cs-objs := vx_entry.o vxp_ops.o vxp_mixer.o 7 7 - snd-vxpocket-objs := vxpocket.o 8 8 - snd-vxp440-objs := vxp440.o 6 6 + snd-vxpocket-objs := vxpocket.o vxp_ops.o vxp_mixer.o 9 7 10 10 - obj-$(CONFIG_SND_VXPOCKET) += snd-vxpocket.o snd-vx-cs.o 11 11 - obj-$(CONFIG_SND_VXP440) += snd-vxp440.o snd-vx-cs.o 8 8 + obj-$(CONFIG_SND_VXPOCKET) += snd-vxpocket.o

-375

sound/pcmcia/vx/vx_entry.c

reviewed

··· 1 1 - /* 2 2 - * Driver for Digigram VXpocket soundcards 3 3 - * 4 4 - * PCMCIA entry part 5 5 - * 6 6 - * Copyright (c) 2002 by Takashi Iwai <tiwai@suse.de> 7 7 - * 8 8 - * This program is free software; you can redistribute it and/or modify 9 9 - * it under the terms of the GNU General Public License as published by 10 10 - * the Free Software Foundation; either version 2 of the License, or 11 11 - * (at your option) any later version. 12 12 - * 13 13 - * This program is distributed in the hope that it will be useful, 14 14 - * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 15 - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 16 - * GNU General Public License for more details. 17 17 - * 18 18 - * You should have received a copy of the GNU General Public License 19 19 - * along with this program; if not, write to the Free Software 20 20 - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 21 21 - */ 22 22 - 23 23 - #include <sound/driver.h> 24 24 - #include <sound/core.h> 25 25 - #include "vxpocket.h" 26 26 - #include <pcmcia/ciscode.h> 27 27 - #include <pcmcia/cisreg.h> 28 28 - 29 29 - 30 30 - MODULE_AUTHOR("Takashi Iwai <tiwai@suse.de>"); 31 31 - MODULE_DESCRIPTION("Common routines for Digigram PCMCIA VX drivers"); 32 32 - MODULE_LICENSE("GPL"); 33 33 - 34 34 - /* 35 35 - * prototypes 36 36 - */ 37 37 - static void vxpocket_config(dev_link_t *link); 38 38 - 39 39 - 40 40 - static void vxpocket_release(dev_link_t *link) 41 41 - { 42 42 - if (link->state & DEV_CONFIG) { 43 43 - /* release cs resources */ 44 44 - pcmcia_release_configuration(link->handle); 45 45 - pcmcia_release_io(link->handle, &link->io); 46 46 - pcmcia_release_irq(link->handle, &link->irq); 47 47 - link->state &= ~DEV_CONFIG; 48 48 - } 49 49 - } 50 50 - 51 51 - /* 52 52 - * destructor 53 53 - */ 54 54 - static int snd_vxpocket_free(vx_core_t *chip) 55 55 - { 56 56 - struct snd_vxpocket *vxp = (struct snd_vxpocket *)chip; 57 57 - struct snd_vxp_entry *hw; 58 58 - dev_link_t *link = &vxp->link; 59 59 - 60 60 - vxpocket_release(link); 61 61 - 62 62 - /* Break the link with Card Services */ 63 63 - if (link->handle) 64 64 - pcmcia_deregister_client(link->handle); 65 65 - 66 66 - hw = vxp->hw_entry; 67 67 - if (hw) 68 68 - hw->card_list[vxp->index] = NULL; 69 69 - chip->card = NULL; 70 70 - kfree(chip->dev); 71 71 - 72 72 - snd_vx_free_firmware(chip); 73 73 - kfree(chip); 74 74 - return 0; 75 75 - } 76 76 - 77 77 - static int snd_vxpocket_dev_free(snd_device_t *device) 78 78 - { 79 79 - vx_core_t *chip = device->device_data; 80 80 - return snd_vxpocket_free(chip); 81 81 - } 82 82 - 83 83 - /* 84 84 - * snd_vxpocket_attach - attach callback for cs 85 85 - * @hw: the hardware information 86 86 - */ 87 87 - dev_link_t *snd_vxpocket_attach(struct snd_vxp_entry *hw) 88 88 - { 89 89 - client_reg_t client_reg; /* Register with cardmgr */ 90 90 - dev_link_t *link; /* Info for cardmgr */ 91 91 - int i, ret; 92 92 - vx_core_t *chip; 93 93 - struct snd_vxpocket *vxp; 94 94 - snd_card_t *card; 95 95 - static snd_device_ops_t ops = { 96 96 - .dev_free = snd_vxpocket_dev_free, 97 97 - }; 98 98 - 99 99 - snd_printdd(KERN_DEBUG "vxpocket_attach called\n"); 100 100 - /* find an empty slot from the card list */ 101 101 - for (i = 0; i < SNDRV_CARDS; i++) { 102 102 - if (! hw->card_list[i]) 103 103 - break; 104 104 - } 105 105 - if (i >= SNDRV_CARDS) { 106 106 - snd_printk(KERN_ERR "vxpocket: too many cards found\n"); 107 107 - return NULL; 108 108 - } 109 109 - if (! hw->enable_table[i]) 110 110 - return NULL; /* disabled explicitly */ 111 111 - 112 112 - /* ok, create a card instance */ 113 113 - card = snd_card_new(hw->index_table[i], hw->id_table[i], THIS_MODULE, 0); 114 114 - if (card == NULL) { 115 115 - snd_printk(KERN_ERR "vxpocket: cannot create a card instance\n"); 116 116 - return NULL; 117 117 - } 118 118 - 119 119 - chip = snd_vx_create(card, hw->hardware, hw->ops, 120 120 - sizeof(struct snd_vxpocket) - sizeof(vx_core_t)); 121 121 - if (! chip) 122 122 - return NULL; 123 123 - 124 124 - #ifdef SND_VX_FW_LOADER 125 125 - /* fake a device here since pcmcia doesn't give a valid device... */ 126 126 - chip->dev = kcalloc(1, sizeof(*chip->dev), GFP_KERNEL); 127 127 - if (! chip->dev) { 128 128 - snd_printk(KERN_ERR "vxp: can't malloc chip->dev\n"); 129 129 - kfree(chip); 130 130 - snd_card_free(card); 131 131 - return NULL; 132 132 - } 133 133 - device_initialize(chip->dev); 134 134 - sprintf(chip->dev->bus_id, "vxpocket%d", i); 135 135 - #endif 136 136 - 137 137 - if (snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops) < 0) { 138 138 - kfree(chip); 139 139 - snd_card_free(card); 140 140 - return NULL; 141 141 - } 142 142 - 143 143 - vxp = (struct snd_vxpocket *)chip; 144 144 - vxp->index = i; 145 145 - vxp->hw_entry = hw; 146 146 - chip->ibl.size = hw->ibl[i]; 147 147 - hw->card_list[i] = chip; 148 148 - 149 149 - link = &vxp->link; 150 150 - link->priv = chip; 151 151 - 152 152 - link->io.Attributes1 = IO_DATA_PATH_WIDTH_AUTO; 153 153 - link->io.NumPorts1 = 16; 154 154 - 155 155 - link->irq.Attributes = IRQ_TYPE_EXCLUSIVE | IRQ_HANDLE_PRESENT; 156 156 - // link->irq.Attributes = IRQ_TYPE_DYNAMIC_SHARING|IRQ_FIRST_SHARED; 157 157 - 158 158 - link->irq.IRQInfo1 = IRQ_LEVEL_ID; 159 159 - link->irq.Handler = &snd_vx_irq_handler; 160 160 - link->irq.Instance = chip; 161 161 - 162 162 - link->conf.Attributes = CONF_ENABLE_IRQ; 163 163 - link->conf.Vcc = 50; 164 164 - link->conf.IntType = INT_MEMORY_AND_IO; 165 165 - link->conf.ConfigIndex = 1; 166 166 - link->conf.Present = PRESENT_OPTION; 167 167 - 168 168 - /* Register with Card Services */ 169 169 - memset(&client_reg, 0, sizeof(client_reg)); 170 170 - client_reg.dev_info = hw->dev_info; 171 171 - client_reg.Version = 0x0210; 172 172 - client_reg.event_callback_args.client_data = link; 173 173 - 174 174 - ret = pcmcia_register_client(&link->handle, &client_reg); 175 175 - if (ret != CS_SUCCESS) { 176 176 - cs_error(link->handle, RegisterClient, ret); 177 177 - snd_card_free(card); 178 178 - return NULL; 179 179 - } 180 180 - 181 181 - /* Chain drivers */ 182 182 - link->next = hw->dev_list; 183 183 - hw->dev_list = link; 184 184 - 185 185 - /* snd_card_set_pm_callback(card, snd_vxpocket_suspend, snd_vxpocket_resume, chip); */ 186 186 - 187 187 - return link; 188 188 - } 189 189 - 190 190 - 191 191 - /** 192 192 - * snd_vxpocket_assign_resources - initialize the hardware and card instance. 193 193 - * @port: i/o port for the card 194 194 - * @irq: irq number for the card 195 195 - * 196 196 - * this function assigns the specified port and irq, boot the card, 197 197 - * create pcm and control instances, and initialize the rest hardware. 198 198 - * 199 199 - * returns 0 if successful, or a negative error code. 200 200 - */ 201 201 - static int snd_vxpocket_assign_resources(vx_core_t *chip, int port, int irq) 202 202 - { 203 203 - int err; 204 204 - snd_card_t *card = chip->card; 205 205 - struct snd_vxpocket *vxp = (struct snd_vxpocket *)chip; 206 206 - 207 207 - snd_printdd(KERN_DEBUG "vxpocket assign resources: port = 0x%x, irq = %d\n", port, irq); 208 208 - vxp->port = port; 209 209 - 210 210 - sprintf(card->shortname, "Digigram %s", card->driver); 211 211 - sprintf(card->longname, "%s at 0x%x, irq %i", 212 212 - card->shortname, port, irq); 213 213 - 214 214 - chip->irq = irq; 215 215 - 216 216 - if ((err = snd_vx_setup_firmware(chip)) < 0) 217 217 - return err; 218 218 - 219 219 - return 0; 220 220 - } 221 221 - 222 222 - 223 223 - /* 224 224 - * snd_vxpocket_detach - detach callback for cs 225 225 - * @hw: the hardware information 226 226 - */ 227 227 - void snd_vxpocket_detach(struct snd_vxp_entry *hw, dev_link_t *link) 228 228 - { 229 229 - vx_core_t *chip; 230 230 - 231 231 - if (! link) 232 232 - return; 233 233 - 234 234 - chip = link->priv; 235 235 - 236 236 - snd_printdd(KERN_DEBUG "vxpocket_detach called\n"); 237 237 - /* Remove the interface data from the linked list */ 238 238 - if (hw) { 239 239 - dev_link_t **linkp; 240 240 - /* Locate device structure */ 241 241 - for (linkp = &hw->dev_list; *linkp; linkp = &(*linkp)->next) 242 242 - if (*linkp == link) { 243 243 - *linkp = link->next; 244 244 - break; 245 245 - } 246 246 - } 247 247 - chip->chip_status |= VX_STAT_IS_STALE; /* to be sure */ 248 248 - snd_card_disconnect(chip->card); 249 249 - snd_card_free_in_thread(chip->card); 250 250 - } 251 251 - 252 252 - /* 253 253 - * configuration callback 254 254 - */ 255 255 - 256 256 - #define CS_CHECK(fn, ret) \ 257 257 - do { last_fn = (fn); if ((last_ret = (ret)) != 0) goto cs_failed; } while (0) 258 258 - 259 259 - static void vxpocket_config(dev_link_t *link) 260 260 - { 261 261 - client_handle_t handle = link->handle; 262 262 - vx_core_t *chip = link->priv; 263 263 - struct snd_vxpocket *vxp = (struct snd_vxpocket *)chip; 264 264 - tuple_t tuple; 265 265 - cisparse_t *parse = NULL; 266 266 - u_short buf[32]; 267 267 - int last_fn, last_ret; 268 268 - 269 269 - snd_printdd(KERN_DEBUG "vxpocket_config called\n"); 270 270 - parse = kmalloc(sizeof(*parse), GFP_KERNEL); 271 271 - if (! parse) { 272 272 - snd_printk(KERN_ERR "vx: cannot allocate\n"); 273 273 - return; 274 274 - } 275 275 - tuple.Attributes = 0; 276 276 - tuple.TupleData = (cisdata_t *)buf; 277 277 - tuple.TupleDataMax = sizeof(buf); 278 278 - tuple.TupleOffset = 0; 279 279 - tuple.DesiredTuple = CISTPL_CONFIG; 280 280 - CS_CHECK(GetFirstTuple, pcmcia_get_first_tuple(handle, &tuple)); 281 281 - CS_CHECK(GetTupleData, pcmcia_get_tuple_data(handle, &tuple)); 282 282 - CS_CHECK(ParseTuple, pcmcia_parse_tuple(handle, &tuple, parse)); 283 283 - link->conf.ConfigBase = parse->config.base; 284 284 - link->conf.Present = parse->config.rmask[0]; 285 285 - 286 286 - /* Configure card */ 287 287 - link->state |= DEV_CONFIG; 288 288 - 289 289 - CS_CHECK(RequestIO, pcmcia_request_io(handle, &link->io)); 290 290 - CS_CHECK(RequestIRQ, pcmcia_request_irq(link->handle, &link->irq)); 291 291 - CS_CHECK(RequestConfiguration, pcmcia_request_configuration(link->handle, &link->conf)); 292 292 - 293 293 - if (snd_vxpocket_assign_resources(chip, link->io.BasePort1, link->irq.AssignedIRQ) < 0) 294 294 - goto failed; 295 295 - 296 296 - link->dev = &vxp->node; 297 297 - link->state &= ~DEV_CONFIG_PENDING; 298 298 - kfree(parse); 299 299 - return; 300 300 - 301 301 - cs_failed: 302 302 - cs_error(link->handle, last_fn, last_ret); 303 303 - failed: 304 304 - pcmcia_release_configuration(link->handle); 305 305 - pcmcia_release_io(link->handle, &link->io); 306 306 - pcmcia_release_irq(link->handle, &link->irq); 307 307 - link->state &= ~DEV_CONFIG; 308 308 - kfree(parse); 309 309 - } 310 310 - 311 311 - 312 312 - /* 313 313 - * event callback 314 314 - */ 315 315 - int vxpocket_event(event_t event, int priority, event_callback_args_t *args) 316 316 - { 317 317 - dev_link_t *link = args->client_data; 318 318 - vx_core_t *chip = link->priv; 319 319 - 320 320 - switch (event) { 321 321 - case CS_EVENT_CARD_REMOVAL: 322 322 - snd_printdd(KERN_DEBUG "CARD_REMOVAL..\n"); 323 323 - link->state &= ~DEV_PRESENT; 324 324 - if (link->state & DEV_CONFIG) { 325 325 - chip->chip_status |= VX_STAT_IS_STALE; 326 326 - } 327 327 - break; 328 328 - case CS_EVENT_CARD_INSERTION: 329 329 - snd_printdd(KERN_DEBUG "CARD_INSERTION..\n"); 330 330 - link->state |= DEV_PRESENT | DEV_CONFIG_PENDING; 331 331 - vxpocket_config(link); 332 332 - break; 333 333 - #ifdef CONFIG_PM 334 334 - case CS_EVENT_PM_SUSPEND: 335 335 - snd_printdd(KERN_DEBUG "SUSPEND\n"); 336 336 - link->state |= DEV_SUSPEND; 337 337 - if (chip && chip->card->pm_suspend) { 338 338 - snd_printdd(KERN_DEBUG "snd_vx_suspend calling\n"); 339 339 - chip->card->pm_suspend(chip->card, PMSG_SUSPEND); 340 340 - } 341 341 - /* Fall through... */ 342 342 - case CS_EVENT_RESET_PHYSICAL: 343 343 - snd_printdd(KERN_DEBUG "RESET_PHYSICAL\n"); 344 344 - if (link->state & DEV_CONFIG) 345 345 - pcmcia_release_configuration(link->handle); 346 346 - break; 347 347 - case CS_EVENT_PM_RESUME: 348 348 - snd_printdd(KERN_DEBUG "RESUME\n"); 349 349 - link->state &= ~DEV_SUSPEND; 350 350 - /* Fall through... */ 351 351 - case CS_EVENT_CARD_RESET: 352 352 - snd_printdd(KERN_DEBUG "CARD_RESET\n"); 353 353 - if (DEV_OK(link)) { 354 354 - //struct snd_vxpocket *vxp = (struct snd_vxpocket *)chip; 355 355 - snd_printdd(KERN_DEBUG "requestconfig...\n"); 356 356 - pcmcia_request_configuration(link->handle, &link->conf); 357 357 - if (chip && chip->card->pm_resume) { 358 358 - snd_printdd(KERN_DEBUG "calling snd_vx_resume\n"); 359 359 - chip->card->pm_resume(chip->card); 360 360 - } 361 361 - } 362 362 - snd_printdd(KERN_DEBUG "resume done!\n"); 363 363 - break; 364 364 - #endif 365 365 - } 366 366 - return 0; 367 367 - } 368 368 - 369 369 - /* 370 370 - * exported stuffs 371 371 - */ 372 372 - EXPORT_SYMBOL(snd_vxpocket_ops); 373 373 - EXPORT_SYMBOL(snd_vxpocket_attach); 374 374 - EXPORT_SYMBOL(vxpocket_event); 375 375 - EXPORT_SYMBOL(snd_vxpocket_detach);

-14

sound/pcmcia/vx/vxp440.c

reviewed

··· 1 1 - #define COMPILE_VXP440 2 2 - 3 3 - /* 4 4 - add the following as /etc/pcmcia/vxp440.conf: 5 5 - 6 6 - device "snd-vxp440" 7 7 - class "audio" module "snd-vxp440" 8 8 - 9 9 - card "Digigram VX-POCKET440" 10 10 - manfid 0x01f1, 0x0100 11 11 - bind "snd-vxp440" 12 12 - */ 13 13 - 14 14 - #include "vxpocket.c"

+373 -54

sound/pcmcia/vx/vxpocket.c

reviewed

··· 24 24 #include <linux/moduleparam.h> 25 25 #include <sound/core.h> 26 26 #include "vxpocket.h" 27 27 + #include <pcmcia/ciscode.h> 28 28 + #include <pcmcia/cisreg.h> 27 29 #include <sound/initval.h> 28 30 29 31 /* 30 32 */ 31 33 32 32 - #ifdef COMPILE_VXP440 33 33 - #define CARD_NAME "VXPocket440" 34 34 - #else 35 35 - #define CARD_NAME "VXPocket" 36 36 - #endif 37 37 - 38 34 MODULE_AUTHOR("Takashi Iwai <tiwai@suse.de>"); 39 39 - MODULE_DESCRIPTION("Digigram " CARD_NAME); 35 35 + MODULE_DESCRIPTION("Digigram VXPocket"); 40 36 MODULE_LICENSE("GPL"); 41 41 - MODULE_SUPPORTED_DEVICE("{{Digigram," CARD_NAME "}}"); 37 37 + MODULE_SUPPORTED_DEVICE("{{Digigram,VXPocket},{Digigram,VXPocket440}}"); 42 38 43 39 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */ 44 40 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */ ··· 42 46 static int ibl[SNDRV_CARDS]; 43 47 44 48 module_param_array(index, int, NULL, 0444); 45 45 - MODULE_PARM_DESC(index, "Index value for " CARD_NAME " soundcard."); 49 49 + MODULE_PARM_DESC(index, "Index value for VXPocket soundcard."); 46 50 module_param_array(id, charp, NULL, 0444); 47 47 - MODULE_PARM_DESC(id, "ID string for " CARD_NAME " soundcard."); 51 51 + MODULE_PARM_DESC(id, "ID string for VXPocket soundcard."); 48 52 module_param_array(enable, bool, NULL, 0444); 49 49 - MODULE_PARM_DESC(enable, "Enable " CARD_NAME " soundcard."); 53 53 + MODULE_PARM_DESC(enable, "Enable VXPocket soundcard."); 50 54 module_param_array(ibl, int, NULL, 0444); 51 51 - MODULE_PARM_DESC(ibl, "Capture IBL size for " CARD_NAME " soundcard."); 55 55 + MODULE_PARM_DESC(ibl, "Capture IBL size for VXPocket soundcard."); 52 56 53 57 54 58 /* 55 59 */ 56 60 57 57 - #ifdef COMPILE_VXP440 61 61 + static unsigned int card_alloc; 62 62 + static dev_link_t *dev_list; /* Linked list of devices */ 63 63 + static dev_info_t dev_info = "snd-vxpocket"; 58 64 59 59 - /* 1 DSP, 1 sync UER, 1 sync World Clock (NIY) */ 60 60 - /* SMPTE (NIY) */ 61 61 - /* 2 stereo analog input (line/micro) */ 62 62 - /* 2 stereo analog output */ 63 63 - /* Only output levels can be modified */ 64 64 - /* UER, but only for the first two inputs and outputs. */ 65 65 66 66 - #define NUM_CODECS 2 67 67 - #define CARD_TYPE VX_TYPE_VXP440 68 68 - #define DEV_INFO "snd-vxp440" 66 66 + static int vxpocket_event(event_t event, int priority, event_callback_args_t *args); 69 67 70 70 - #else 71 68 72 72 - /* 1 DSP, 1 sync UER */ 73 73 - /* 1 programmable clock (NIY) */ 74 74 - /* 1 stereo analog input (line/micro) */ 75 75 - /* 1 stereo analog output */ 76 76 - /* Only output levels can be modified */ 69 69 + /* 70 70 + */ 71 71 + static void vxpocket_release(dev_link_t *link) 72 72 + { 73 73 + if (link->state & DEV_CONFIG) { 74 74 + /* release cs resources */ 75 75 + pcmcia_release_configuration(link->handle); 76 76 + pcmcia_release_io(link->handle, &link->io); 77 77 + pcmcia_release_irq(link->handle, &link->irq); 78 78 + link->state &= ~DEV_CONFIG; 79 79 + } 80 80 + if (link->handle) { 81 81 + /* Break the link with Card Services */ 82 82 + pcmcia_deregister_client(link->handle); 83 83 + link->handle = NULL; 84 84 + } 85 85 + } 77 86 78 78 - #define NUM_CODECS 1 79 79 - #define CARD_TYPE VX_TYPE_VXPOCKET 80 80 - #define DEV_INFO "snd-vxpocket" 87 87 + /* 88 88 + * destructor, called from snd_card_free_in_thread() 89 89 + */ 90 90 + static int snd_vxpocket_dev_free(snd_device_t *device) 91 91 + { 92 92 + vx_core_t *chip = device->device_data; 81 93 82 82 - #endif 94 94 + snd_vx_free_firmware(chip); 95 95 + kfree(chip); 96 96 + return 0; 97 97 + } 83 98 84 84 - static dev_info_t dev_info = DEV_INFO; 85 99 86 86 - static struct snd_vx_hardware vxp_hw = { 87 87 - .name = CARD_NAME, 88 88 - .type = CARD_TYPE, 100 100 + /* 101 101 + * Hardware information 102 102 + */ 103 103 + 104 104 + /* VX-pocket V2 105 105 + * 106 106 + * 1 DSP, 1 sync UER 107 107 + * 1 programmable clock (NIY) 108 108 + * 1 stereo analog input (line/micro) 109 109 + * 1 stereo analog output 110 110 + * Only output levels can be modified 111 111 + */ 112 112 + 113 113 + static struct snd_vx_hardware vxpocket_hw = { 114 114 + .name = "VXPocket", 115 115 + .type = VX_TYPE_VXPOCKET, 89 116 90 117 /* hardware specs */ 91 91 - .num_codecs = NUM_CODECS, 92 92 - .num_ins = NUM_CODECS, 93 93 - .num_outs = NUM_CODECS, 118 118 + .num_codecs = 1, 119 119 + .num_ins = 1, 120 120 + .num_outs = 1, 94 121 .output_level_max = VX_ANALOG_OUT_LEVEL_MAX, 95 122 }; 96 123 97 97 - static struct snd_vxp_entry hw_entry = { 98 98 - .dev_info = &dev_info, 124 124 + /* VX-pocket 440 125 125 + * 126 126 + * 1 DSP, 1 sync UER, 1 sync World Clock (NIY) 127 127 + * SMPTE (NIY) 128 128 + * 2 stereo analog input (line/micro) 129 129 + * 2 stereo analog output 130 130 + * Only output levels can be modified 131 131 + * UER, but only for the first two inputs and outputs. 132 132 + */ 99 133 100 100 - /* module parameters */ 101 101 - .index_table = index, 102 102 - .id_table = id, 103 103 - .enable_table = enable, 104 104 - .ibl = ibl, 134 134 + static struct snd_vx_hardware vxp440_hw = { 135 135 + .name = "VXPocket440", 136 136 + .type = VX_TYPE_VXP440, 105 137 106 106 - /* h/w config */ 107 107 - .hardware = &vxp_hw, 108 108 - .ops = &snd_vxpocket_ops, 109 109 - }; 138 138 + /* hardware specs */ 139 139 + .num_codecs = 2, 140 140 + .num_ins = 2, 141 141 + .num_outs = 2, 142 142 + .output_level_max = VX_ANALOG_OUT_LEVEL_MAX, 143 143 + }; 144 144 + 145 145 + 146 146 + /* 147 147 + * create vxpocket instance 148 148 + */ 149 149 + static struct snd_vxpocket *snd_vxpocket_new(snd_card_t *card, int ibl) 150 150 + { 151 151 + client_reg_t client_reg; /* Register with cardmgr */ 152 152 + dev_link_t *link; /* Info for cardmgr */ 153 153 + vx_core_t *chip; 154 154 + struct snd_vxpocket *vxp; 155 155 + int ret; 156 156 + static snd_device_ops_t ops = { 157 157 + .dev_free = snd_vxpocket_dev_free, 158 158 + }; 159 159 + 160 160 + chip = snd_vx_create(card, &vxpocket_hw, &snd_vxpocket_ops, 161 161 + sizeof(struct snd_vxpocket) - sizeof(vx_core_t)); 162 162 + if (! chip) 163 163 + return NULL; 164 164 + 165 165 + if (snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops) < 0) { 166 166 + kfree(chip); 167 167 + return NULL; 168 168 + } 169 169 + chip->ibl.size = ibl; 170 170 + 171 171 + vxp = (struct snd_vxpocket *)chip; 172 172 + 173 173 + link = &vxp->link; 174 174 + link->priv = chip; 175 175 + 176 176 + link->io.Attributes1 = IO_DATA_PATH_WIDTH_AUTO; 177 177 + link->io.NumPorts1 = 16; 178 178 + 179 179 + link->irq.Attributes = IRQ_TYPE_EXCLUSIVE | IRQ_HANDLE_PRESENT; 180 180 + 181 181 + link->irq.IRQInfo1 = IRQ_LEVEL_ID; 182 182 + link->irq.Handler = &snd_vx_irq_handler; 183 183 + link->irq.Instance = chip; 184 184 + 185 185 + link->conf.Attributes = CONF_ENABLE_IRQ; 186 186 + link->conf.Vcc = 50; 187 187 + link->conf.IntType = INT_MEMORY_AND_IO; 188 188 + link->conf.ConfigIndex = 1; 189 189 + link->conf.Present = PRESENT_OPTION; 190 190 + 191 191 + /* Register with Card Services */ 192 192 + memset(&client_reg, 0, sizeof(client_reg)); 193 193 + client_reg.dev_info = &dev_info; 194 194 + client_reg.EventMask = 195 195 + CS_EVENT_CARD_INSERTION | CS_EVENT_CARD_REMOVAL 196 196 + #ifdef CONFIG_PM 197 197 + | CS_EVENT_RESET_PHYSICAL | CS_EVENT_CARD_RESET 198 198 + | CS_EVENT_PM_SUSPEND | CS_EVENT_PM_RESUME 199 199 + #endif 200 200 + ; 201 201 + client_reg.event_handler = &vxpocket_event; 202 202 + client_reg.Version = 0x0210; 203 203 + client_reg.event_callback_args.client_data = link; 204 204 + 205 205 + ret = pcmcia_register_client(&link->handle, &client_reg); 206 206 + if (ret != CS_SUCCESS) { 207 207 + cs_error(link->handle, RegisterClient, ret); 208 208 + return NULL; 209 209 + } 210 210 + 211 211 + return vxp; 212 212 + } 213 213 + 214 214 + 215 215 + /** 216 216 + * snd_vxpocket_assign_resources - initialize the hardware and card instance. 217 217 + * @port: i/o port for the card 218 218 + * @irq: irq number for the card 219 219 + * 220 220 + * this function assigns the specified port and irq, boot the card, 221 221 + * create pcm and control instances, and initialize the rest hardware. 222 222 + * 223 223 + * returns 0 if successful, or a negative error code. 224 224 + */ 225 225 + static int snd_vxpocket_assign_resources(vx_core_t *chip, int port, int irq) 226 226 + { 227 227 + int err; 228 228 + snd_card_t *card = chip->card; 229 229 + struct snd_vxpocket *vxp = (struct snd_vxpocket *)chip; 230 230 + 231 231 + snd_printdd(KERN_DEBUG "vxpocket assign resources: port = 0x%x, irq = %d\n", port, irq); 232 232 + vxp->port = port; 233 233 + 234 234 + sprintf(card->shortname, "Digigram %s", card->driver); 235 235 + sprintf(card->longname, "%s at 0x%x, irq %i", 236 236 + card->shortname, port, irq); 237 237 + 238 238 + chip->irq = irq; 239 239 + 240 240 + if ((err = snd_vx_setup_firmware(chip)) < 0) 241 241 + return err; 242 242 + 243 243 + return 0; 244 244 + } 245 245 + 246 246 + 247 247 + /* 248 248 + * configuration callback 249 249 + */ 250 250 + 251 251 + #define CS_CHECK(fn, ret) \ 252 252 + do { last_fn = (fn); if ((last_ret = (ret)) != 0) goto cs_failed; } while (0) 253 253 + 254 254 + static void vxpocket_config(dev_link_t *link) 255 255 + { 256 256 + client_handle_t handle = link->handle; 257 257 + vx_core_t *chip = link->priv; 258 258 + struct snd_vxpocket *vxp = (struct snd_vxpocket *)chip; 259 259 + tuple_t tuple; 260 260 + cisparse_t *parse; 261 261 + u_short buf[32]; 262 262 + int last_fn, last_ret; 263 263 + 264 264 + snd_printdd(KERN_DEBUG "vxpocket_config called\n"); 265 265 + parse = kmalloc(sizeof(*parse), GFP_KERNEL); 266 266 + if (! parse) { 267 267 + snd_printk(KERN_ERR "vx: cannot allocate\n"); 268 268 + return; 269 269 + } 270 270 + tuple.Attributes = 0; 271 271 + tuple.TupleData = (cisdata_t *)buf; 272 272 + tuple.TupleDataMax = sizeof(buf); 273 273 + tuple.TupleOffset = 0; 274 274 + tuple.DesiredTuple = CISTPL_CONFIG; 275 275 + CS_CHECK(GetFirstTuple, pcmcia_get_first_tuple(handle, &tuple)); 276 276 + CS_CHECK(GetTupleData, pcmcia_get_tuple_data(handle, &tuple)); 277 277 + CS_CHECK(ParseTuple, pcmcia_parse_tuple(handle, &tuple, parse)); 278 278 + link->conf.ConfigBase = parse->config.base; 279 279 + link->conf.Present = parse->config.rmask[0]; 280 280 + 281 281 + /* redefine hardware record according to the VERSION1 string */ 282 282 + tuple.DesiredTuple = CISTPL_VERS_1; 283 283 + CS_CHECK(GetFirstTuple, pcmcia_get_first_tuple(handle, &tuple)); 284 284 + CS_CHECK(GetTupleData, pcmcia_get_tuple_data(handle, &tuple)); 285 285 + CS_CHECK(ParseTuple, pcmcia_parse_tuple(handle, &tuple, parse)); 286 286 + if (! strcmp(parse->version_1.str + parse->version_1.ofs[1], "VX-POCKET")) { 287 287 + snd_printdd("VX-pocket is detected\n"); 288 288 + } else { 289 289 + snd_printdd("VX-pocket 440 is detected\n"); 290 290 + /* overwrite the hardware information */ 291 291 + chip->hw = &vxp440_hw; 292 292 + chip->type = vxp440_hw.type; 293 293 + strcpy(chip->card->driver, vxp440_hw.name); 294 294 + } 295 295 + 296 296 + /* Configure card */ 297 297 + link->state |= DEV_CONFIG; 298 298 + 299 299 + CS_CHECK(RequestIO, pcmcia_request_io(handle, &link->io)); 300 300 + CS_CHECK(RequestIRQ, pcmcia_request_irq(link->handle, &link->irq)); 301 301 + CS_CHECK(RequestConfiguration, pcmcia_request_configuration(link->handle, &link->conf)); 302 302 + 303 303 + chip->dev = &handle_to_dev(link->handle); 304 304 + 305 305 + if (snd_vxpocket_assign_resources(chip, link->io.BasePort1, link->irq.AssignedIRQ) < 0) 306 306 + goto failed; 307 307 + 308 308 + link->dev = &vxp->node; 309 309 + link->state &= ~DEV_CONFIG_PENDING; 310 310 + kfree(parse); 311 311 + return; 312 312 + 313 313 + cs_failed: 314 314 + cs_error(link->handle, last_fn, last_ret); 315 315 + failed: 316 316 + pcmcia_release_configuration(link->handle); 317 317 + pcmcia_release_io(link->handle, &link->io); 318 318 + pcmcia_release_irq(link->handle, &link->irq); 319 319 + link->state &= ~DEV_CONFIG; 320 320 + kfree(parse); 321 321 + } 322 322 + 323 323 + 324 324 + /* 325 325 + * event callback 326 326 + */ 327 327 + static int vxpocket_event(event_t event, int priority, event_callback_args_t *args) 328 328 + { 329 329 + dev_link_t *link = args->client_data; 330 330 + vx_core_t *chip = link->priv; 331 331 + 332 332 + switch (event) { 333 333 + case CS_EVENT_CARD_REMOVAL: 334 334 + snd_printdd(KERN_DEBUG "CARD_REMOVAL..\n"); 335 335 + link->state &= ~DEV_PRESENT; 336 336 + if (link->state & DEV_CONFIG) 337 337 + chip->chip_status |= VX_STAT_IS_STALE; 338 338 + break; 339 339 + case CS_EVENT_CARD_INSERTION: 340 340 + snd_printdd(KERN_DEBUG "CARD_INSERTION..\n"); 341 341 + link->state |= DEV_PRESENT | DEV_CONFIG_PENDING; 342 342 + vxpocket_config(link); 343 343 + break; 344 344 + #ifdef CONFIG_PM 345 345 + case CS_EVENT_PM_SUSPEND: 346 346 + snd_printdd(KERN_DEBUG "SUSPEND\n"); 347 347 + link->state |= DEV_SUSPEND; 348 348 + if (chip && chip->card->pm_suspend) { 349 349 + snd_printdd(KERN_DEBUG "snd_vx_suspend calling\n"); 350 350 + chip->card->pm_suspend(chip->card, PMSG_SUSPEND); 351 351 + } 352 352 + /* Fall through... */ 353 353 + case CS_EVENT_RESET_PHYSICAL: 354 354 + snd_printdd(KERN_DEBUG "RESET_PHYSICAL\n"); 355 355 + if (link->state & DEV_CONFIG) 356 356 + pcmcia_release_configuration(link->handle); 357 357 + break; 358 358 + case CS_EVENT_PM_RESUME: 359 359 + snd_printdd(KERN_DEBUG "RESUME\n"); 360 360 + link->state &= ~DEV_SUSPEND; 361 361 + /* Fall through... */ 362 362 + case CS_EVENT_CARD_RESET: 363 363 + snd_printdd(KERN_DEBUG "CARD_RESET\n"); 364 364 + if (DEV_OK(link)) { 365 365 + //struct snd_vxpocket *vxp = (struct snd_vxpocket *)chip; 366 366 + snd_printdd(KERN_DEBUG "requestconfig...\n"); 367 367 + pcmcia_request_configuration(link->handle, &link->conf); 368 368 + if (chip && chip->card->pm_resume) { 369 369 + snd_printdd(KERN_DEBUG "calling snd_vx_resume\n"); 370 370 + chip->card->pm_resume(chip->card); 371 371 + } 372 372 + } 373 373 + snd_printdd(KERN_DEBUG "resume done!\n"); 374 374 + break; 375 375 + #endif 376 376 + } 377 377 + return 0; 378 378 + } 379 379 + 110 380 111 381 /* 112 382 */ 113 383 static dev_link_t *vxp_attach(void) 114 384 { 115 115 - return snd_vxpocket_attach(&hw_entry); 385 385 + snd_card_t *card; 386 386 + struct snd_vxpocket *vxp; 387 387 + int i; 388 388 + 389 389 + /* find an empty slot from the card list */ 390 390 + for (i = 0; i < SNDRV_CARDS; i++) { 391 391 + if (! card_alloc & (1 << i)) 392 392 + break; 393 393 + } 394 394 + if (i >= SNDRV_CARDS) { 395 395 + snd_printk(KERN_ERR "vxpocket: too many cards found\n"); 396 396 + return NULL; 397 397 + } 398 398 + if (! enable[i]) 399 399 + return NULL; /* disabled explicitly */ 400 400 + 401 401 + /* ok, create a card instance */ 402 402 + card = snd_card_new(index[i], id[i], THIS_MODULE, 0); 403 403 + if (card == NULL) { 404 404 + snd_printk(KERN_ERR "vxpocket: cannot create a card instance\n"); 405 405 + return NULL; 406 406 + } 407 407 + 408 408 + vxp = snd_vxpocket_new(card, ibl[i]); 409 409 + if (! vxp) { 410 410 + snd_card_free(card); 411 411 + return NULL; 412 412 + } 413 413 + 414 414 + vxp->index = index[i]; 415 415 + card_alloc |= 1 << i; 416 416 + 417 417 + /* Chain drivers */ 418 418 + vxp->link.next = dev_list; 419 419 + dev_list = &vxp->link; 420 420 + 421 421 + return &vxp->link; 116 422 } 117 423 118 424 static void vxp_detach(dev_link_t *link) 119 425 { 120 120 - snd_vxpocket_detach(&hw_entry, link); 426 426 + struct snd_vxpocket *vxp; 427 427 + vx_core_t *chip; 428 428 + dev_link_t **linkp; 429 429 + 430 430 + if (! link) 431 431 + return; 432 432 + 433 433 + vxp = link->priv; 434 434 + chip = (vx_core_t *)vxp; 435 435 + card_alloc &= ~(1 << vxp->index); 436 436 + 437 437 + /* Remove the interface data from the linked list */ 438 438 + for (linkp = &dev_list; *linkp; linkp = &(*linkp)->next) 439 439 + if (*linkp == link) { 440 440 + *linkp = link->next; 441 441 + break; 442 442 + } 443 443 + 444 444 + chip->chip_status |= VX_STAT_IS_STALE; /* to be sure */ 445 445 + snd_card_disconnect(chip->card); 446 446 + vxpocket_release(link); 447 447 + snd_card_free_in_thread(chip->card); 121 448 } 122 449 123 450 /* ··· 456 137 static struct pcmcia_driver vxp_cs_driver = { 457 138 .owner = THIS_MODULE, 458 139 .drv = { 459 459 - .name = DEV_INFO, 140 140 + .name = "snd-vxpocket", 460 141 }, 461 142 .attach = vxp_attach, 462 143 .detach = vxp_detach, ··· 471 152 static void __exit exit_vxpocket(void) 472 153 { 473 154 pcmcia_unregister_driver(&vxp_cs_driver); 474 474 - BUG_ON(hw_entry.dev_list != NULL); 155 155 + BUG_ON(dev_list != NULL); 475 156 } 476 157 477 158 module_init(init_vxpocket);

+1 -26

sound/pcmcia/vx/vxpocket.h

reviewed

··· 28 28 #include <pcmcia/cistpl.h> 29 29 #include <pcmcia/ds.h> 30 30 31 31 - struct snd_vxp_entry { 32 32 - dev_info_t *dev_info; 33 33 - 34 34 - /* module parameters */ 35 35 - int *index_table; 36 36 - char **id_table; 37 37 - int *enable_table; 38 38 - int *ibl; 39 39 - 40 40 - /* h/w config */ 41 41 - struct snd_vx_hardware *hardware; 42 42 - struct snd_vx_ops *ops; 43 43 - 44 44 - /* slots */ 45 45 - vx_core_t *card_list[SNDRV_CARDS]; 46 46 - dev_link_t *dev_list; /* Linked list of devices */ 47 47 - }; 48 48 - 49 31 struct snd_vxpocket { 50 32 51 33 vx_core_t core; ··· 39 57 unsigned int regCDSP; /* current CDSP register */ 40 58 unsigned int regDIALOG; /* current DIALOG register */ 41 59 42 42 - int index; 43 43 - struct snd_vxp_entry *hw_entry; 60 60 + int index; /* card index */ 44 61 45 62 /* pcmcia stuff */ 46 63 dev_link_t link; ··· 50 69 51 70 void vx_set_mic_boost(vx_core_t *chip, int boost); 52 71 void vx_set_mic_level(vx_core_t *chip, int level); 53 53 - 54 54 - /* 55 55 - * pcmcia stuff 56 56 - */ 57 57 - dev_link_t *snd_vxpocket_attach(struct snd_vxp_entry *hw); 58 58 - void snd_vxpocket_detach(struct snd_vxp_entry *hw, dev_link_t *link); 59 72 60 73 int vxp_add_mic_controls(vx_core_t *chip); 61 74

+3 -3

sound/ppc/awacs.c

reviewed

··· 103 103 snd_pmac_awacs_write_noreg(chip, 1, chip->awacs_reg[1]); 104 104 if (chip->manufacturer == 0x1) 105 105 /* delay for broken crystal part */ 106 106 - big_mdelay(750); 106 106 + msleep(750); 107 107 snd_pmac_awacs_write_noreg(chip, 1, 108 108 chip->awacs_reg[1] | MASK_RECALIBRATE | MASK_CMUTE | MASK_AMUTE); 109 109 snd_pmac_awacs_write_noreg(chip, 1, chip->awacs_reg[1]); ··· 653 653 { 654 654 if (machine_is_compatible("PowerBook3,1") 655 655 || machine_is_compatible("PowerBook3,2")) { 656 656 - big_mdelay(100); 656 656 + msleep(100); 657 657 snd_pmac_awacs_write_reg(chip, 1, 658 658 chip->awacs_reg[1] & ~MASK_PAROUT); 659 659 - big_mdelay(300); 659 659 + msleep(300); 660 660 } 661 661 662 662 awacs_restore_all_regs(chip);

-5

sound/ppc/pmac.h

reviewed

··· 212 212 213 213 int snd_pmac_add_automute(pmac_t *chip); 214 214 215 215 - #define big_mdelay(msec) do {\ 216 216 - set_current_state(TASK_UNINTERRUPTIBLE);\ 217 217 - schedule_timeout(((msec) * HZ + 999) / 1000);\ 218 218 - } while (0) 219 219 - 220 215 #endif /* __PMAC_H */

+8 -8

sound/ppc/tumbler.c

reviewed

··· 945 945 check_mute(chip, &mix->line_mute, 0, mix->auto_mute_notify, 946 946 chip->lineout_sw_ctl); 947 947 if (mix->anded_reset) 948 948 - big_mdelay(10); 948 948 + msleep(10); 949 949 check_mute(chip, &mix->amp_mute, 1, mix->auto_mute_notify, 950 950 chip->speaker_sw_ctl); 951 951 mix->drc_enable = 0; ··· 954 954 check_mute(chip, &mix->amp_mute, 0, mix->auto_mute_notify, 955 955 chip->speaker_sw_ctl); 956 956 if (mix->anded_reset) 957 957 - big_mdelay(10); 957 957 + msleep(10); 958 958 check_mute(chip, &mix->hp_mute, 1, mix->auto_mute_notify, 959 959 chip->master_sw_ctl); 960 960 if (mix->line_mute.addr != 0) ··· 1109 1109 DBG("(I) codec anded reset !\n"); 1110 1110 write_audio_gpio(&mix->hp_mute, 0); 1111 1111 write_audio_gpio(&mix->amp_mute, 0); 1112 1112 - big_mdelay(200); 1112 1112 + msleep(200); 1113 1113 write_audio_gpio(&mix->hp_mute, 1); 1114 1114 write_audio_gpio(&mix->amp_mute, 1); 1115 1115 - big_mdelay(100); 1115 1115 + msleep(100); 1116 1116 write_audio_gpio(&mix->hp_mute, 0); 1117 1117 write_audio_gpio(&mix->amp_mute, 0); 1118 1118 - big_mdelay(100); 1118 1118 + msleep(100); 1119 1119 } else { 1120 1120 DBG("(I) codec normal reset !\n"); 1121 1121 1122 1122 write_audio_gpio(&mix->audio_reset, 0); 1123 1123 - big_mdelay(200); 1123 1123 + msleep(200); 1124 1124 write_audio_gpio(&mix->audio_reset, 1); 1125 1125 - big_mdelay(100); 1125 1125 + msleep(100); 1126 1126 write_audio_gpio(&mix->audio_reset, 0); 1127 1127 - big_mdelay(100); 1127 1127 + msleep(100); 1128 1128 } 1129 1129 } 1130 1130

+20 -2

sound/sparc/Kconfig

reviewed

··· 7 7 tristate "Sun AMD7930" 8 8 depends on SBUS && SND 9 9 select SND_PCM 10 10 + help 11 11 + Say Y here to include support for AMD7930 sound device on Sun. 10 12 11 11 - # dep_tristate 'Sun DBRI' CONFIG_SND_SUN_DBRI $CONFIG_SND 13 13 + To compile this driver as a module, choose M here: the module 14 14 + will be called snd-sun-amd7930. 15 15 + 12 16 config SND_SUN_CS4231 13 17 tristate "Sun CS4231" 14 18 depends on SND 15 19 select SND_PCM 20 20 + help 21 21 + Say Y here to include support for CS4231 sound device on Sun. 22 22 + 23 23 + To compile this driver as a module, choose M here: the module 24 24 + will be called snd-sun-cs4231. 25 25 + 26 26 + config SND_SUN_DBRI 27 27 + tristate "Sun DBRI" 28 28 + depends on SND && SBUS 29 29 + select SND_PCM 30 30 + help 31 31 + Say Y here to include support for DBRI sound device on Sun. 32 32 + 33 33 + To compile this driver as a module, choose M here: the module 34 34 + will be called snd-sun-dbri. 16 35 17 36 endmenu 18 18 -

+2 -2

sound/sparc/Makefile

reviewed

··· 4 4 # 5 5 6 6 snd-sun-amd7930-objs := amd7930.o 7 7 - #snd-sun-dbri-objs := dbri.o 8 7 snd-sun-cs4231-objs := cs4231.o 8 8 + snd-sun-dbri-objs := dbri.o 9 9 10 10 obj-$(CONFIG_SND_SUN_AMD7930) += snd-sun-amd7930.o 11 11 - #obj-$(CONFIG_SND_SUN_DBRI) += snd-sun-dbri.o 12 11 obj-$(CONFIG_SND_SUN_CS4231) += snd-sun-cs4231.o 12 12 + obj-$(CONFIG_SND_SUN_DBRI) += snd-sun-dbri.o

+2729

sound/sparc/dbri.c

reviewed

··· 1 1 + /* 2 2 + * Driver for DBRI sound chip found on Sparcs. 3 3 + * Copyright (C) 2004 Martin Habets (mhabets@users.sourceforge.net) 4 4 + * 5 5 + * Based entirely upon drivers/sbus/audio/dbri.c which is: 6 6 + * Copyright (C) 1997 Rudolf Koenig (rfkoenig@immd4.informatik.uni-erlangen.de) 7 7 + * Copyright (C) 1998, 1999 Brent Baccala (baccala@freesoft.org) 8 8 + * 9 9 + * This is the lowlevel driver for the DBRI & MMCODEC duo used for ISDN & AUDIO 10 10 + * on Sun SPARCstation 10, 20, LX and Voyager models. 11 11 + * 12 12 + * - DBRI: AT&T T5900FX Dual Basic Rates ISDN Interface. It is a 32 channel 13 13 + * data time multiplexer with ISDN support (aka T7259) 14 14 + * Interfaces: SBus,ISDN NT & TE, CHI, 4 bits parallel. 15 15 + * CHI: (spelled ki) Concentration Highway Interface (AT&T or Intel bus ?). 16 16 + * Documentation: 17 17 + * - "STP 4000SBus Dual Basic Rate ISDN (DBRI) Tranceiver" from 18 18 + * Sparc Technology Business (courtesy of Sun Support) 19 19 + * - Data sheet of the T7903, a newer but very similar ISA bus equivalent 20 20 + * available from the Lucent (formarly AT&T microelectronics) home 21 21 + * page. 22 22 + * - http://www.freesoft.org/Linux/DBRI/ 23 23 + * - MMCODEC: Crystal Semiconductor CS4215 16 bit Multimedia Audio Codec 24 24 + * Interfaces: CHI, Audio In & Out, 2 bits parallel 25 25 + * Documentation: from the Crystal Semiconductor home page. 26 26 + * 27 27 + * The DBRI is a 32 pipe machine, each pipe can transfer some bits between 28 28 + * memory and a serial device (long pipes, nr 0-15) or between two serial 29 29 + * devices (short pipes, nr 16-31), or simply send a fixed data to a serial 30 30 + * device (short pipes). 31 31 + * A timeslot defines the bit-offset and nr of bits read from a serial device. 32 32 + * The timeslots are linked to 6 circular lists, one for each direction for 33 33 + * each serial device (NT,TE,CHI). A timeslot is associated to 1 or 2 pipes 34 34 + * (the second one is a monitor/tee pipe, valid only for serial input). 35 35 + * 36 36 + * The mmcodec is connected via the CHI bus and needs the data & some 37 37 + * parameters (volume, balance, output selection) timemultiplexed in 8 byte 38 38 + * chunks. It also has a control mode, which serves for audio format setting. 39 39 + * 40 40 + * Looking at the CS4215 data sheet it is easy to set up 2 or 4 codecs on 41 41 + * the same CHI bus, so I thought perhaps it is possible to use the onboard 42 42 + * & the speakerbox codec simultanously, giving 2 (not very independent :-) 43 43 + * audio devices. But the SUN HW group decided against it, at least on my 44 44 + * LX the speakerbox connector has at least 1 pin missing and 1 wrongly 45 45 + * connected. 46 46 + */ 47 47 + 48 48 + #include <sound/driver.h> 49 49 + #include <linux/interrupt.h> 50 50 + #include <linux/delay.h> 51 51 + 52 52 + #include <sound/core.h> 53 53 + #include <sound/pcm.h> 54 54 + #include <sound/pcm_params.h> 55 55 + #include <sound/info.h> 56 56 + #include <sound/control.h> 57 57 + #include <sound/initval.h> 58 58 + 59 59 + #include <asm/irq.h> 60 60 + #include <asm/io.h> 61 61 + #include <asm/sbus.h> 62 62 + #include <asm/atomic.h> 63 63 + 64 64 + MODULE_AUTHOR("Rudolf Koenig, Brent Baccala and Martin Habets"); 65 65 + MODULE_DESCRIPTION("Sun DBRI"); 66 66 + MODULE_LICENSE("GPL"); 67 67 + MODULE_SUPPORTED_DEVICE("{{Sun,DBRI}}"); 68 68 + 69 69 + static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */ 70 70 + static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */ 71 71 + static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */ 72 72 + 73 73 + module_param_array(index, int, NULL, 0444); 74 74 + MODULE_PARM_DESC(index, "Index value for Sun DBRI soundcard."); 75 75 + module_param_array(id, charp, NULL, 0444); 76 76 + MODULE_PARM_DESC(id, "ID string for Sun DBRI soundcard."); 77 77 + module_param_array(enable, bool, NULL, 0444); 78 78 + MODULE_PARM_DESC(enable, "Enable Sun DBRI soundcard."); 79 79 + 80 80 + #define DBRI_DEBUG 81 81 + 82 82 + #define D_INT (1<<0) 83 83 + #define D_GEN (1<<1) 84 84 + #define D_CMD (1<<2) 85 85 + #define D_MM (1<<3) 86 86 + #define D_USR (1<<4) 87 87 + #define D_DESC (1<<5) 88 88 + 89 89 + static int dbri_debug = 0; 90 90 + module_param(dbri_debug, int, 0444); 91 91 + MODULE_PARM_DESC(dbri_debug, "Debug value for Sun DBRI soundcard."); 92 92 + 93 93 + #ifdef DBRI_DEBUG 94 94 + static char *cmds[] = { 95 95 + "WAIT", "PAUSE", "JUMP", "IIQ", "REX", "SDP", "CDP", "DTS", 96 96 + "SSP", "CHI", "NT", "TE", "CDEC", "TEST", "CDM", "RESRV" 97 97 + }; 98 98 + 99 99 + #define dprintk(a, x...) if(dbri_debug & a) printk(KERN_DEBUG x) 100 100 + 101 101 + #define DBRI_CMD(cmd, intr, value) ((cmd << 28) | \ 102 102 + (1 << 27) | \ 103 103 + value) 104 104 + #else 105 105 + #define dprintk(a, x...) 106 106 + 107 107 + #define DBRI_CMD(cmd, intr, value) ((cmd << 28) | \ 108 108 + (intr << 27) | \ 109 109 + value) 110 110 + #endif /* DBRI_DEBUG */ 111 111 + 112 112 + /*************************************************************************** 113 113 + CS4215 specific definitions and structures 114 114 + ****************************************************************************/ 115 115 + 116 116 + struct cs4215 { 117 117 + __u8 data[4]; /* Data mode: Time slots 5-8 */ 118 118 + __u8 ctrl[4]; /* Ctrl mode: Time slots 1-4 */ 119 119 + __u8 onboard; 120 120 + __u8 offset; /* Bit offset from frame sync to time slot 1 */ 121 121 + volatile __u32 status; 122 122 + volatile __u32 version; 123 123 + __u8 precision; /* In bits, either 8 or 16 */ 124 124 + __u8 channels; /* 1 or 2 */ 125 125 + }; 126 126 + 127 127 + /* 128 128 + * Control mode first 129 129 + */ 130 130 + 131 131 + /* Time Slot 1, Status register */ 132 132 + #define CS4215_CLB (1<<2) /* Control Latch Bit */ 133 133 + #define CS4215_OLB (1<<3) /* 1: line: 2.0V, speaker 4V */ 134 134 + /* 0: line: 2.8V, speaker 8V */ 135 135 + #define CS4215_MLB (1<<4) /* 1: Microphone: 20dB gain disabled */ 136 136 + #define CS4215_RSRVD_1 (1<<5) 137 137 + 138 138 + /* Time Slot 2, Data Format Register */ 139 139 + #define CS4215_DFR_LINEAR16 0 140 140 + #define CS4215_DFR_ULAW 1 141 141 + #define CS4215_DFR_ALAW 2 142 142 + #define CS4215_DFR_LINEAR8 3 143 143 + #define CS4215_DFR_STEREO (1<<2) 144 144 + static struct { 145 145 + unsigned short freq; 146 146 + unsigned char xtal; 147 147 + unsigned char csval; 148 148 + } CS4215_FREQ[] = { 149 149 + { 8000, (1 << 4), (0 << 3) }, 150 150 + { 16000, (1 << 4), (1 << 3) }, 151 151 + { 27429, (1 << 4), (2 << 3) }, /* Actually 24428.57 */ 152 152 + { 32000, (1 << 4), (3 << 3) }, 153 153 + /* { NA, (1 << 4), (4 << 3) }, */ 154 154 + /* { NA, (1 << 4), (5 << 3) }, */ 155 155 + { 48000, (1 << 4), (6 << 3) }, 156 156 + { 9600, (1 << 4), (7 << 3) }, 157 157 + { 5513, (2 << 4), (0 << 3) }, /* Actually 5512.5 */ 158 158 + { 11025, (2 << 4), (1 << 3) }, 159 159 + { 18900, (2 << 4), (2 << 3) }, 160 160 + { 22050, (2 << 4), (3 << 3) }, 161 161 + { 37800, (2 << 4), (4 << 3) }, 162 162 + { 44100, (2 << 4), (5 << 3) }, 163 163 + { 33075, (2 << 4), (6 << 3) }, 164 164 + { 6615, (2 << 4), (7 << 3) }, 165 165 + { 0, 0, 0} 166 166 + }; 167 167 + 168 168 + #define CS4215_HPF (1<<7) /* High Pass Filter, 1: Enabled */ 169 169 + 170 170 + #define CS4215_12_MASK 0xfcbf /* Mask off reserved bits in slot 1 & 2 */ 171 171 + 172 172 + /* Time Slot 3, Serial Port Control register */ 173 173 + #define CS4215_XEN (1<<0) /* 0: Enable serial output */ 174 174 + #define CS4215_XCLK (1<<1) /* 1: Master mode: Generate SCLK */ 175 175 + #define CS4215_BSEL_64 (0<<2) /* Bitrate: 64 bits per frame */ 176 176 + #define CS4215_BSEL_128 (1<<2) 177 177 + #define CS4215_BSEL_256 (2<<2) 178 178 + #define CS4215_MCK_MAST (0<<4) /* Master clock */ 179 179 + #define CS4215_MCK_XTL1 (1<<4) /* 24.576 MHz clock source */ 180 180 + #define CS4215_MCK_XTL2 (2<<4) /* 16.9344 MHz clock source */ 181 181 + #define CS4215_MCK_CLK1 (3<<4) /* Clockin, 256 x Fs */ 182 182 + #define CS4215_MCK_CLK2 (4<<4) /* Clockin, see DFR */ 183 183 + 184 184 + /* Time Slot 4, Test Register */ 185 185 + #define CS4215_DAD (1<<0) /* 0:Digital-Dig loop, 1:Dig-Analog-Dig loop */ 186 186 + #define CS4215_ENL (1<<1) /* Enable Loopback Testing */ 187 187 + 188 188 + /* Time Slot 5, Parallel Port Register */ 189 189 + /* Read only here and the same as the in data mode */ 190 190 + 191 191 + /* Time Slot 6, Reserved */ 192 192 + 193 193 + /* Time Slot 7, Version Register */ 194 194 + #define CS4215_VERSION_MASK 0xf /* Known versions 0/C, 1/D, 2/E */ 195 195 + 196 196 + /* Time Slot 8, Reserved */ 197 197 + 198 198 + /* 199 199 + * Data mode 200 200 + */ 201 201 + /* Time Slot 1-2: Left Channel Data, 2-3: Right Channel Data */ 202 202 + 203 203 + /* Time Slot 5, Output Setting */ 204 204 + #define CS4215_LO(v) v /* Left Output Attenuation 0x3f: -94.5 dB */ 205 205 + #define CS4215_LE (1<<6) /* Line Out Enable */ 206 206 + #define CS4215_HE (1<<7) /* Headphone Enable */ 207 207 + 208 208 + /* Time Slot 6, Output Setting */ 209 209 + #define CS4215_RO(v) v /* Right Output Attenuation 0x3f: -94.5 dB */ 210 210 + #define CS4215_SE (1<<6) /* Speaker Enable */ 211 211 + #define CS4215_ADI (1<<7) /* A/D Data Invalid: Busy in calibration */ 212 212 + 213 213 + /* Time Slot 7, Input Setting */ 214 214 + #define CS4215_LG(v) v /* Left Gain Setting 0xf: 22.5 dB */ 215 215 + #define CS4215_IS (1<<4) /* Input Select: 1=Microphone, 0=Line */ 216 216 + #define CS4215_OVR (1<<5) /* 1: Overrange condition occurred */ 217 217 + #define CS4215_PIO0 (1<<6) /* Parallel I/O 0 */ 218 218 + #define CS4215_PIO1 (1<<7) 219 219 + 220 220 + /* Time Slot 8, Input Setting */ 221 221 + #define CS4215_RG(v) v /* Right Gain Setting 0xf: 22.5 dB */ 222 222 + #define CS4215_MA(v) (v<<4) /* Monitor Path Attenuation 0xf: mute */ 223 223 + 224 224 + /*************************************************************************** 225 225 + DBRI specific definitions and structures 226 226 + ****************************************************************************/ 227 227 + 228 228 + /* DBRI main registers */ 229 229 + #define REG0 0x00UL /* Status and Control */ 230 230 + #define REG1 0x04UL /* Mode and Interrupt */ 231 231 + #define REG2 0x08UL /* Parallel IO */ 232 232 + #define REG3 0x0cUL /* Test */ 233 233 + #define REG8 0x20UL /* Command Queue Pointer */ 234 234 + #define REG9 0x24UL /* Interrupt Queue Pointer */ 235 235 + 236 236 + #define DBRI_NO_CMDS 64 237 237 + #define DBRI_NO_INTS 1 /* Note: the value of this define was 238 238 + * originally 2. The ringbuffer to store 239 239 + * interrupts in dma is currently broken. 240 240 + * This is a temporary fix until the ringbuffer 241 241 + * is fixed. 242 242 + */ 243 243 + #define DBRI_INT_BLK 64 244 244 + #define DBRI_NO_DESCS 64 245 245 + #define DBRI_NO_PIPES 32 246 246 + 247 247 + #define DBRI_MM_ONB 1 248 248 + #define DBRI_MM_SB 2 249 249 + 250 250 + #define DBRI_REC 0 251 251 + #define DBRI_PLAY 1 252 252 + #define DBRI_NO_STREAMS 2 253 253 + 254 254 + /* One transmit/receive descriptor */ 255 255 + struct dbri_mem { 256 256 + volatile __u32 word1; 257 257 + volatile __u32 ba; /* Transmit/Receive Buffer Address */ 258 258 + volatile __u32 nda; /* Next Descriptor Address */ 259 259 + volatile __u32 word4; 260 260 + }; 261 261 + 262 262 + /* This structure is in a DMA region where it can accessed by both 263 263 + * the CPU and the DBRI 264 264 + */ 265 265 + struct dbri_dma { 266 266 + volatile s32 cmd[DBRI_NO_CMDS]; /* Place for commands */ 267 267 + volatile s32 intr[DBRI_NO_INTS * DBRI_INT_BLK]; /* Interrupt field */ 268 268 + struct dbri_mem desc[DBRI_NO_DESCS]; /* Xmit/receive descriptors */ 269 269 + }; 270 270 + 271 271 + #define dbri_dma_off(member, elem) \ 272 272 + ((u32)(unsigned long) \ 273 273 + (&(((struct dbri_dma *)0)->member[elem]))) 274 274 + 275 275 + enum in_or_out { PIPEinput, PIPEoutput }; 276 276 + 277 277 + struct dbri_pipe { 278 278 + u32 sdp; /* SDP command word */ 279 279 + enum in_or_out direction; 280 280 + int nextpipe; /* Next pipe in linked list */ 281 281 + int prevpipe; 282 282 + int cycle; /* Offset of timeslot (bits) */ 283 283 + int length; /* Length of timeslot (bits) */ 284 284 + int first_desc; /* Index of first descriptor */ 285 285 + int desc; /* Index of active descriptor */ 286 286 + volatile __u32 *recv_fixed_ptr; /* Ptr to receive fixed data */ 287 287 + }; 288 288 + 289 289 + struct dbri_desc { 290 290 + int inuse; /* Boolean flag */ 291 291 + int next; /* Index of next desc, or -1 */ 292 292 + unsigned int len; 293 293 + }; 294 294 + 295 295 + /* Per stream (playback or record) information */ 296 296 + typedef struct dbri_streaminfo { 297 297 + snd_pcm_substream_t *substream; 298 298 + u32 dvma_buffer; /* Device view of Alsa DMA buffer */ 299 299 + int left; /* # of bytes left in DMA buffer */ 300 300 + int size; /* Size of DMA buffer */ 301 301 + size_t offset; /* offset in user buffer */ 302 302 + int pipe; /* Data pipe used */ 303 303 + int left_gain; /* mixer elements */ 304 304 + int right_gain; 305 305 + int balance; 306 306 + } dbri_streaminfo_t; 307 307 + 308 308 + /* This structure holds the information for both chips (DBRI & CS4215) */ 309 309 + typedef struct snd_dbri { 310 310 + snd_card_t *card; /* ALSA card */ 311 311 + snd_pcm_t *pcm; 312 312 + 313 313 + int regs_size, irq; /* Needed for unload */ 314 314 + struct sbus_dev *sdev; /* SBUS device info */ 315 315 + spinlock_t lock; 316 316 + 317 317 + volatile struct dbri_dma *dma; /* Pointer to our DMA block */ 318 318 + u32 dma_dvma; /* DBRI visible DMA address */ 319 319 + 320 320 + void __iomem *regs; /* dbri HW regs */ 321 321 + int dbri_version; /* 'e' and up is OK */ 322 322 + int dbri_irqp; /* intr queue pointer */ 323 323 + int wait_seen; 324 324 + 325 325 + struct dbri_pipe pipes[DBRI_NO_PIPES]; /* DBRI's 32 data pipes */ 326 326 + struct dbri_desc descs[DBRI_NO_DESCS]; 327 327 + 328 328 + int chi_in_pipe; 329 329 + int chi_out_pipe; 330 330 + int chi_bpf; 331 331 + 332 332 + struct cs4215 mm; /* mmcodec special info */ 333 333 + /* per stream (playback/record) info */ 334 334 + struct dbri_streaminfo stream_info[DBRI_NO_STREAMS]; 335 335 + 336 336 + struct snd_dbri *next; 337 337 + } snd_dbri_t; 338 338 + 339 339 + /* Needed for the ALSA macros to work */ 340 340 + #define chip_t snd_dbri_t 341 341 + 342 342 + #define DBRI_MAX_VOLUME 63 /* Output volume */ 343 343 + #define DBRI_MAX_GAIN 15 /* Input gain */ 344 344 + #define DBRI_RIGHT_BALANCE 255 345 345 + #define DBRI_MID_BALANCE (DBRI_RIGHT_BALANCE >> 1) 346 346 + 347 347 + /* DBRI Reg0 - Status Control Register - defines. (Page 17) */ 348 348 + #define D_P (1<<15) /* Program command & queue pointer valid */ 349 349 + #define D_G (1<<14) /* Allow 4-Word SBus Burst */ 350 350 + #define D_S (1<<13) /* Allow 16-Word SBus Burst */ 351 351 + #define D_E (1<<12) /* Allow 8-Word SBus Burst */ 352 352 + #define D_X (1<<7) /* Sanity Timer Disable */ 353 353 + #define D_T (1<<6) /* Permit activation of the TE interface */ 354 354 + #define D_N (1<<5) /* Permit activation of the NT interface */ 355 355 + #define D_C (1<<4) /* Permit activation of the CHI interface */ 356 356 + #define D_F (1<<3) /* Force Sanity Timer Time-Out */ 357 357 + #define D_D (1<<2) /* Disable Master Mode */ 358 358 + #define D_H (1<<1) /* Halt for Analysis */ 359 359 + #define D_R (1<<0) /* Soft Reset */ 360 360 + 361 361 + /* DBRI Reg1 - Mode and Interrupt Register - defines. (Page 18) */ 362 362 + #define D_LITTLE_END (1<<8) /* Byte Order */ 363 363 + #define D_BIG_END (0<<8) /* Byte Order */ 364 364 + #define D_MRR (1<<4) /* Multiple Error Ack on SBus (readonly) */ 365 365 + #define D_MLE (1<<3) /* Multiple Late Error on SBus (readonly) */ 366 366 + #define D_LBG (1<<2) /* Lost Bus Grant on SBus (readonly) */ 367 367 + #define D_MBE (1<<1) /* Burst Error on SBus (readonly) */ 368 368 + #define D_IR (1<<0) /* Interrupt Indicator (readonly) */ 369 369 + 370 370 + /* DBRI Reg2 - Parallel IO Register - defines. (Page 18) */ 371 371 + #define D_ENPIO3 (1<<7) /* Enable Pin 3 */ 372 372 + #define D_ENPIO2 (1<<6) /* Enable Pin 2 */ 373 373 + #define D_ENPIO1 (1<<5) /* Enable Pin 1 */ 374 374 + #define D_ENPIO0 (1<<4) /* Enable Pin 0 */ 375 375 + #define D_ENPIO (0xf0) /* Enable all the pins */ 376 376 + #define D_PIO3 (1<<3) /* Pin 3: 1: Data mode, 0: Ctrl mode */ 377 377 + #define D_PIO2 (1<<2) /* Pin 2: 1: Onboard PDN */ 378 378 + #define D_PIO1 (1<<1) /* Pin 1: 0: Reset */ 379 379 + #define D_PIO0 (1<<0) /* Pin 0: 1: Speakerbox PDN */ 380 380 + 381 381 + /* DBRI Commands (Page 20) */ 382 382 + #define D_WAIT 0x0 /* Stop execution */ 383 383 + #define D_PAUSE 0x1 /* Flush long pipes */ 384 384 + #define D_JUMP 0x2 /* New command queue */ 385 385 + #define D_IIQ 0x3 /* Initialize Interrupt Queue */ 386 386 + #define D_REX 0x4 /* Report command execution via interrupt */ 387 387 + #define D_SDP 0x5 /* Setup Data Pipe */ 388 388 + #define D_CDP 0x6 /* Continue Data Pipe (reread NULL Pointer) */ 389 389 + #define D_DTS 0x7 /* Define Time Slot */ 390 390 + #define D_SSP 0x8 /* Set short Data Pipe */ 391 391 + #define D_CHI 0x9 /* Set CHI Global Mode */ 392 392 + #define D_NT 0xa /* NT Command */ 393 393 + #define D_TE 0xb /* TE Command */ 394 394 + #define D_CDEC 0xc /* Codec setup */ 395 395 + #define D_TEST 0xd /* No comment */ 396 396 + #define D_CDM 0xe /* CHI Data mode command */ 397 397 + 398 398 + /* Special bits for some commands */ 399 399 + #define D_PIPE(v) ((v)<<0) /* Pipe Nr: 0-15 long, 16-21 short */ 400 400 + 401 401 + /* Setup Data Pipe */ 402 402 + /* IRM */ 403 403 + #define D_SDP_2SAME (1<<18) /* Report 2nd time in a row value rcvd */ 404 404 + #define D_SDP_CHANGE (2<<18) /* Report any changes */ 405 405 + #define D_SDP_EVERY (3<<18) /* Report any changes */ 406 406 + #define D_SDP_EOL (1<<17) /* EOL interrupt enable */ 407 407 + #define D_SDP_IDLE (1<<16) /* HDLC idle interrupt enable */ 408 408 + 409 409 + /* Pipe data MODE */ 410 410 + #define D_SDP_MEM (0<<13) /* To/from memory */ 411 411 + #define D_SDP_HDLC (2<<13) 412 412 + #define D_SDP_HDLC_D (3<<13) /* D Channel (prio control) */ 413 413 + #define D_SDP_SER (4<<13) /* Serial to serial */ 414 414 + #define D_SDP_FIXED (6<<13) /* Short only */ 415 415 + #define D_SDP_MODE(v) ((v)&(7<<13)) 416 416 + 417 417 + #define D_SDP_TO_SER (1<<12) /* Direction */ 418 418 + #define D_SDP_FROM_SER (0<<12) /* Direction */ 419 419 + #define D_SDP_MSB (1<<11) /* Bit order within Byte */ 420 420 + #define D_SDP_LSB (0<<11) /* Bit order within Byte */ 421 421 + #define D_SDP_P (1<<10) /* Pointer Valid */ 422 422 + #define D_SDP_A (1<<8) /* Abort */ 423 423 + #define D_SDP_C (1<<7) /* Clear */ 424 424 + 425 425 + /* Define Time Slot */ 426 426 + #define D_DTS_VI (1<<17) /* Valid Input Time-Slot Descriptor */ 427 427 + #define D_DTS_VO (1<<16) /* Valid Output Time-Slot Descriptor */ 428 428 + #define D_DTS_INS (1<<15) /* Insert Time Slot */ 429 429 + #define D_DTS_DEL (0<<15) /* Delete Time Slot */ 430 430 + #define D_DTS_PRVIN(v) ((v)<<10) /* Previous In Pipe */ 431 431 + #define D_DTS_PRVOUT(v) ((v)<<5) /* Previous Out Pipe */ 432 432 + 433 433 + /* Time Slot defines */ 434 434 + #define D_TS_LEN(v) ((v)<<24) /* Number of bits in this time slot */ 435 435 + #define D_TS_CYCLE(v) ((v)<<14) /* Bit Count at start of TS */ 436 436 + #define D_TS_DI (1<<13) /* Data Invert */ 437 437 + #define D_TS_1CHANNEL (0<<10) /* Single Channel / Normal mode */ 438 438 + #define D_TS_MONITOR (2<<10) /* Monitor pipe */ 439 439 + #define D_TS_NONCONTIG (3<<10) /* Non contiguous mode */ 440 440 + #define D_TS_ANCHOR (7<<10) /* Starting short pipes */ 441 441 + #define D_TS_MON(v) ((v)<<5) /* Monitor Pipe */ 442 442 + #define D_TS_NEXT(v) ((v)<<0) /* Pipe Nr: 0-15 long, 16-21 short */ 443 443 + 444 444 + /* Concentration Highway Interface Modes */ 445 445 + #define D_CHI_CHICM(v) ((v)<<16) /* Clock mode */ 446 446 + #define D_CHI_IR (1<<15) /* Immediate Interrupt Report */ 447 447 + #define D_CHI_EN (1<<14) /* CHIL Interrupt enabled */ 448 448 + #define D_CHI_OD (1<<13) /* Open Drain Enable */ 449 449 + #define D_CHI_FE (1<<12) /* Sample CHIFS on Rising Frame Edge */ 450 450 + #define D_CHI_FD (1<<11) /* Frame Drive */ 451 451 + #define D_CHI_BPF(v) ((v)<<0) /* Bits per Frame */ 452 452 + 453 453 + /* NT: These are here for completeness */ 454 454 + #define D_NT_FBIT (1<<17) /* Frame Bit */ 455 455 + #define D_NT_NBF (1<<16) /* Number of bad frames to loose framing */ 456 456 + #define D_NT_IRM_IMM (1<<15) /* Interrupt Report & Mask: Immediate */ 457 457 + #define D_NT_IRM_EN (1<<14) /* Interrupt Report & Mask: Enable */ 458 458 + #define D_NT_ISNT (1<<13) /* Configfure interface as NT */ 459 459 + #define D_NT_FT (1<<12) /* Fixed Timing */ 460 460 + #define D_NT_EZ (1<<11) /* Echo Channel is Zeros */ 461 461 + #define D_NT_IFA (1<<10) /* Inhibit Final Activation */ 462 462 + #define D_NT_ACT (1<<9) /* Activate Interface */ 463 463 + #define D_NT_MFE (1<<8) /* Multiframe Enable */ 464 464 + #define D_NT_RLB(v) ((v)<<5) /* Remote Loopback */ 465 465 + #define D_NT_LLB(v) ((v)<<2) /* Local Loopback */ 466 466 + #define D_NT_FACT (1<<1) /* Force Activation */ 467 467 + #define D_NT_ABV (1<<0) /* Activate Bipolar Violation */ 468 468 + 469 469 + /* Codec Setup */ 470 470 + #define D_CDEC_CK(v) ((v)<<24) /* Clock Select */ 471 471 + #define D_CDEC_FED(v) ((v)<<12) /* FSCOD Falling Edge Delay */ 472 472 + #define D_CDEC_RED(v) ((v)<<0) /* FSCOD Rising Edge Delay */ 473 473 + 474 474 + /* Test */ 475 475 + #define D_TEST_RAM(v) ((v)<<16) /* RAM Pointer */ 476 476 + #define D_TEST_SIZE(v) ((v)<<11) /* */ 477 477 + #define D_TEST_ROMONOFF 0x5 /* Toggle ROM opcode monitor on/off */ 478 478 + #define D_TEST_PROC 0x6 /* MicroProcessor test */ 479 479 + #define D_TEST_SER 0x7 /* Serial-Controller test */ 480 480 + #define D_TEST_RAMREAD 0x8 /* Copy from Ram to system memory */ 481 481 + #define D_TEST_RAMWRITE 0x9 /* Copy into Ram from system memory */ 482 482 + #define D_TEST_RAMBIST 0xa /* RAM Built-In Self Test */ 483 483 + #define D_TEST_MCBIST 0xb /* Microcontroller Built-In Self Test */ 484 484 + #define D_TEST_DUMP 0xe /* ROM Dump */ 485 485 + 486 486 + /* CHI Data Mode */ 487 487 + #define D_CDM_THI (1<<8) /* Transmit Data on CHIDR Pin */ 488 488 + #define D_CDM_RHI (1<<7) /* Receive Data on CHIDX Pin */ 489 489 + #define D_CDM_RCE (1<<6) /* Receive on Rising Edge of CHICK */ 490 490 + #define D_CDM_XCE (1<<2) /* Transmit Data on Rising Edge of CHICK */ 491 491 + #define D_CDM_XEN (1<<1) /* Transmit Highway Enable */ 492 492 + #define D_CDM_REN (1<<0) /* Receive Highway Enable */ 493 493 + 494 494 + /* The Interrupts */ 495 495 + #define D_INTR_BRDY 1 /* Buffer Ready for processing */ 496 496 + #define D_INTR_MINT 2 /* Marked Interrupt in RD/TD */ 497 497 + #define D_INTR_IBEG 3 /* Flag to idle transition detected (HDLC) */ 498 498 + #define D_INTR_IEND 4 /* Idle to flag transition detected (HDLC) */ 499 499 + #define D_INTR_EOL 5 /* End of List */ 500 500 + #define D_INTR_CMDI 6 /* Command has bean read */ 501 501 + #define D_INTR_XCMP 8 /* Transmission of frame complete */ 502 502 + #define D_INTR_SBRI 9 /* BRI status change info */ 503 503 + #define D_INTR_FXDT 10 /* Fixed data change */ 504 504 + #define D_INTR_CHIL 11 /* CHI lost frame sync (channel 36 only) */ 505 505 + #define D_INTR_COLL 11 /* Unrecoverable D-Channel collision */ 506 506 + #define D_INTR_DBYT 12 /* Dropped by frame slip */ 507 507 + #define D_INTR_RBYT 13 /* Repeated by frame slip */ 508 508 + #define D_INTR_LINT 14 /* Lost Interrupt */ 509 509 + #define D_INTR_UNDR 15 /* DMA underrun */ 510 510 + 511 511 + #define D_INTR_TE 32 512 512 + #define D_INTR_NT 34 513 513 + #define D_INTR_CHI 36 514 514 + #define D_INTR_CMD 38 515 515 + 516 516 + #define D_INTR_GETCHAN(v) (((v)>>24) & 0x3f) 517 517 + #define D_INTR_GETCODE(v) (((v)>>20) & 0xf) 518 518 + #define D_INTR_GETCMD(v) (((v)>>16) & 0xf) 519 519 + #define D_INTR_GETVAL(v) ((v) & 0xffff) 520 520 + #define D_INTR_GETRVAL(v) ((v) & 0xfffff) 521 521 + 522 522 + #define D_P_0 0 /* TE receive anchor */ 523 523 + #define D_P_1 1 /* TE transmit anchor */ 524 524 + #define D_P_2 2 /* NT transmit anchor */ 525 525 + #define D_P_3 3 /* NT receive anchor */ 526 526 + #define D_P_4 4 /* CHI send data */ 527 527 + #define D_P_5 5 /* CHI receive data */ 528 528 + #define D_P_6 6 /* */ 529 529 + #define D_P_7 7 /* */ 530 530 + #define D_P_8 8 /* */ 531 531 + #define D_P_9 9 /* */ 532 532 + #define D_P_10 10 /* */ 533 533 + #define D_P_11 11 /* */ 534 534 + #define D_P_12 12 /* */ 535 535 + #define D_P_13 13 /* */ 536 536 + #define D_P_14 14 /* */ 537 537 + #define D_P_15 15 /* */ 538 538 + #define D_P_16 16 /* CHI anchor pipe */ 539 539 + #define D_P_17 17 /* CHI send */ 540 540 + #define D_P_18 18 /* CHI receive */ 541 541 + #define D_P_19 19 /* CHI receive */ 542 542 + #define D_P_20 20 /* CHI receive */ 543 543 + #define D_P_21 21 /* */ 544 544 + #define D_P_22 22 /* */ 545 545 + #define D_P_23 23 /* */ 546 546 + #define D_P_24 24 /* */ 547 547 + #define D_P_25 25 /* */ 548 548 + #define D_P_26 26 /* */ 549 549 + #define D_P_27 27 /* */ 550 550 + #define D_P_28 28 /* */ 551 551 + #define D_P_29 29 /* */ 552 552 + #define D_P_30 30 /* */ 553 553 + #define D_P_31 31 /* */ 554 554 + 555 555 + /* Transmit descriptor defines */ 556 556 + #define DBRI_TD_F (1<<31) /* End of Frame */ 557 557 + #define DBRI_TD_D (1<<30) /* Do not append CRC */ 558 558 + #define DBRI_TD_CNT(v) ((v)<<16) /* Number of valid bytes in the buffer */ 559 559 + #define DBRI_TD_B (1<<15) /* Final interrupt */ 560 560 + #define DBRI_TD_M (1<<14) /* Marker interrupt */ 561 561 + #define DBRI_TD_I (1<<13) /* Transmit Idle Characters */ 562 562 + #define DBRI_TD_FCNT(v) (v) /* Flag Count */ 563 563 + #define DBRI_TD_UNR (1<<3) /* Underrun: transmitter is out of data */ 564 564 + #define DBRI_TD_ABT (1<<2) /* Abort: frame aborted */ 565 565 + #define DBRI_TD_TBC (1<<0) /* Transmit buffer Complete */ 566 566 + #define DBRI_TD_STATUS(v) ((v)&0xff) /* Transmit status */ 567 567 + /* Maximum buffer size per TD: almost 8Kb */ 568 568 + #define DBRI_TD_MAXCNT ((1 << 13) - 1) 569 569 + 570 570 + /* Receive descriptor defines */ 571 571 + #define DBRI_RD_F (1<<31) /* End of Frame */ 572 572 + #define DBRI_RD_C (1<<30) /* Completed buffer */ 573 573 + #define DBRI_RD_B (1<<15) /* Final interrupt */ 574 574 + #define DBRI_RD_M (1<<14) /* Marker interrupt */ 575 575 + #define DBRI_RD_BCNT(v) (v) /* Buffer size */ 576 576 + #define DBRI_RD_CRC (1<<7) /* 0: CRC is correct */ 577 577 + #define DBRI_RD_BBC (1<<6) /* 1: Bad Byte received */ 578 578 + #define DBRI_RD_ABT (1<<5) /* Abort: frame aborted */ 579 579 + #define DBRI_RD_OVRN (1<<3) /* Overrun: data lost */ 580 580 + #define DBRI_RD_STATUS(v) ((v)&0xff) /* Receive status */ 581 581 + #define DBRI_RD_CNT(v) (((v)>>16)&0x1fff) /* Valid bytes in the buffer */ 582 582 + 583 583 + /* stream_info[] access */ 584 584 + /* Translate the ALSA direction into the array index */ 585 585 + #define DBRI_STREAMNO(substream) \ 586 586 + (substream->stream == \ 587 587 + SNDRV_PCM_STREAM_PLAYBACK? DBRI_PLAY: DBRI_REC) 588 588 + 589 589 + /* Return a pointer to dbri_streaminfo */ 590 590 + #define DBRI_STREAM(dbri, substream) &dbri->stream_info[DBRI_STREAMNO(substream)] 591 591 + 592 592 + static snd_dbri_t *dbri_list = NULL; /* All DBRI devices */ 593 593 + 594 594 + /* 595 595 + * Short data pipes transmit LSB first. The CS4215 receives MSB first. Grrr. 596 596 + * So we have to reverse the bits. Note: not all bit lengths are supported 597 597 + */ 598 598 + static __u32 reverse_bytes(__u32 b, int len) 599 599 + { 600 600 + switch (len) { 601 601 + case 32: 602 602 + b = ((b & 0xffff0000) >> 16) | ((b & 0x0000ffff) << 16); 603 603 + case 16: 604 604 + b = ((b & 0xff00ff00) >> 8) | ((b & 0x00ff00ff) << 8); 605 605 + case 8: 606 606 + b = ((b & 0xf0f0f0f0) >> 4) | ((b & 0x0f0f0f0f) << 4); 607 607 + case 4: 608 608 + b = ((b & 0xcccccccc) >> 2) | ((b & 0x33333333) << 2); 609 609 + case 2: 610 610 + b = ((b & 0xaaaaaaaa) >> 1) | ((b & 0x55555555) << 1); 611 611 + case 1: 612 612 + case 0: 613 613 + break; 614 614 + default: 615 615 + printk(KERN_ERR "DBRI reverse_bytes: unsupported length\n"); 616 616 + }; 617 617 + 618 618 + return b; 619 619 + } 620 620 + 621 621 + /* 622 622 + **************************************************************************** 623 623 + ************** DBRI initialization and command synchronization ************* 624 624 + **************************************************************************** 625 625 + 626 626 + Commands are sent to the DBRI by building a list of them in memory, 627 627 + then writing the address of the first list item to DBRI register 8. 628 628 + The list is terminated with a WAIT command, which can generate a 629 629 + CPU interrupt if required. 630 630 + 631 631 + Since the DBRI can run in parallel with the CPU, several means of 632 632 + synchronization present themselves. The original scheme (Rudolf's) 633 633 + was to set a flag when we "cmdlock"ed the DBRI, clear the flag when 634 634 + an interrupt signaled completion, and wait on a wait_queue if a routine 635 635 + attempted to cmdlock while the flag was set. The problems arose when 636 636 + we tried to cmdlock from inside an interrupt handler, which might 637 637 + cause scheduling in an interrupt (if we waited), etc, etc 638 638 + 639 639 + A more sophisticated scheme might involve a circular command buffer 640 640 + or an array of command buffers. A routine could fill one with 641 641 + commands and link it onto a list. When a interrupt signaled 642 642 + completion of the current command buffer, look on the list for 643 643 + the next one. 644 644 + 645 645 + I've decided to implement something much simpler - after each command, 646 646 + the CPU waits for the DBRI to finish the command by polling the P bit 647 647 + in DBRI register 0. I've tried to implement this in such a way 648 648 + that might make implementing a more sophisticated scheme easier. 649 649 + 650 650 + Every time a routine wants to write commands to the DBRI, it must 651 651 + first call dbri_cmdlock() and get an initial pointer into dbri->dma->cmd 652 652 + in return. After the commands have been writen, dbri_cmdsend() is 653 653 + called with the final pointer value. 654 654 + 655 655 + */ 656 656 + 657 657 + enum dbri_lock_t { NoGetLock, GetLock }; 658 658 + 659 659 + static volatile s32 *dbri_cmdlock(snd_dbri_t * dbri, enum dbri_lock_t get) 660 660 + { 661 661 + #ifndef SMP 662 662 + if ((get == GetLock) && spin_is_locked(&dbri->lock)) { 663 663 + printk(KERN_ERR "DBRI: cmdlock called while in spinlock."); 664 664 + } 665 665 + #endif 666 666 + 667 667 + /*if (get == GetLock) spin_lock(&dbri->lock); */ 668 668 + return &dbri->dma->cmd[0]; 669 669 + } 670 670 + 671 671 + static void dbri_process_interrupt_buffer(snd_dbri_t *); 672 672 + 673 673 + static void dbri_cmdsend(snd_dbri_t * dbri, volatile s32 * cmd) 674 674 + { 675 675 + int MAXLOOPS = 1000000; 676 676 + int maxloops = MAXLOOPS; 677 677 + volatile s32 *ptr; 678 678 + 679 679 + for (ptr = &dbri->dma->cmd[0]; ptr < cmd; ptr++) { 680 680 + dprintk(D_CMD, "cmd: %lx:%08x\n", (unsigned long)ptr, *ptr); 681 681 + } 682 682 + 683 683 + if ((cmd - &dbri->dma->cmd[0]) >= DBRI_NO_CMDS - 1) { 684 684 + printk("DBRI: Command buffer overflow! (bug in driver)\n"); 685 685 + /* Ignore the last part. */ 686 686 + cmd = &dbri->dma->cmd[DBRI_NO_CMDS - 3]; 687 687 + } 688 688 + 689 689 + *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0); 690 690 + *(cmd++) = DBRI_CMD(D_WAIT, 1, 0); 691 691 + dbri->wait_seen = 0; 692 692 + sbus_writel(dbri->dma_dvma, dbri->regs + REG8); 693 693 + while ((--maxloops) > 0 && (sbus_readl(dbri->regs + REG0) & D_P)) 694 694 + barrier(); 695 695 + if (maxloops == 0) { 696 696 + printk(KERN_ERR "DBRI: Chip never completed command buffer\n"); 697 697 + dprintk(D_CMD, "DBRI: Chip never completed command buffer\n"); 698 698 + } else { 699 699 + while ((--maxloops) > 0 && (!dbri->wait_seen)) 700 700 + dbri_process_interrupt_buffer(dbri); 701 701 + if (maxloops == 0) { 702 702 + printk(KERN_ERR "DBRI: Chip never acked WAIT\n"); 703 703 + dprintk(D_CMD, "DBRI: Chip never acked WAIT\n"); 704 704 + } else { 705 705 + dprintk(D_CMD, "Chip completed command " 706 706 + "buffer (%d)\n", MAXLOOPS - maxloops); 707 707 + } 708 708 + } 709 709 + 710 710 + /*spin_unlock(&dbri->lock); */ 711 711 + } 712 712 + 713 713 + /* Lock must be held when calling this */ 714 714 + static void dbri_reset(snd_dbri_t * dbri) 715 715 + { 716 716 + int i; 717 717 + 718 718 + dprintk(D_GEN, "reset 0:%x 2:%x 8:%x 9:%x\n", 719 719 + sbus_readl(dbri->regs + REG0), 720 720 + sbus_readl(dbri->regs + REG2), 721 721 + sbus_readl(dbri->regs + REG8), sbus_readl(dbri->regs + REG9)); 722 722 + 723 723 + sbus_writel(D_R, dbri->regs + REG0); /* Soft Reset */ 724 724 + for (i = 0; (sbus_readl(dbri->regs + REG0) & D_R) && i < 64; i++) 725 725 + udelay(10); 726 726 + } 727 727 + 728 728 + /* Lock must not be held before calling this */ 729 729 + static void dbri_initialize(snd_dbri_t * dbri) 730 730 + { 731 731 + volatile s32 *cmd; 732 732 + u32 dma_addr, tmp; 733 733 + unsigned long flags; 734 734 + int n; 735 735 + 736 736 + spin_lock_irqsave(&dbri->lock, flags); 737 737 + 738 738 + dbri_reset(dbri); 739 739 + 740 740 + cmd = dbri_cmdlock(dbri, NoGetLock); 741 741 + dprintk(D_GEN, "init: cmd: %p, int: %p\n", 742 742 + &dbri->dma->cmd[0], &dbri->dma->intr[0]); 743 743 + 744 744 + /* 745 745 + * Initialize the interrupt ringbuffer. 746 746 + */ 747 747 + for (n = 0; n < DBRI_NO_INTS - 1; n++) { 748 748 + dma_addr = dbri->dma_dvma; 749 749 + dma_addr += dbri_dma_off(intr, ((n + 1) & DBRI_INT_BLK)); 750 750 + dbri->dma->intr[n * DBRI_INT_BLK] = dma_addr; 751 751 + } 752 752 + dma_addr = dbri->dma_dvma + dbri_dma_off(intr, 0); 753 753 + dbri->dma->intr[n * DBRI_INT_BLK] = dma_addr; 754 754 + dbri->dbri_irqp = 1; 755 755 + 756 756 + /* Initialize pipes */ 757 757 + for (n = 0; n < DBRI_NO_PIPES; n++) 758 758 + dbri->pipes[n].desc = dbri->pipes[n].first_desc = -1; 759 759 + 760 760 + /* We should query the openprom to see what burst sizes this 761 761 + * SBus supports. For now, just disable all SBus bursts */ 762 762 + tmp = sbus_readl(dbri->regs + REG0); 763 763 + tmp &= ~(D_G | D_S | D_E); 764 764 + sbus_writel(tmp, dbri->regs + REG0); 765 765 + 766 766 + /* 767 767 + * Set up the interrupt queue 768 768 + */ 769 769 + dma_addr = dbri->dma_dvma + dbri_dma_off(intr, 0); 770 770 + *(cmd++) = DBRI_CMD(D_IIQ, 0, 0); 771 771 + *(cmd++) = dma_addr; 772 772 + 773 773 + dbri_cmdsend(dbri, cmd); 774 774 + spin_unlock_irqrestore(&dbri->lock, flags); 775 775 + } 776 776 + 777 777 + /* 778 778 + **************************************************************************** 779 779 + ************************** DBRI data pipe management *********************** 780 780 + **************************************************************************** 781 781 + 782 782 + While DBRI control functions use the command and interrupt buffers, the 783 783 + main data path takes the form of data pipes, which can be short (command 784 784 + and interrupt driven), or long (attached to DMA buffers). These functions 785 785 + provide a rudimentary means of setting up and managing the DBRI's pipes, 786 786 + but the calling functions have to make sure they respect the pipes' linked 787 787 + list ordering, among other things. The transmit and receive functions 788 788 + here interface closely with the transmit and receive interrupt code. 789 789 + 790 790 + */ 791 791 + static int pipe_active(snd_dbri_t * dbri, int pipe) 792 792 + { 793 793 + return ((pipe >= 0) && (dbri->pipes[pipe].desc != -1)); 794 794 + } 795 795 + 796 796 + /* reset_pipe(dbri, pipe) 797 797 + * 798 798 + * Called on an in-use pipe to clear anything being transmitted or received 799 799 + * Lock must be held before calling this. 800 800 + */ 801 801 + static void reset_pipe(snd_dbri_t * dbri, int pipe) 802 802 + { 803 803 + int sdp; 804 804 + int desc; 805 805 + volatile int *cmd; 806 806 + 807 807 + if (pipe < 0 || pipe > 31) { 808 808 + printk("DBRI: reset_pipe called with illegal pipe number\n"); 809 809 + return; 810 810 + } 811 811 + 812 812 + sdp = dbri->pipes[pipe].sdp; 813 813 + if (sdp == 0) { 814 814 + printk("DBRI: reset_pipe called on uninitialized pipe\n"); 815 815 + return; 816 816 + } 817 817 + 818 818 + cmd = dbri_cmdlock(dbri, NoGetLock); 819 819 + *(cmd++) = DBRI_CMD(D_SDP, 0, sdp | D_SDP_C | D_SDP_P); 820 820 + *(cmd++) = 0; 821 821 + dbri_cmdsend(dbri, cmd); 822 822 + 823 823 + desc = dbri->pipes[pipe].first_desc; 824 824 + while (desc != -1) { 825 825 + dbri->descs[desc].inuse = 0; 826 826 + desc = dbri->descs[desc].next; 827 827 + } 828 828 + 829 829 + dbri->pipes[pipe].desc = -1; 830 830 + dbri->pipes[pipe].first_desc = -1; 831 831 + } 832 832 + 833 833 + /* FIXME: direction as an argument? */ 834 834 + static void setup_pipe(snd_dbri_t * dbri, int pipe, int sdp) 835 835 + { 836 836 + if (pipe < 0 || pipe > 31) { 837 837 + printk("DBRI: setup_pipe called with illegal pipe number\n"); 838 838 + return; 839 839 + } 840 840 + 841 841 + if ((sdp & 0xf800) != sdp) { 842 842 + printk("DBRI: setup_pipe called with strange SDP value\n"); 843 843 + /* sdp &= 0xf800; */ 844 844 + } 845 845 + 846 846 + /* If this is a fixed receive pipe, arrange for an interrupt 847 847 + * every time its data changes 848 848 + */ 849 849 + if (D_SDP_MODE(sdp) == D_SDP_FIXED && !(sdp & D_SDP_TO_SER)) 850 850 + sdp |= D_SDP_CHANGE; 851 851 + 852 852 + sdp |= D_PIPE(pipe); 853 853 + dbri->pipes[pipe].sdp = sdp; 854 854 + dbri->pipes[pipe].desc = -1; 855 855 + dbri->pipes[pipe].first_desc = -1; 856 856 + if (sdp & D_SDP_TO_SER) 857 857 + dbri->pipes[pipe].direction = PIPEoutput; 858 858 + else 859 859 + dbri->pipes[pipe].direction = PIPEinput; 860 860 + 861 861 + reset_pipe(dbri, pipe); 862 862 + } 863 863 + 864 864 + /* FIXME: direction not needed */ 865 865 + static void link_time_slot(snd_dbri_t * dbri, int pipe, 866 866 + enum in_or_out direction, int basepipe, 867 867 + int length, int cycle) 868 868 + { 869 869 + volatile s32 *cmd; 870 870 + int val; 871 871 + int prevpipe; 872 872 + int nextpipe; 873 873 + 874 874 + if (pipe < 0 || pipe > 31 || basepipe < 0 || basepipe > 31) { 875 875 + printk 876 876 + ("DBRI: link_time_slot called with illegal pipe number\n"); 877 877 + return; 878 878 + } 879 879 + 880 880 + if (dbri->pipes[pipe].sdp == 0 || dbri->pipes[basepipe].sdp == 0) { 881 881 + printk("DBRI: link_time_slot called on uninitialized pipe\n"); 882 882 + return; 883 883 + } 884 884 + 885 885 + /* Deal with CHI special case: 886 886 + * "If transmission on edges 0 or 1 is desired, then cycle n 887 887 + * (where n = # of bit times per frame...) must be used." 888 888 + * - DBRI data sheet, page 11 889 889 + */ 890 890 + if (basepipe == 16 && direction == PIPEoutput && cycle == 0) 891 891 + cycle = dbri->chi_bpf; 892 892 + 893 893 + if (basepipe == pipe) { 894 894 + prevpipe = pipe; 895 895 + nextpipe = pipe; 896 896 + } else { 897 897 + /* We're not initializing a new linked list (basepipe != pipe), 898 898 + * so run through the linked list and find where this pipe 899 899 + * should be sloted in, based on its cycle. CHI confuses 900 900 + * things a bit, since it has a single anchor for both its 901 901 + * transmit and receive lists. 902 902 + */ 903 903 + if (basepipe == 16) { 904 904 + if (direction == PIPEinput) { 905 905 + prevpipe = dbri->chi_in_pipe; 906 906 + } else { 907 907 + prevpipe = dbri->chi_out_pipe; 908 908 + } 909 909 + } else { 910 910 + prevpipe = basepipe; 911 911 + } 912 912 + 913 913 + nextpipe = dbri->pipes[prevpipe].nextpipe; 914 914 + 915 915 + while (dbri->pipes[nextpipe].cycle < cycle 916 916 + && dbri->pipes[nextpipe].nextpipe != basepipe) { 917 917 + prevpipe = nextpipe; 918 918 + nextpipe = dbri->pipes[nextpipe].nextpipe; 919 919 + } 920 920 + } 921 921 + 922 922 + if (prevpipe == 16) { 923 923 + if (direction == PIPEinput) { 924 924 + dbri->chi_in_pipe = pipe; 925 925 + } else { 926 926 + dbri->chi_out_pipe = pipe; 927 927 + } 928 928 + } else { 929 929 + dbri->pipes[prevpipe].nextpipe = pipe; 930 930 + } 931 931 + 932 932 + dbri->pipes[pipe].nextpipe = nextpipe; 933 933 + dbri->pipes[pipe].cycle = cycle; 934 934 + dbri->pipes[pipe].length = length; 935 935 + 936 936 + cmd = dbri_cmdlock(dbri, NoGetLock); 937 937 + 938 938 + if (direction == PIPEinput) { 939 939 + val = D_DTS_VI | D_DTS_INS | D_DTS_PRVIN(prevpipe) | pipe; 940 940 + *(cmd++) = DBRI_CMD(D_DTS, 0, val); 941 941 + *(cmd++) = 942 942 + D_TS_LEN(length) | D_TS_CYCLE(cycle) | D_TS_NEXT(nextpipe); 943 943 + *(cmd++) = 0; 944 944 + } else { 945 945 + val = D_DTS_VO | D_DTS_INS | D_DTS_PRVOUT(prevpipe) | pipe; 946 946 + *(cmd++) = DBRI_CMD(D_DTS, 0, val); 947 947 + *(cmd++) = 0; 948 948 + *(cmd++) = 949 949 + D_TS_LEN(length) | D_TS_CYCLE(cycle) | D_TS_NEXT(nextpipe); 950 950 + } 951 951 + 952 952 + dbri_cmdsend(dbri, cmd); 953 953 + } 954 954 + 955 955 + static void unlink_time_slot(snd_dbri_t * dbri, int pipe, 956 956 + enum in_or_out direction, int prevpipe, 957 957 + int nextpipe) 958 958 + { 959 959 + volatile s32 *cmd; 960 960 + int val; 961 961 + 962 962 + if (pipe < 0 || pipe > 31 || prevpipe < 0 || prevpipe > 31) { 963 963 + printk 964 964 + ("DBRI: unlink_time_slot called with illegal pipe number\n"); 965 965 + return; 966 966 + } 967 967 + 968 968 + cmd = dbri_cmdlock(dbri, NoGetLock); 969 969 + 970 970 + if (direction == PIPEinput) { 971 971 + val = D_DTS_VI | D_DTS_DEL | D_DTS_PRVIN(prevpipe) | pipe; 972 972 + *(cmd++) = DBRI_CMD(D_DTS, 0, val); 973 973 + *(cmd++) = D_TS_NEXT(nextpipe); 974 974 + *(cmd++) = 0; 975 975 + } else { 976 976 + val = D_DTS_VO | D_DTS_DEL | D_DTS_PRVOUT(prevpipe) | pipe; 977 977 + *(cmd++) = DBRI_CMD(D_DTS, 0, val); 978 978 + *(cmd++) = 0; 979 979 + *(cmd++) = D_TS_NEXT(nextpipe); 980 980 + } 981 981 + 982 982 + dbri_cmdsend(dbri, cmd); 983 983 + } 984 984 + 985 985 + /* xmit_fixed() / recv_fixed() 986 986 + * 987 987 + * Transmit/receive data on a "fixed" pipe - i.e, one whose contents are not 988 988 + * expected to change much, and which we don't need to buffer. 989 989 + * The DBRI only interrupts us when the data changes (receive pipes), 990 990 + * or only changes the data when this function is called (transmit pipes). 991 991 + * Only short pipes (numbers 16-31) can be used in fixed data mode. 992 992 + * 993 993 + * These function operate on a 32-bit field, no matter how large 994 994 + * the actual time slot is. The interrupt handler takes care of bit 995 995 + * ordering and alignment. An 8-bit time slot will always end up 996 996 + * in the low-order 8 bits, filled either MSB-first or LSB-first, 997 997 + * depending on the settings passed to setup_pipe() 998 998 + */ 999 999 + static void xmit_fixed(snd_dbri_t * dbri, int pipe, unsigned int data) 1000 1000 + { 1001 1001 + volatile s32 *cmd; 1002 1002 + 1003 1003 + if (pipe < 16 || pipe > 31) { 1004 1004 + printk("DBRI: xmit_fixed: Illegal pipe number\n"); 1005 1005 + return; 1006 1006 + } 1007 1007 + 1008 1008 + if (D_SDP_MODE(dbri->pipes[pipe].sdp) == 0) { 1009 1009 + printk("DBRI: xmit_fixed: Uninitialized pipe %d\n", pipe); 1010 1010 + return; 1011 1011 + } 1012 1012 + 1013 1013 + if (D_SDP_MODE(dbri->pipes[pipe].sdp) != D_SDP_FIXED) { 1014 1014 + printk("DBRI: xmit_fixed: Non-fixed pipe %d\n", pipe); 1015 1015 + return; 1016 1016 + } 1017 1017 + 1018 1018 + if (!(dbri->pipes[pipe].sdp & D_SDP_TO_SER)) { 1019 1019 + printk("DBRI: xmit_fixed: Called on receive pipe %d\n", pipe); 1020 1020 + return; 1021 1021 + } 1022 1022 + 1023 1023 + /* DBRI short pipes always transmit LSB first */ 1024 1024 + 1025 1025 + if (dbri->pipes[pipe].sdp & D_SDP_MSB) 1026 1026 + data = reverse_bytes(data, dbri->pipes[pipe].length); 1027 1027 + 1028 1028 + cmd = dbri_cmdlock(dbri, GetLock); 1029 1029 + 1030 1030 + *(cmd++) = DBRI_CMD(D_SSP, 0, pipe); 1031 1031 + *(cmd++) = data; 1032 1032 + 1033 1033 + dbri_cmdsend(dbri, cmd); 1034 1034 + } 1035 1035 + 1036 1036 + static void recv_fixed(snd_dbri_t * dbri, int pipe, volatile __u32 * ptr) 1037 1037 + { 1038 1038 + if (pipe < 16 || pipe > 31) { 1039 1039 + printk("DBRI: recv_fixed called with illegal pipe number\n"); 1040 1040 + return; 1041 1041 + } 1042 1042 + 1043 1043 + if (D_SDP_MODE(dbri->pipes[pipe].sdp) != D_SDP_FIXED) { 1044 1044 + printk("DBRI: recv_fixed called on non-fixed pipe %d\n", pipe); 1045 1045 + return; 1046 1046 + } 1047 1047 + 1048 1048 + if (dbri->pipes[pipe].sdp & D_SDP_TO_SER) { 1049 1049 + printk("DBRI: recv_fixed called on transmit pipe %d\n", pipe); 1050 1050 + return; 1051 1051 + } 1052 1052 + 1053 1053 + dbri->pipes[pipe].recv_fixed_ptr = ptr; 1054 1054 + } 1055 1055 + 1056 1056 + /* setup_descs() 1057 1057 + * 1058 1058 + * Setup transmit/receive data on a "long" pipe - i.e, one associated 1059 1059 + * with a DMA buffer. 1060 1060 + * 1061 1061 + * Only pipe numbers 0-15 can be used in this mode. 1062 1062 + * 1063 1063 + * This function takes a stream number pointing to a data buffer, 1064 1064 + * and work by building chains of descriptors which identify the 1065 1065 + * data buffers. Buffers too large for a single descriptor will 1066 1066 + * be spread across multiple descriptors. 1067 1067 + */ 1068 1068 + static int setup_descs(snd_dbri_t * dbri, int streamno, unsigned int period) 1069 1069 + { 1070 1070 + dbri_streaminfo_t *info = &dbri->stream_info[streamno]; 1071 1071 + __u32 dvma_buffer; 1072 1072 + int desc = 0; 1073 1073 + int len; 1074 1074 + int first_desc = -1; 1075 1075 + int last_desc = -1; 1076 1076 + 1077 1077 + if (info->pipe < 0 || info->pipe > 15) { 1078 1078 + printk("DBRI: setup_descs: Illegal pipe number\n"); 1079 1079 + return -2; 1080 1080 + } 1081 1081 + 1082 1082 + if (dbri->pipes[info->pipe].sdp == 0) { 1083 1083 + printk("DBRI: setup_descs: Uninitialized pipe %d\n", 1084 1084 + info->pipe); 1085 1085 + return -2; 1086 1086 + } 1087 1087 + 1088 1088 + dvma_buffer = info->dvma_buffer; 1089 1089 + len = info->size; 1090 1090 + 1091 1091 + if (streamno == DBRI_PLAY) { 1092 1092 + if (!(dbri->pipes[info->pipe].sdp & D_SDP_TO_SER)) { 1093 1093 + printk("DBRI: setup_descs: Called on receive pipe %d\n", 1094 1094 + info->pipe); 1095 1095 + return -2; 1096 1096 + } 1097 1097 + } else { 1098 1098 + if (dbri->pipes[info->pipe].sdp & D_SDP_TO_SER) { 1099 1099 + printk 1100 1100 + ("DBRI: setup_descs: Called on transmit pipe %d\n", 1101 1101 + info->pipe); 1102 1102 + return -2; 1103 1103 + } 1104 1104 + /* Should be able to queue multiple buffers to receive on a pipe */ 1105 1105 + if (pipe_active(dbri, info->pipe)) { 1106 1106 + printk("DBRI: recv_on_pipe: Called on active pipe %d\n", 1107 1107 + info->pipe); 1108 1108 + return -2; 1109 1109 + } 1110 1110 + 1111 1111 + /* Make sure buffer size is multiple of four */ 1112 1112 + len &= ~3; 1113 1113 + } 1114 1114 + 1115 1115 + while (len > 0) { 1116 1116 + int mylen; 1117 1117 + 1118 1118 + for (; desc < DBRI_NO_DESCS; desc++) { 1119 1119 + if (!dbri->descs[desc].inuse) 1120 1120 + break; 1121 1121 + } 1122 1122 + if (desc == DBRI_NO_DESCS) { 1123 1123 + printk("DBRI: setup_descs: No descriptors\n"); 1124 1124 + return -1; 1125 1125 + } 1126 1126 + 1127 1127 + if (len > DBRI_TD_MAXCNT) { 1128 1128 + mylen = DBRI_TD_MAXCNT; /* 8KB - 1 */ 1129 1129 + } else { 1130 1130 + mylen = len; 1131 1131 + } 1132 1132 + if (mylen > period) { 1133 1133 + mylen = period; 1134 1134 + } 1135 1135 + 1136 1136 + dbri->descs[desc].inuse = 1; 1137 1137 + dbri->descs[desc].next = -1; 1138 1138 + dbri->dma->desc[desc].ba = dvma_buffer; 1139 1139 + dbri->dma->desc[desc].nda = 0; 1140 1140 + 1141 1141 + if (streamno == DBRI_PLAY) { 1142 1142 + dbri->descs[desc].len = mylen; 1143 1143 + dbri->dma->desc[desc].word1 = DBRI_TD_CNT(mylen); 1144 1144 + dbri->dma->desc[desc].word4 = 0; 1145 1145 + if (first_desc != -1) 1146 1146 + dbri->dma->desc[desc].word1 |= DBRI_TD_M; 1147 1147 + } else { 1148 1148 + dbri->descs[desc].len = 0; 1149 1149 + dbri->dma->desc[desc].word1 = 0; 1150 1150 + dbri->dma->desc[desc].word4 = 1151 1151 + DBRI_RD_B | DBRI_RD_BCNT(mylen); 1152 1152 + } 1153 1153 + 1154 1154 + if (first_desc == -1) { 1155 1155 + first_desc = desc; 1156 1156 + } else { 1157 1157 + dbri->descs[last_desc].next = desc; 1158 1158 + dbri->dma->desc[last_desc].nda = 1159 1159 + dbri->dma_dvma + dbri_dma_off(desc, desc); 1160 1160 + } 1161 1161 + 1162 1162 + last_desc = desc; 1163 1163 + dvma_buffer += mylen; 1164 1164 + len -= mylen; 1165 1165 + } 1166 1166 + 1167 1167 + if (first_desc == -1 || last_desc == -1) { 1168 1168 + printk("DBRI: setup_descs: Not enough descriptors available\n"); 1169 1169 + return -1; 1170 1170 + } 1171 1171 + 1172 1172 + dbri->dma->desc[last_desc].word1 &= ~DBRI_TD_M; 1173 1173 + if (streamno == DBRI_PLAY) { 1174 1174 + dbri->dma->desc[last_desc].word1 |= 1175 1175 + DBRI_TD_I | DBRI_TD_F | DBRI_TD_B; 1176 1176 + } 1177 1177 + dbri->pipes[info->pipe].first_desc = first_desc; 1178 1178 + dbri->pipes[info->pipe].desc = first_desc; 1179 1179 + 1180 1180 + for (desc = first_desc; desc != -1; desc = dbri->descs[desc].next) { 1181 1181 + dprintk(D_DESC, "DESC %d: %08x %08x %08x %08x\n", 1182 1182 + desc, 1183 1183 + dbri->dma->desc[desc].word1, 1184 1184 + dbri->dma->desc[desc].ba, 1185 1185 + dbri->dma->desc[desc].nda, dbri->dma->desc[desc].word4); 1186 1186 + } 1187 1187 + return 0; 1188 1188 + } 1189 1189 + 1190 1190 + /* 1191 1191 + **************************************************************************** 1192 1192 + ************************** DBRI - CHI interface **************************** 1193 1193 + **************************************************************************** 1194 1194 + 1195 1195 + The CHI is a four-wire (clock, frame sync, data in, data out) time-division 1196 1196 + multiplexed serial interface which the DBRI can operate in either master 1197 1197 + (give clock/frame sync) or slave (take clock/frame sync) mode. 1198 1198 + 1199 1199 + */ 1200 1200 + 1201 1201 + enum master_or_slave { CHImaster, CHIslave }; 1202 1202 + 1203 1203 + static void reset_chi(snd_dbri_t * dbri, enum master_or_slave master_or_slave, 1204 1204 + int bits_per_frame) 1205 1205 + { 1206 1206 + volatile s32 *cmd; 1207 1207 + int val; 1208 1208 + static int chi_initialized = 0; /* FIXME: mutex? */ 1209 1209 + 1210 1210 + if (!chi_initialized) { 1211 1211 + 1212 1212 + cmd = dbri_cmdlock(dbri, GetLock); 1213 1213 + 1214 1214 + /* Set CHI Anchor: Pipe 16 */ 1215 1215 + 1216 1216 + val = D_DTS_VI | D_DTS_INS | D_DTS_PRVIN(16) | D_PIPE(16); 1217 1217 + *(cmd++) = DBRI_CMD(D_DTS, 0, val); 1218 1218 + *(cmd++) = D_TS_ANCHOR | D_TS_NEXT(16); 1219 1219 + *(cmd++) = 0; 1220 1220 + 1221 1221 + val = D_DTS_VO | D_DTS_INS | D_DTS_PRVOUT(16) | D_PIPE(16); 1222 1222 + *(cmd++) = DBRI_CMD(D_DTS, 0, val); 1223 1223 + *(cmd++) = 0; 1224 1224 + *(cmd++) = D_TS_ANCHOR | D_TS_NEXT(16); 1225 1225 + 1226 1226 + dbri->pipes[16].sdp = 1; 1227 1227 + dbri->pipes[16].nextpipe = 16; 1228 1228 + dbri->chi_in_pipe = 16; 1229 1229 + dbri->chi_out_pipe = 16; 1230 1230 + 1231 1231 + #if 0 1232 1232 + chi_initialized++; 1233 1233 + #endif 1234 1234 + } else { 1235 1235 + int pipe; 1236 1236 + 1237 1237 + for (pipe = dbri->chi_in_pipe; 1238 1238 + pipe != 16; pipe = dbri->pipes[pipe].nextpipe) { 1239 1239 + unlink_time_slot(dbri, pipe, PIPEinput, 1240 1240 + 16, dbri->pipes[pipe].nextpipe); 1241 1241 + } 1242 1242 + for (pipe = dbri->chi_out_pipe; 1243 1243 + pipe != 16; pipe = dbri->pipes[pipe].nextpipe) { 1244 1244 + unlink_time_slot(dbri, pipe, PIPEoutput, 1245 1245 + 16, dbri->pipes[pipe].nextpipe); 1246 1246 + } 1247 1247 + 1248 1248 + dbri->chi_in_pipe = 16; 1249 1249 + dbri->chi_out_pipe = 16; 1250 1250 + 1251 1251 + cmd = dbri_cmdlock(dbri, GetLock); 1252 1252 + } 1253 1253 + 1254 1254 + if (master_or_slave == CHIslave) { 1255 1255 + /* Setup DBRI for CHI Slave - receive clock, frame sync (FS) 1256 1256 + * 1257 1257 + * CHICM = 0 (slave mode, 8 kHz frame rate) 1258 1258 + * IR = give immediate CHI status interrupt 1259 1259 + * EN = give CHI status interrupt upon change 1260 1260 + */ 1261 1261 + *(cmd++) = DBRI_CMD(D_CHI, 0, D_CHI_CHICM(0)); 1262 1262 + } else { 1263 1263 + /* Setup DBRI for CHI Master - generate clock, FS 1264 1264 + * 1265 1265 + * BPF = bits per 8 kHz frame 1266 1266 + * 12.288 MHz / CHICM_divisor = clock rate 1267 1267 + * FD = 1 - drive CHIFS on rising edge of CHICK 1268 1268 + */ 1269 1269 + int clockrate = bits_per_frame * 8; 1270 1270 + int divisor = 12288 / clockrate; 1271 1271 + 1272 1272 + if (divisor > 255 || divisor * clockrate != 12288) 1273 1273 + printk("DBRI: illegal bits_per_frame in setup_chi\n"); 1274 1274 + 1275 1275 + *(cmd++) = DBRI_CMD(D_CHI, 0, D_CHI_CHICM(divisor) | D_CHI_FD 1276 1276 + | D_CHI_BPF(bits_per_frame)); 1277 1277 + } 1278 1278 + 1279 1279 + dbri->chi_bpf = bits_per_frame; 1280 1280 + 1281 1281 + /* CHI Data Mode 1282 1282 + * 1283 1283 + * RCE = 0 - receive on falling edge of CHICK 1284 1284 + * XCE = 1 - transmit on rising edge of CHICK 1285 1285 + * XEN = 1 - enable transmitter 1286 1286 + * REN = 1 - enable receiver 1287 1287 + */ 1288 1288 + 1289 1289 + *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0); 1290 1290 + *(cmd++) = DBRI_CMD(D_CDM, 0, D_CDM_XCE | D_CDM_XEN | D_CDM_REN); 1291 1291 + 1292 1292 + dbri_cmdsend(dbri, cmd); 1293 1293 + } 1294 1294 + 1295 1295 + /* 1296 1296 + **************************************************************************** 1297 1297 + *********************** CS4215 audio codec management ********************** 1298 1298 + **************************************************************************** 1299 1299 + 1300 1300 + In the standard SPARC audio configuration, the CS4215 codec is attached 1301 1301 + to the DBRI via the CHI interface and few of the DBRI's PIO pins. 1302 1302 + 1303 1303 + */ 1304 1304 + static void cs4215_setup_pipes(snd_dbri_t * dbri) 1305 1305 + { 1306 1306 + /* 1307 1307 + * Data mode: 1308 1308 + * Pipe 4: Send timeslots 1-4 (audio data) 1309 1309 + * Pipe 20: Send timeslots 5-8 (part of ctrl data) 1310 1310 + * Pipe 6: Receive timeslots 1-4 (audio data) 1311 1311 + * Pipe 21: Receive timeslots 6-7. We can only receive 20 bits via 1312 1312 + * interrupt, and the rest of the data (slot 5 and 8) is 1313 1313 + * not relevant for us (only for doublechecking). 1314 1314 + * 1315 1315 + * Control mode: 1316 1316 + * Pipe 17: Send timeslots 1-4 (slots 5-8 are readonly) 1317 1317 + * Pipe 18: Receive timeslot 1 (clb). 1318 1318 + * Pipe 19: Receive timeslot 7 (version). 1319 1319 + */ 1320 1320 + 1321 1321 + setup_pipe(dbri, 4, D_SDP_MEM | D_SDP_TO_SER | D_SDP_MSB); 1322 1322 + setup_pipe(dbri, 20, D_SDP_FIXED | D_SDP_TO_SER | D_SDP_MSB); 1323 1323 + setup_pipe(dbri, 6, D_SDP_MEM | D_SDP_FROM_SER | D_SDP_MSB); 1324 1324 + setup_pipe(dbri, 21, D_SDP_FIXED | D_SDP_FROM_SER | D_SDP_MSB); 1325 1325 + 1326 1326 + setup_pipe(dbri, 17, D_SDP_FIXED | D_SDP_TO_SER | D_SDP_MSB); 1327 1327 + setup_pipe(dbri, 18, D_SDP_FIXED | D_SDP_FROM_SER | D_SDP_MSB); 1328 1328 + setup_pipe(dbri, 19, D_SDP_FIXED | D_SDP_FROM_SER | D_SDP_MSB); 1329 1329 + } 1330 1330 + 1331 1331 + static int cs4215_init_data(struct cs4215 *mm) 1332 1332 + { 1333 1333 + /* 1334 1334 + * No action, memory resetting only. 1335 1335 + * 1336 1336 + * Data Time Slot 5-8 1337 1337 + * Speaker,Line and Headphone enable. Gain set to the half. 1338 1338 + * Input is mike. 1339 1339 + */ 1340 1340 + mm->data[0] = CS4215_LO(0x20) | CS4215_HE | CS4215_LE; 1341 1341 + mm->data[1] = CS4215_RO(0x20) | CS4215_SE; 1342 1342 + mm->data[2] = CS4215_LG(0x8) | CS4215_IS | CS4215_PIO0 | CS4215_PIO1; 1343 1343 + mm->data[3] = CS4215_RG(0x8) | CS4215_MA(0xf); 1344 1344 + 1345 1345 + /* 1346 1346 + * Control Time Slot 1-4 1347 1347 + * 0: Default I/O voltage scale 1348 1348 + * 1: 8 bit ulaw, 8kHz, mono, high pass filter disabled 1349 1349 + * 2: Serial enable, CHI master, 128 bits per frame, clock 1 1350 1350 + * 3: Tests disabled 1351 1351 + */ 1352 1352 + mm->ctrl[0] = CS4215_RSRVD_1 | CS4215_MLB; 1353 1353 + mm->ctrl[1] = CS4215_DFR_ULAW | CS4215_FREQ[0].csval; 1354 1354 + mm->ctrl[2] = CS4215_XCLK | CS4215_BSEL_128 | CS4215_FREQ[0].xtal; 1355 1355 + mm->ctrl[3] = 0; 1356 1356 + 1357 1357 + mm->status = 0; 1358 1358 + mm->version = 0xff; 1359 1359 + mm->precision = 8; /* For ULAW */ 1360 1360 + mm->channels = 2; 1361 1361 + 1362 1362 + return 0; 1363 1363 + } 1364 1364 + 1365 1365 + static void cs4215_setdata(snd_dbri_t * dbri, int muted) 1366 1366 + { 1367 1367 + if (muted) { 1368 1368 + dbri->mm.data[0] |= 63; 1369 1369 + dbri->mm.data[1] |= 63; 1370 1370 + dbri->mm.data[2] &= ~15; 1371 1371 + dbri->mm.data[3] &= ~15; 1372 1372 + } else { 1373 1373 + /* Start by setting the playback attenuation. */ 1374 1374 + dbri_streaminfo_t *info = &dbri->stream_info[DBRI_PLAY]; 1375 1375 + int left_gain = info->left_gain % 64; 1376 1376 + int right_gain = info->right_gain % 64; 1377 1377 + 1378 1378 + if (info->balance < DBRI_MID_BALANCE) { 1379 1379 + right_gain *= info->balance; 1380 1380 + right_gain /= DBRI_MID_BALANCE; 1381 1381 + } else { 1382 1382 + left_gain *= DBRI_RIGHT_BALANCE - info->balance; 1383 1383 + left_gain /= DBRI_MID_BALANCE; 1384 1384 + } 1385 1385 + 1386 1386 + dbri->mm.data[0] &= ~0x3f; /* Reset the volume bits */ 1387 1387 + dbri->mm.data[1] &= ~0x3f; 1388 1388 + dbri->mm.data[0] |= (DBRI_MAX_VOLUME - left_gain); 1389 1389 + dbri->mm.data[1] |= (DBRI_MAX_VOLUME - right_gain); 1390 1390 + 1391 1391 + /* Now set the recording gain. */ 1392 1392 + info = &dbri->stream_info[DBRI_REC]; 1393 1393 + left_gain = info->left_gain % 16; 1394 1394 + right_gain = info->right_gain % 16; 1395 1395 + dbri->mm.data[2] |= CS4215_LG(left_gain); 1396 1396 + dbri->mm.data[3] |= CS4215_RG(right_gain); 1397 1397 + } 1398 1398 + 1399 1399 + xmit_fixed(dbri, 20, *(int *)dbri->mm.data); 1400 1400 + } 1401 1401 + 1402 1402 + /* 1403 1403 + * Set the CS4215 to data mode. 1404 1404 + */ 1405 1405 + static void cs4215_open(snd_dbri_t * dbri) 1406 1406 + { 1407 1407 + int data_width; 1408 1408 + u32 tmp; 1409 1409 + 1410 1410 + dprintk(D_MM, "cs4215_open: %d channels, %d bits\n", 1411 1411 + dbri->mm.channels, dbri->mm.precision); 1412 1412 + 1413 1413 + /* Temporarily mute outputs, and wait 1/8000 sec (125 us) 1414 1414 + * to make sure this takes. This avoids clicking noises. 1415 1415 + */ 1416 1416 + 1417 1417 + cs4215_setdata(dbri, 1); 1418 1418 + udelay(125); 1419 1419 + 1420 1420 + /* 1421 1421 + * Data mode: 1422 1422 + * Pipe 4: Send timeslots 1-4 (audio data) 1423 1423 + * Pipe 20: Send timeslots 5-8 (part of ctrl data) 1424 1424 + * Pipe 6: Receive timeslots 1-4 (audio data) 1425 1425 + * Pipe 21: Receive timeslots 6-7. We can only receive 20 bits via 1426 1426 + * interrupt, and the rest of the data (slot 5 and 8) is 1427 1427 + * not relevant for us (only for doublechecking). 1428 1428 + * 1429 1429 + * Just like in control mode, the time slots are all offset by eight 1430 1430 + * bits. The CS4215, it seems, observes TSIN (the delayed signal) 1431 1431 + * even if it's the CHI master. Don't ask me... 1432 1432 + */ 1433 1433 + tmp = sbus_readl(dbri->regs + REG0); 1434 1434 + tmp &= ~(D_C); /* Disable CHI */ 1435 1435 + sbus_writel(tmp, dbri->regs + REG0); 1436 1436 + 1437 1437 + /* Switch CS4215 to data mode - set PIO3 to 1 */ 1438 1438 + sbus_writel(D_ENPIO | D_PIO1 | D_PIO3 | 1439 1439 + (dbri->mm.onboard ? D_PIO0 : D_PIO2), dbri->regs + REG2); 1440 1440 + 1441 1441 + reset_chi(dbri, CHIslave, 128); 1442 1442 + 1443 1443 + /* Note: this next doesn't work for 8-bit stereo, because the two 1444 1444 + * channels would be on timeslots 1 and 3, with 2 and 4 idle. 1445 1445 + * (See CS4215 datasheet Fig 15) 1446 1446 + * 1447 1447 + * DBRI non-contiguous mode would be required to make this work. 1448 1448 + */ 1449 1449 + data_width = dbri->mm.channels * dbri->mm.precision; 1450 1450 + 1451 1451 + link_time_slot(dbri, 20, PIPEoutput, 16, 32, dbri->mm.offset + 32); 1452 1452 + link_time_slot(dbri, 4, PIPEoutput, 16, data_width, dbri->mm.offset); 1453 1453 + link_time_slot(dbri, 6, PIPEinput, 16, data_width, dbri->mm.offset); 1454 1454 + link_time_slot(dbri, 21, PIPEinput, 16, 16, dbri->mm.offset + 40); 1455 1455 + 1456 1456 + /* FIXME: enable CHI after _setdata? */ 1457 1457 + tmp = sbus_readl(dbri->regs + REG0); 1458 1458 + tmp |= D_C; /* Enable CHI */ 1459 1459 + sbus_writel(tmp, dbri->regs + REG0); 1460 1460 + 1461 1461 + cs4215_setdata(dbri, 0); 1462 1462 + } 1463 1463 + 1464 1464 + /* 1465 1465 + * Send the control information (i.e. audio format) 1466 1466 + */ 1467 1467 + static int cs4215_setctrl(snd_dbri_t * dbri) 1468 1468 + { 1469 1469 + int i, val; 1470 1470 + u32 tmp; 1471 1471 + 1472 1472 + /* FIXME - let the CPU do something useful during these delays */ 1473 1473 + 1474 1474 + /* Temporarily mute outputs, and wait 1/8000 sec (125 us) 1475 1475 + * to make sure this takes. This avoids clicking noises. 1476 1476 + */ 1477 1477 + 1478 1478 + cs4215_setdata(dbri, 1); 1479 1479 + udelay(125); 1480 1480 + 1481 1481 + /* 1482 1482 + * Enable Control mode: Set DBRI's PIO3 (4215's D/~C) to 0, then wait 1483 1483 + * 12 cycles <= 12/(5512.5*64) sec = 34.01 usec 1484 1484 + */ 1485 1485 + val = D_ENPIO | D_PIO1 | (dbri->mm.onboard ? D_PIO0 : D_PIO2); 1486 1486 + sbus_writel(val, dbri->regs + REG2); 1487 1487 + dprintk(D_MM, "cs4215_setctrl: reg2=0x%x\n", val); 1488 1488 + udelay(34); 1489 1489 + 1490 1490 + /* In Control mode, the CS4215 is a slave device, so the DBRI must 1491 1491 + * operate as CHI master, supplying clocking and frame synchronization. 1492 1492 + * 1493 1493 + * In Data mode, however, the CS4215 must be CHI master to insure 1494 1494 + * that its data stream is synchronous with its codec. 1495 1495 + * 1496 1496 + * The upshot of all this? We start by putting the DBRI into master 1497 1497 + * mode, program the CS4215 in Control mode, then switch the CS4215 1498 1498 + * into Data mode and put the DBRI into slave mode. Various timing 1499 1499 + * requirements must be observed along the way. 1500 1500 + * 1501 1501 + * Oh, and one more thing, on a SPARCStation 20 (and maybe 1502 1502 + * others?), the addressing of the CS4215's time slots is 1503 1503 + * offset by eight bits, so we add eight to all the "cycle" 1504 1504 + * values in the Define Time Slot (DTS) commands. This is 1505 1505 + * done in hardware by a TI 248 that delays the DBRI->4215 1506 1506 + * frame sync signal by eight clock cycles. Anybody know why? 1507 1507 + */ 1508 1508 + tmp = sbus_readl(dbri->regs + REG0); 1509 1509 + tmp &= ~D_C; /* Disable CHI */ 1510 1510 + sbus_writel(tmp, dbri->regs + REG0); 1511 1511 + 1512 1512 + reset_chi(dbri, CHImaster, 128); 1513 1513 + 1514 1514 + /* 1515 1515 + * Control mode: 1516 1516 + * Pipe 17: Send timeslots 1-4 (slots 5-8 are readonly) 1517 1517 + * Pipe 18: Receive timeslot 1 (clb). 1518 1518 + * Pipe 19: Receive timeslot 7 (version). 1519 1519 + */ 1520 1520 + 1521 1521 + link_time_slot(dbri, 17, PIPEoutput, 16, 32, dbri->mm.offset); 1522 1522 + link_time_slot(dbri, 18, PIPEinput, 16, 8, dbri->mm.offset); 1523 1523 + link_time_slot(dbri, 19, PIPEinput, 16, 8, dbri->mm.offset + 48); 1524 1524 + 1525 1525 + /* Wait for the chip to echo back CLB (Control Latch Bit) as zero */ 1526 1526 + dbri->mm.ctrl[0] &= ~CS4215_CLB; 1527 1527 + xmit_fixed(dbri, 17, *(int *)dbri->mm.ctrl); 1528 1528 + 1529 1529 + tmp = sbus_readl(dbri->regs + REG0); 1530 1530 + tmp |= D_C; /* Enable CHI */ 1531 1531 + sbus_writel(tmp, dbri->regs + REG0); 1532 1532 + 1533 1533 + for (i = 64; ((dbri->mm.status & 0xe4) != 0x20); --i) { 1534 1534 + udelay(125); 1535 1535 + } 1536 1536 + if (i == 0) { 1537 1537 + dprintk(D_MM, "CS4215 didn't respond to CLB (0x%02x)\n", 1538 1538 + dbri->mm.status); 1539 1539 + return -1; 1540 1540 + } 1541 1541 + 1542 1542 + /* Disable changes to our copy of the version number, as we are about 1543 1543 + * to leave control mode. 1544 1544 + */ 1545 1545 + recv_fixed(dbri, 19, NULL); 1546 1546 + 1547 1547 + /* Terminate CS4215 control mode - data sheet says 1548 1548 + * "Set CLB=1 and send two more frames of valid control info" 1549 1549 + */ 1550 1550 + dbri->mm.ctrl[0] |= CS4215_CLB; 1551 1551 + xmit_fixed(dbri, 17, *(int *)dbri->mm.ctrl); 1552 1552 + 1553 1553 + /* Two frames of control info @ 8kHz frame rate = 250 us delay */ 1554 1554 + udelay(250); 1555 1555 + 1556 1556 + cs4215_setdata(dbri, 0); 1557 1557 + 1558 1558 + return 0; 1559 1559 + } 1560 1560 + 1561 1561 + /* 1562 1562 + * Setup the codec with the sampling rate, audio format and number of 1563 1563 + * channels. 1564 1564 + * As part of the process we resend the settings for the data 1565 1565 + * timeslots as well. 1566 1566 + */ 1567 1567 + static int cs4215_prepare(snd_dbri_t * dbri, unsigned int rate, 1568 1568 + snd_pcm_format_t format, unsigned int channels) 1569 1569 + { 1570 1570 + int freq_idx; 1571 1571 + int ret = 0; 1572 1572 + 1573 1573 + /* Lookup index for this rate */ 1574 1574 + for (freq_idx = 0; CS4215_FREQ[freq_idx].freq != 0; freq_idx++) { 1575 1575 + if (CS4215_FREQ[freq_idx].freq == rate) 1576 1576 + break; 1577 1577 + } 1578 1578 + if (CS4215_FREQ[freq_idx].freq != rate) { 1579 1579 + printk(KERN_WARNING "DBRI: Unsupported rate %d Hz\n", rate); 1580 1580 + return -1; 1581 1581 + } 1582 1582 + 1583 1583 + switch (format) { 1584 1584 + case SNDRV_PCM_FORMAT_MU_LAW: 1585 1585 + dbri->mm.ctrl[1] = CS4215_DFR_ULAW; 1586 1586 + dbri->mm.precision = 8; 1587 1587 + break; 1588 1588 + case SNDRV_PCM_FORMAT_A_LAW: 1589 1589 + dbri->mm.ctrl[1] = CS4215_DFR_ALAW; 1590 1590 + dbri->mm.precision = 8; 1591 1591 + break; 1592 1592 + case SNDRV_PCM_FORMAT_U8: 1593 1593 + dbri->mm.ctrl[1] = CS4215_DFR_LINEAR8; 1594 1594 + dbri->mm.precision = 8; 1595 1595 + break; 1596 1596 + case SNDRV_PCM_FORMAT_S16_BE: 1597 1597 + dbri->mm.ctrl[1] = CS4215_DFR_LINEAR16; 1598 1598 + dbri->mm.precision = 16; 1599 1599 + break; 1600 1600 + default: 1601 1601 + printk(KERN_WARNING "DBRI: Unsupported format %d\n", format); 1602 1602 + return -1; 1603 1603 + } 1604 1604 + 1605 1605 + /* Add rate parameters */ 1606 1606 + dbri->mm.ctrl[1] |= CS4215_FREQ[freq_idx].csval; 1607 1607 + dbri->mm.ctrl[2] = CS4215_XCLK | 1608 1608 + CS4215_BSEL_128 | CS4215_FREQ[freq_idx].xtal; 1609 1609 + 1610 1610 + dbri->mm.channels = channels; 1611 1611 + /* Stereo bit: 8 bit stereo not working yet. */ 1612 1612 + if ((channels > 1) && (dbri->mm.precision == 16)) 1613 1613 + dbri->mm.ctrl[1] |= CS4215_DFR_STEREO; 1614 1614 + 1615 1615 + ret = cs4215_setctrl(dbri); 1616 1616 + if (ret == 0) 1617 1617 + cs4215_open(dbri); /* set codec to data mode */ 1618 1618 + 1619 1619 + return ret; 1620 1620 + } 1621 1621 + 1622 1622 + /* 1623 1623 + * 1624 1624 + */ 1625 1625 + static int cs4215_init(snd_dbri_t * dbri) 1626 1626 + { 1627 1627 + u32 reg2 = sbus_readl(dbri->regs + REG2); 1628 1628 + dprintk(D_MM, "cs4215_init: reg2=0x%x\n", reg2); 1629 1629 + 1630 1630 + /* Look for the cs4215 chips */ 1631 1631 + if (reg2 & D_PIO2) { 1632 1632 + dprintk(D_MM, "Onboard CS4215 detected\n"); 1633 1633 + dbri->mm.onboard = 1; 1634 1634 + } 1635 1635 + if (reg2 & D_PIO0) { 1636 1636 + dprintk(D_MM, "Speakerbox detected\n"); 1637 1637 + dbri->mm.onboard = 0; 1638 1638 + 1639 1639 + if (reg2 & D_PIO2) { 1640 1640 + printk(KERN_INFO "DBRI: Using speakerbox / " 1641 1641 + "ignoring onboard mmcodec.\n"); 1642 1642 + sbus_writel(D_ENPIO2, dbri->regs + REG2); 1643 1643 + } 1644 1644 + } 1645 1645 + 1646 1646 + if (!(reg2 & (D_PIO0 | D_PIO2))) { 1647 1647 + printk(KERN_ERR "DBRI: no mmcodec found.\n"); 1648 1648 + return -EIO; 1649 1649 + } 1650 1650 + 1651 1651 + cs4215_setup_pipes(dbri); 1652 1652 + 1653 1653 + cs4215_init_data(&dbri->mm); 1654 1654 + 1655 1655 + /* Enable capture of the status & version timeslots. */ 1656 1656 + recv_fixed(dbri, 18, &dbri->mm.status); 1657 1657 + recv_fixed(dbri, 19, &dbri->mm.version); 1658 1658 + 1659 1659 + dbri->mm.offset = dbri->mm.onboard ? 0 : 8; 1660 1660 + if (cs4215_setctrl(dbri) == -1 || dbri->mm.version == 0xff) { 1661 1661 + dprintk(D_MM, "CS4215 failed probe at offset %d\n", 1662 1662 + dbri->mm.offset); 1663 1663 + return -EIO; 1664 1664 + } 1665 1665 + dprintk(D_MM, "Found CS4215 at offset %d\n", dbri->mm.offset); 1666 1666 + 1667 1667 + return 0; 1668 1668 + } 1669 1669 + 1670 1670 + /* 1671 1671 + **************************************************************************** 1672 1672 + *************************** DBRI interrupt handler ************************* 1673 1673 + **************************************************************************** 1674 1674 + 1675 1675 + The DBRI communicates with the CPU mainly via a circular interrupt 1676 1676 + buffer. When an interrupt is signaled, the CPU walks through the 1677 1677 + buffer and calls dbri_process_one_interrupt() for each interrupt word. 1678 1678 + Complicated interrupts are handled by dedicated functions (which 1679 1679 + appear first in this file). Any pending interrupts can be serviced by 1680 1680 + calling dbri_process_interrupt_buffer(), which works even if the CPU's 1681 1681 + interrupts are disabled. This function is used by dbri_cmdsend() 1682 1682 + to make sure we're synced up with the chip after each command sequence, 1683 1683 + even if we're running cli'ed. 1684 1684 + 1685 1685 + */ 1686 1686 + 1687 1687 + /* xmit_descs() 1688 1688 + * 1689 1689 + * Transmit the current TD's for recording/playing, if needed. 1690 1690 + * For playback, ALSA has filled the DMA memory with new data (we hope). 1691 1691 + */ 1692 1692 + static void xmit_descs(unsigned long data) 1693 1693 + { 1694 1694 + snd_dbri_t *dbri = (snd_dbri_t *) data; 1695 1695 + dbri_streaminfo_t *info; 1696 1696 + volatile s32 *cmd; 1697 1697 + unsigned long flags; 1698 1698 + int first_td; 1699 1699 + 1700 1700 + if (dbri == NULL) 1701 1701 + return; /* Disabled */ 1702 1702 + 1703 1703 + /* First check the recording stream for buffer overflow */ 1704 1704 + info = &dbri->stream_info[DBRI_REC]; 1705 1705 + spin_lock_irqsave(&dbri->lock, flags); 1706 1706 + 1707 1707 + if ((info->left >= info->size) && (info->pipe >= 0)) { 1708 1708 + first_td = dbri->pipes[info->pipe].first_desc; 1709 1709 + 1710 1710 + dprintk(D_DESC, "xmit_descs rec @ TD %d\n", first_td); 1711 1711 + 1712 1712 + /* Stream could be closed by the time we run. */ 1713 1713 + if (first_td < 0) { 1714 1714 + goto play; 1715 1715 + } 1716 1716 + 1717 1717 + cmd = dbri_cmdlock(dbri, NoGetLock); 1718 1718 + *(cmd++) = DBRI_CMD(D_SDP, 0, 1719 1719 + dbri->pipes[info->pipe].sdp 1720 1720 + | D_SDP_P | D_SDP_EVERY | D_SDP_C); 1721 1721 + *(cmd++) = dbri->dma_dvma + dbri_dma_off(desc, first_td); 1722 1722 + dbri_cmdsend(dbri, cmd); 1723 1723 + 1724 1724 + /* Reset our admin of the pipe & bytes read. */ 1725 1725 + dbri->pipes[info->pipe].desc = first_td; 1726 1726 + info->left = 0; 1727 1727 + } 1728 1728 + 1729 1729 + play: 1730 1730 + spin_unlock_irqrestore(&dbri->lock, flags); 1731 1731 + 1732 1732 + /* Now check the playback stream for buffer underflow */ 1733 1733 + info = &dbri->stream_info[DBRI_PLAY]; 1734 1734 + spin_lock_irqsave(&dbri->lock, flags); 1735 1735 + 1736 1736 + if ((info->left <= 0) && (info->pipe >= 0)) { 1737 1737 + first_td = dbri->pipes[info->pipe].first_desc; 1738 1738 + 1739 1739 + dprintk(D_DESC, "xmit_descs play @ TD %d\n", first_td); 1740 1740 + 1741 1741 + /* Stream could be closed by the time we run. */ 1742 1742 + if (first_td < 0) { 1743 1743 + spin_unlock_irqrestore(&dbri->lock, flags); 1744 1744 + return; 1745 1745 + } 1746 1746 + 1747 1747 + cmd = dbri_cmdlock(dbri, NoGetLock); 1748 1748 + *(cmd++) = DBRI_CMD(D_SDP, 0, 1749 1749 + dbri->pipes[info->pipe].sdp 1750 1750 + | D_SDP_P | D_SDP_EVERY | D_SDP_C); 1751 1751 + *(cmd++) = dbri->dma_dvma + dbri_dma_off(desc, first_td); 1752 1752 + dbri_cmdsend(dbri, cmd); 1753 1753 + 1754 1754 + /* Reset our admin of the pipe & bytes written. */ 1755 1755 + dbri->pipes[info->pipe].desc = first_td; 1756 1756 + info->left = info->size; 1757 1757 + } 1758 1758 + spin_unlock_irqrestore(&dbri->lock, flags); 1759 1759 + } 1760 1760 + 1761 1761 + DECLARE_TASKLET(xmit_descs_task, xmit_descs, 0); 1762 1762 + 1763 1763 + /* transmission_complete_intr() 1764 1764 + * 1765 1765 + * Called by main interrupt handler when DBRI signals transmission complete 1766 1766 + * on a pipe (interrupt triggered by the B bit in a transmit descriptor). 1767 1767 + * 1768 1768 + * Walks through the pipe's list of transmit buffer descriptors, releasing 1769 1769 + * each one's DMA buffer (if present), flagging the descriptor available, 1770 1770 + * and signaling its callback routine (if present), before proceeding 1771 1771 + * to the next one. Stops when the first descriptor is found without 1772 1772 + * TBC (Transmit Buffer Complete) set, or we've run through them all. 1773 1773 + */ 1774 1774 + 1775 1775 + static void transmission_complete_intr(snd_dbri_t * dbri, int pipe) 1776 1776 + { 1777 1777 + dbri_streaminfo_t *info; 1778 1778 + int td; 1779 1779 + int status; 1780 1780 + 1781 1781 + info = &dbri->stream_info[DBRI_PLAY]; 1782 1782 + 1783 1783 + td = dbri->pipes[pipe].desc; 1784 1784 + while (td >= 0) { 1785 1785 + if (td >= DBRI_NO_DESCS) { 1786 1786 + printk(KERN_ERR "DBRI: invalid td on pipe %d\n", pipe); 1787 1787 + return; 1788 1788 + } 1789 1789 + 1790 1790 + status = DBRI_TD_STATUS(dbri->dma->desc[td].word4); 1791 1791 + if (!(status & DBRI_TD_TBC)) { 1792 1792 + break; 1793 1793 + } 1794 1794 + 1795 1795 + dprintk(D_INT, "TD %d, status 0x%02x\n", td, status); 1796 1796 + 1797 1797 + dbri->dma->desc[td].word4 = 0; /* Reset it for next time. */ 1798 1798 + info->offset += dbri->descs[td].len; 1799 1799 + info->left -= dbri->descs[td].len; 1800 1800 + 1801 1801 + /* On the last TD, transmit them all again. */ 1802 1802 + if (dbri->descs[td].next == -1) { 1803 1803 + if (info->left > 0) { 1804 1804 + printk(KERN_WARNING 1805 1805 + "%d bytes left after last transfer.\n", 1806 1806 + info->left); 1807 1807 + info->left = 0; 1808 1808 + } 1809 1809 + tasklet_schedule(&xmit_descs_task); 1810 1810 + } 1811 1811 + 1812 1812 + td = dbri->descs[td].next; 1813 1813 + dbri->pipes[pipe].desc = td; 1814 1814 + } 1815 1815 + 1816 1816 + /* Notify ALSA */ 1817 1817 + if (spin_is_locked(&dbri->lock)) { 1818 1818 + spin_unlock(&dbri->lock); 1819 1819 + snd_pcm_period_elapsed(info->substream); 1820 1820 + spin_lock(&dbri->lock); 1821 1821 + } else 1822 1822 + snd_pcm_period_elapsed(info->substream); 1823 1823 + } 1824 1824 + 1825 1825 + static void reception_complete_intr(snd_dbri_t * dbri, int pipe) 1826 1826 + { 1827 1827 + dbri_streaminfo_t *info; 1828 1828 + int rd = dbri->pipes[pipe].desc; 1829 1829 + s32 status; 1830 1830 + 1831 1831 + if (rd < 0 || rd >= DBRI_NO_DESCS) { 1832 1832 + printk(KERN_ERR "DBRI: invalid rd on pipe %d\n", pipe); 1833 1833 + return; 1834 1834 + } 1835 1835 + 1836 1836 + dbri->descs[rd].inuse = 0; 1837 1837 + dbri->pipes[pipe].desc = dbri->descs[rd].next; 1838 1838 + status = dbri->dma->desc[rd].word1; 1839 1839 + dbri->dma->desc[rd].word1 = 0; /* Reset it for next time. */ 1840 1840 + 1841 1841 + info = &dbri->stream_info[DBRI_REC]; 1842 1842 + info->offset += DBRI_RD_CNT(status); 1843 1843 + info->left += DBRI_RD_CNT(status); 1844 1844 + 1845 1845 + /* FIXME: Check status */ 1846 1846 + 1847 1847 + dprintk(D_INT, "Recv RD %d, status 0x%02x, len %d\n", 1848 1848 + rd, DBRI_RD_STATUS(status), DBRI_RD_CNT(status)); 1849 1849 + 1850 1850 + /* On the last TD, transmit them all again. */ 1851 1851 + if (dbri->descs[rd].next == -1) { 1852 1852 + if (info->left > info->size) { 1853 1853 + printk(KERN_WARNING 1854 1854 + "%d bytes recorded in %d size buffer.\n", 1855 1855 + info->left, info->size); 1856 1856 + } 1857 1857 + tasklet_schedule(&xmit_descs_task); 1858 1858 + } 1859 1859 + 1860 1860 + /* Notify ALSA */ 1861 1861 + if (spin_is_locked(&dbri->lock)) { 1862 1862 + spin_unlock(&dbri->lock); 1863 1863 + snd_pcm_period_elapsed(info->substream); 1864 1864 + spin_lock(&dbri->lock); 1865 1865 + } else 1866 1866 + snd_pcm_period_elapsed(info->substream); 1867 1867 + } 1868 1868 + 1869 1869 + static void dbri_process_one_interrupt(snd_dbri_t * dbri, int x) 1870 1870 + { 1871 1871 + int val = D_INTR_GETVAL(x); 1872 1872 + int channel = D_INTR_GETCHAN(x); 1873 1873 + int command = D_INTR_GETCMD(x); 1874 1874 + int code = D_INTR_GETCODE(x); 1875 1875 + #ifdef DBRI_DEBUG 1876 1876 + int rval = D_INTR_GETRVAL(x); 1877 1877 + #endif 1878 1878 + 1879 1879 + if (channel == D_INTR_CMD) { 1880 1880 + dprintk(D_CMD, "INTR: Command: %-5s Value:%d\n", 1881 1881 + cmds[command], val); 1882 1882 + } else { 1883 1883 + dprintk(D_INT, "INTR: Chan:%d Code:%d Val:%#x\n", 1884 1884 + channel, code, rval); 1885 1885 + } 1886 1886 + 1887 1887 + if (channel == D_INTR_CMD && command == D_WAIT) { 1888 1888 + dbri->wait_seen++; 1889 1889 + return; 1890 1890 + } 1891 1891 + 1892 1892 + switch (code) { 1893 1893 + case D_INTR_BRDY: 1894 1894 + reception_complete_intr(dbri, channel); 1895 1895 + break; 1896 1896 + case D_INTR_XCMP: 1897 1897 + case D_INTR_MINT: 1898 1898 + transmission_complete_intr(dbri, channel); 1899 1899 + break; 1900 1900 + case D_INTR_UNDR: 1901 1901 + /* UNDR - Transmission underrun 1902 1902 + * resend SDP command with clear pipe bit (C) set 1903 1903 + */ 1904 1904 + { 1905 1905 + volatile s32 *cmd; 1906 1906 + 1907 1907 + int pipe = channel; 1908 1908 + int td = dbri->pipes[pipe].desc; 1909 1909 + 1910 1910 + dbri->dma->desc[td].word4 = 0; 1911 1911 + cmd = dbri_cmdlock(dbri, NoGetLock); 1912 1912 + *(cmd++) = DBRI_CMD(D_SDP, 0, 1913 1913 + dbri->pipes[pipe].sdp 1914 1914 + | D_SDP_P | D_SDP_C | D_SDP_2SAME); 1915 1915 + *(cmd++) = dbri->dma_dvma + dbri_dma_off(desc, td); 1916 1916 + dbri_cmdsend(dbri, cmd); 1917 1917 + } 1918 1918 + break; 1919 1919 + case D_INTR_FXDT: 1920 1920 + /* FXDT - Fixed data change */ 1921 1921 + if (dbri->pipes[channel].sdp & D_SDP_MSB) 1922 1922 + val = reverse_bytes(val, dbri->pipes[channel].length); 1923 1923 + 1924 1924 + if (dbri->pipes[channel].recv_fixed_ptr) 1925 1925 + *(dbri->pipes[channel].recv_fixed_ptr) = val; 1926 1926 + break; 1927 1927 + default: 1928 1928 + if (channel != D_INTR_CMD) 1929 1929 + printk(KERN_WARNING 1930 1930 + "DBRI: Ignored Interrupt: %d (0x%x)\n", code, x); 1931 1931 + } 1932 1932 + } 1933 1933 + 1934 1934 + /* dbri_process_interrupt_buffer advances through the DBRI's interrupt 1935 1935 + * buffer until it finds a zero word (indicating nothing more to do 1936 1936 + * right now). Non-zero words require processing and are handed off 1937 1937 + * to dbri_process_one_interrupt AFTER advancing the pointer. This 1938 1938 + * order is important since we might recurse back into this function 1939 1939 + * and need to make sure the pointer has been advanced first. 1940 1940 + */ 1941 1941 + static void dbri_process_interrupt_buffer(snd_dbri_t * dbri) 1942 1942 + { 1943 1943 + s32 x; 1944 1944 + 1945 1945 + while ((x = dbri->dma->intr[dbri->dbri_irqp]) != 0) { 1946 1946 + dbri->dma->intr[dbri->dbri_irqp] = 0; 1947 1947 + dbri->dbri_irqp++; 1948 1948 + if (dbri->dbri_irqp == (DBRI_NO_INTS * DBRI_INT_BLK)) 1949 1949 + dbri->dbri_irqp = 1; 1950 1950 + else if ((dbri->dbri_irqp & (DBRI_INT_BLK - 1)) == 0) 1951 1951 + dbri->dbri_irqp++; 1952 1952 + 1953 1953 + dbri_process_one_interrupt(dbri, x); 1954 1954 + } 1955 1955 + } 1956 1956 + 1957 1957 + static irqreturn_t snd_dbri_interrupt(int irq, void *dev_id, 1958 1958 + struct pt_regs *regs) 1959 1959 + { 1960 1960 + snd_dbri_t *dbri = dev_id; 1961 1961 + static int errcnt = 0; 1962 1962 + int x; 1963 1963 + 1964 1964 + if (dbri == NULL) 1965 1965 + return IRQ_NONE; 1966 1966 + spin_lock(&dbri->lock); 1967 1967 + 1968 1968 + /* 1969 1969 + * Read it, so the interrupt goes away. 1970 1970 + */ 1971 1971 + x = sbus_readl(dbri->regs + REG1); 1972 1972 + 1973 1973 + if (x & (D_MRR | D_MLE | D_LBG | D_MBE)) { 1974 1974 + u32 tmp; 1975 1975 + 1976 1976 + if (x & D_MRR) 1977 1977 + printk(KERN_ERR 1978 1978 + "DBRI: Multiple Error Ack on SBus reg1=0x%x\n", 1979 1979 + x); 1980 1980 + if (x & D_MLE) 1981 1981 + printk(KERN_ERR 1982 1982 + "DBRI: Multiple Late Error on SBus reg1=0x%x\n", 1983 1983 + x); 1984 1984 + if (x & D_LBG) 1985 1985 + printk(KERN_ERR 1986 1986 + "DBRI: Lost Bus Grant on SBus reg1=0x%x\n", x); 1987 1987 + if (x & D_MBE) 1988 1988 + printk(KERN_ERR 1989 1989 + "DBRI: Burst Error on SBus reg1=0x%x\n", x); 1990 1990 + 1991 1991 + /* Some of these SBus errors cause the chip's SBus circuitry 1992 1992 + * to be disabled, so just re-enable and try to keep going. 1993 1993 + * 1994 1994 + * The only one I've seen is MRR, which will be triggered 1995 1995 + * if you let a transmit pipe underrun, then try to CDP it. 1996 1996 + * 1997 1997 + * If these things persist, we should probably reset 1998 1998 + * and re-init the chip. 1999 1999 + */ 2000 2000 + if ((++errcnt) % 10 == 0) { 2001 2001 + dprintk(D_INT, "Interrupt errors exceeded.\n"); 2002 2002 + dbri_reset(dbri); 2003 2003 + } else { 2004 2004 + tmp = sbus_readl(dbri->regs + REG0); 2005 2005 + tmp &= ~(D_D); 2006 2006 + sbus_writel(tmp, dbri->regs + REG0); 2007 2007 + } 2008 2008 + } 2009 2009 + 2010 2010 + dbri_process_interrupt_buffer(dbri); 2011 2011 + 2012 2012 + /* FIXME: Write 0 into regs to ACK interrupt */ 2013 2013 + 2014 2014 + spin_unlock(&dbri->lock); 2015 2015 + 2016 2016 + return IRQ_HANDLED; 2017 2017 + } 2018 2018 + 2019 2019 + /**************************************************************************** 2020 2020 + PCM Interface 2021 2021 + ****************************************************************************/ 2022 2022 + static snd_pcm_hardware_t snd_dbri_pcm_hw = { 2023 2023 + .info = (SNDRV_PCM_INFO_MMAP | 2024 2024 + SNDRV_PCM_INFO_INTERLEAVED | 2025 2025 + SNDRV_PCM_INFO_BLOCK_TRANSFER | 2026 2026 + SNDRV_PCM_INFO_MMAP_VALID), 2027 2027 + .formats = SNDRV_PCM_FMTBIT_MU_LAW | 2028 2028 + SNDRV_PCM_FMTBIT_A_LAW | 2029 2029 + SNDRV_PCM_FMTBIT_U8 | 2030 2030 + SNDRV_PCM_FMTBIT_S16_BE, 2031 2031 + .rates = SNDRV_PCM_RATE_8000_48000, 2032 2032 + .rate_min = 8000, 2033 2033 + .rate_max = 48000, 2034 2034 + .channels_min = 1, 2035 2035 + .channels_max = 2, 2036 2036 + .buffer_bytes_max = (64 * 1024), 2037 2037 + .period_bytes_min = 1, 2038 2038 + .period_bytes_max = DBRI_TD_MAXCNT, 2039 2039 + .periods_min = 1, 2040 2040 + .periods_max = 1024, 2041 2041 + }; 2042 2042 + 2043 2043 + static int snd_dbri_open(snd_pcm_substream_t * substream) 2044 2044 + { 2045 2045 + snd_dbri_t *dbri = snd_pcm_substream_chip(substream); 2046 2046 + snd_pcm_runtime_t *runtime = substream->runtime; 2047 2047 + dbri_streaminfo_t *info = DBRI_STREAM(dbri, substream); 2048 2048 + unsigned long flags; 2049 2049 + 2050 2050 + dprintk(D_USR, "open audio output.\n"); 2051 2051 + runtime->hw = snd_dbri_pcm_hw; 2052 2052 + 2053 2053 + spin_lock_irqsave(&dbri->lock, flags); 2054 2054 + info->substream = substream; 2055 2055 + info->left = 0; 2056 2056 + info->offset = 0; 2057 2057 + info->dvma_buffer = 0; 2058 2058 + info->pipe = -1; 2059 2059 + spin_unlock_irqrestore(&dbri->lock, flags); 2060 2060 + 2061 2061 + cs4215_open(dbri); 2062 2062 + 2063 2063 + return 0; 2064 2064 + } 2065 2065 + 2066 2066 + static int snd_dbri_close(snd_pcm_substream_t * substream) 2067 2067 + { 2068 2068 + snd_dbri_t *dbri = snd_pcm_substream_chip(substream); 2069 2069 + dbri_streaminfo_t *info = DBRI_STREAM(dbri, substream); 2070 2070 + 2071 2071 + dprintk(D_USR, "close audio output.\n"); 2072 2072 + info->substream = NULL; 2073 2073 + info->left = 0; 2074 2074 + info->offset = 0; 2075 2075 + 2076 2076 + return 0; 2077 2077 + } 2078 2078 + 2079 2079 + static int snd_dbri_hw_params(snd_pcm_substream_t * substream, 2080 2080 + snd_pcm_hw_params_t * hw_params) 2081 2081 + { 2082 2082 + snd_pcm_runtime_t *runtime = substream->runtime; 2083 2083 + snd_dbri_t *dbri = snd_pcm_substream_chip(substream); 2084 2084 + dbri_streaminfo_t *info = DBRI_STREAM(dbri, substream); 2085 2085 + int direction; 2086 2086 + int ret; 2087 2087 + 2088 2088 + /* set sampling rate, audio format and number of channels */ 2089 2089 + ret = cs4215_prepare(dbri, params_rate(hw_params), 2090 2090 + params_format(hw_params), 2091 2091 + params_channels(hw_params)); 2092 2092 + if (ret != 0) 2093 2093 + return ret; 2094 2094 + 2095 2095 + if ((ret = snd_pcm_lib_malloc_pages(substream, 2096 2096 + params_buffer_bytes(hw_params))) < 0) { 2097 2097 + snd_printk(KERN_ERR "malloc_pages failed with %d\n", ret); 2098 2098 + return ret; 2099 2099 + } 2100 2100 + 2101 2101 + /* hw_params can get called multiple times. Only map the DMA once. 2102 2102 + */ 2103 2103 + if (info->dvma_buffer == 0) { 2104 2104 + if (DBRI_STREAMNO(substream) == DBRI_PLAY) 2105 2105 + direction = SBUS_DMA_TODEVICE; 2106 2106 + else 2107 2107 + direction = SBUS_DMA_FROMDEVICE; 2108 2108 + 2109 2109 + info->dvma_buffer = sbus_map_single(dbri->sdev, 2110 2110 + runtime->dma_area, 2111 2111 + params_buffer_bytes(hw_params), 2112 2112 + direction); 2113 2113 + } 2114 2114 + 2115 2115 + direction = params_buffer_bytes(hw_params); 2116 2116 + dprintk(D_USR, "hw_params: %d bytes, dvma=%x\n", 2117 2117 + direction, info->dvma_buffer); 2118 2118 + return 0; 2119 2119 + } 2120 2120 + 2121 2121 + static int snd_dbri_hw_free(snd_pcm_substream_t * substream) 2122 2122 + { 2123 2123 + snd_dbri_t *dbri = snd_pcm_substream_chip(substream); 2124 2124 + dbri_streaminfo_t *info = DBRI_STREAM(dbri, substream); 2125 2125 + int direction; 2126 2126 + dprintk(D_USR, "hw_free.\n"); 2127 2127 + 2128 2128 + /* hw_free can get called multiple times. Only unmap the DMA once. 2129 2129 + */ 2130 2130 + if (info->dvma_buffer) { 2131 2131 + if (DBRI_STREAMNO(substream) == DBRI_PLAY) 2132 2132 + direction = SBUS_DMA_TODEVICE; 2133 2133 + else 2134 2134 + direction = SBUS_DMA_FROMDEVICE; 2135 2135 + 2136 2136 + sbus_unmap_single(dbri->sdev, info->dvma_buffer, 2137 2137 + substream->runtime->buffer_size, direction); 2138 2138 + info->dvma_buffer = 0; 2139 2139 + } 2140 2140 + info->pipe = -1; 2141 2141 + 2142 2142 + return snd_pcm_lib_free_pages(substream); 2143 2143 + } 2144 2144 + 2145 2145 + static int snd_dbri_prepare(snd_pcm_substream_t * substream) 2146 2146 + { 2147 2147 + snd_dbri_t *dbri = snd_pcm_substream_chip(substream); 2148 2148 + dbri_streaminfo_t *info = DBRI_STREAM(dbri, substream); 2149 2149 + snd_pcm_runtime_t *runtime = substream->runtime; 2150 2150 + int ret; 2151 2151 + 2152 2152 + info->size = snd_pcm_lib_buffer_bytes(substream); 2153 2153 + if (DBRI_STREAMNO(substream) == DBRI_PLAY) 2154 2154 + info->pipe = 4; /* Send pipe */ 2155 2155 + else { 2156 2156 + info->pipe = 6; /* Receive pipe */ 2157 2157 + info->left = info->size; /* To trigger submittal */ 2158 2158 + } 2159 2159 + 2160 2160 + spin_lock_irq(&dbri->lock); 2161 2161 + 2162 2162 + /* Setup the all the transmit/receive desciptors to cover the 2163 2163 + * whole DMA buffer. 2164 2164 + */ 2165 2165 + ret = setup_descs(dbri, DBRI_STREAMNO(substream), 2166 2166 + snd_pcm_lib_period_bytes(substream)); 2167 2167 + 2168 2168 + runtime->stop_threshold = DBRI_TD_MAXCNT / runtime->channels; 2169 2169 + 2170 2170 + spin_unlock_irq(&dbri->lock); 2171 2171 + 2172 2172 + dprintk(D_USR, "prepare audio output. %d bytes\n", info->size); 2173 2173 + return ret; 2174 2174 + } 2175 2175 + 2176 2176 + static int snd_dbri_trigger(snd_pcm_substream_t * substream, int cmd) 2177 2177 + { 2178 2178 + snd_dbri_t *dbri = snd_pcm_substream_chip(substream); 2179 2179 + dbri_streaminfo_t *info = DBRI_STREAM(dbri, substream); 2180 2180 + int ret = 0; 2181 2181 + 2182 2182 + switch (cmd) { 2183 2183 + case SNDRV_PCM_TRIGGER_START: 2184 2184 + dprintk(D_USR, "start audio, period is %d bytes\n", 2185 2185 + (int)snd_pcm_lib_period_bytes(substream)); 2186 2186 + /* Enable & schedule the tasklet that re-submits the TDs. */ 2187 2187 + xmit_descs_task.data = (unsigned long)dbri; 2188 2188 + tasklet_schedule(&xmit_descs_task); 2189 2189 + break; 2190 2190 + case SNDRV_PCM_TRIGGER_STOP: 2191 2191 + dprintk(D_USR, "stop audio.\n"); 2192 2192 + /* Make the tasklet bail out immediately. */ 2193 2193 + xmit_descs_task.data = 0; 2194 2194 + reset_pipe(dbri, info->pipe); 2195 2195 + break; 2196 2196 + default: 2197 2197 + ret = -EINVAL; 2198 2198 + } 2199 2199 + 2200 2200 + return ret; 2201 2201 + } 2202 2202 + 2203 2203 + static snd_pcm_uframes_t snd_dbri_pointer(snd_pcm_substream_t * substream) 2204 2204 + { 2205 2205 + snd_dbri_t *dbri = snd_pcm_substream_chip(substream); 2206 2206 + dbri_streaminfo_t *info = DBRI_STREAM(dbri, substream); 2207 2207 + snd_pcm_uframes_t ret; 2208 2208 + 2209 2209 + ret = bytes_to_frames(substream->runtime, info->offset) 2210 2210 + % substream->runtime->buffer_size; 2211 2211 + dprintk(D_USR, "I/O pointer: %ld frames, %d bytes left.\n", 2212 2212 + ret, info->left); 2213 2213 + return ret; 2214 2214 + } 2215 2215 + 2216 2216 + static snd_pcm_ops_t snd_dbri_ops = { 2217 2217 + .open = snd_dbri_open, 2218 2218 + .close = snd_dbri_close, 2219 2219 + .ioctl = snd_pcm_lib_ioctl, 2220 2220 + .hw_params = snd_dbri_hw_params, 2221 2221 + .hw_free = snd_dbri_hw_free, 2222 2222 + .prepare = snd_dbri_prepare, 2223 2223 + .trigger = snd_dbri_trigger, 2224 2224 + .pointer = snd_dbri_pointer, 2225 2225 + }; 2226 2226 + 2227 2227 + static int __devinit snd_dbri_pcm(snd_dbri_t * dbri) 2228 2228 + { 2229 2229 + snd_pcm_t *pcm; 2230 2230 + int err; 2231 2231 + 2232 2232 + if ((err = snd_pcm_new(dbri->card, 2233 2233 + /* ID */ "sun_dbri", 2234 2234 + /* device */ 0, 2235 2235 + /* playback count */ 1, 2236 2236 + /* capture count */ 1, &pcm)) < 0) 2237 2237 + return err; 2238 2238 + snd_assert(pcm != NULL, return -EINVAL); 2239 2239 + 2240 2240 + snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_dbri_ops); 2241 2241 + snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_dbri_ops); 2242 2242 + 2243 2243 + pcm->private_data = dbri; 2244 2244 + pcm->info_flags = 0; 2245 2245 + strcpy(pcm->name, dbri->card->shortname); 2246 2246 + dbri->pcm = pcm; 2247 2247 + 2248 2248 + if ((err = snd_pcm_lib_preallocate_pages_for_all(pcm, 2249 2249 + SNDRV_DMA_TYPE_CONTINUOUS, 2250 2250 + snd_dma_continuous_data(GFP_KERNEL), 2251 2251 + 64 * 1024, 64 * 1024)) < 0) { 2252 2252 + return err; 2253 2253 + } 2254 2254 + 2255 2255 + return 0; 2256 2256 + } 2257 2257 + 2258 2258 + /***************************************************************************** 2259 2259 + Mixer interface 2260 2260 + *****************************************************************************/ 2261 2261 + 2262 2262 + static int snd_cs4215_info_volume(snd_kcontrol_t * kcontrol, 2263 2263 + snd_ctl_elem_info_t * uinfo) 2264 2264 + { 2265 2265 + uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 2266 2266 + uinfo->count = 2; 2267 2267 + uinfo->value.integer.min = 0; 2268 2268 + if (kcontrol->private_value == DBRI_PLAY) { 2269 2269 + uinfo->value.integer.max = DBRI_MAX_VOLUME; 2270 2270 + } else { 2271 2271 + uinfo->value.integer.max = DBRI_MAX_GAIN; 2272 2272 + } 2273 2273 + return 0; 2274 2274 + } 2275 2275 + 2276 2276 + static int snd_cs4215_get_volume(snd_kcontrol_t * kcontrol, 2277 2277 + snd_ctl_elem_value_t * ucontrol) 2278 2278 + { 2279 2279 + snd_dbri_t *dbri = snd_kcontrol_chip(kcontrol); 2280 2280 + dbri_streaminfo_t *info; 2281 2281 + snd_assert(dbri != NULL, return -EINVAL); 2282 2282 + info = &dbri->stream_info[kcontrol->private_value]; 2283 2283 + snd_assert(info != NULL, return -EINVAL); 2284 2284 + 2285 2285 + ucontrol->value.integer.value[0] = info->left_gain; 2286 2286 + ucontrol->value.integer.value[1] = info->right_gain; 2287 2287 + return 0; 2288 2288 + } 2289 2289 + 2290 2290 + static int snd_cs4215_put_volume(snd_kcontrol_t * kcontrol, 2291 2291 + snd_ctl_elem_value_t * ucontrol) 2292 2292 + { 2293 2293 + snd_dbri_t *dbri = snd_kcontrol_chip(kcontrol); 2294 2294 + dbri_streaminfo_t *info = &dbri->stream_info[kcontrol->private_value]; 2295 2295 + unsigned long flags; 2296 2296 + int changed = 0; 2297 2297 + 2298 2298 + if (info->left_gain != ucontrol->value.integer.value[0]) { 2299 2299 + info->left_gain = ucontrol->value.integer.value[0]; 2300 2300 + changed = 1; 2301 2301 + } 2302 2302 + if (info->right_gain != ucontrol->value.integer.value[1]) { 2303 2303 + info->right_gain = ucontrol->value.integer.value[1]; 2304 2304 + changed = 1; 2305 2305 + } 2306 2306 + if (changed == 1) { 2307 2307 + /* First mute outputs, and wait 1/8000 sec (125 us) 2308 2308 + * to make sure this takes. This avoids clicking noises. 2309 2309 + */ 2310 2310 + spin_lock_irqsave(&dbri->lock, flags); 2311 2311 + 2312 2312 + cs4215_setdata(dbri, 1); 2313 2313 + udelay(125); 2314 2314 + cs4215_setdata(dbri, 0); 2315 2315 + 2316 2316 + spin_unlock_irqrestore(&dbri->lock, flags); 2317 2317 + } 2318 2318 + return changed; 2319 2319 + } 2320 2320 + 2321 2321 + static int snd_cs4215_info_single(snd_kcontrol_t * kcontrol, 2322 2322 + snd_ctl_elem_info_t * uinfo) 2323 2323 + { 2324 2324 + int mask = (kcontrol->private_value >> 16) & 0xff; 2325 2325 + 2326 2326 + uinfo->type = (mask == 1) ? 2327 2327 + SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER; 2328 2328 + uinfo->count = 1; 2329 2329 + uinfo->value.integer.min = 0; 2330 2330 + uinfo->value.integer.max = mask; 2331 2331 + return 0; 2332 2332 + } 2333 2333 + 2334 2334 + static int snd_cs4215_get_single(snd_kcontrol_t * kcontrol, 2335 2335 + snd_ctl_elem_value_t * ucontrol) 2336 2336 + { 2337 2337 + snd_dbri_t *dbri = snd_kcontrol_chip(kcontrol); 2338 2338 + int elem = kcontrol->private_value & 0xff; 2339 2339 + int shift = (kcontrol->private_value >> 8) & 0xff; 2340 2340 + int mask = (kcontrol->private_value >> 16) & 0xff; 2341 2341 + int invert = (kcontrol->private_value >> 24) & 1; 2342 2342 + snd_assert(dbri != NULL, return -EINVAL); 2343 2343 + 2344 2344 + if (elem < 4) { 2345 2345 + ucontrol->value.integer.value[0] = 2346 2346 + (dbri->mm.data[elem] >> shift) & mask; 2347 2347 + } else { 2348 2348 + ucontrol->value.integer.value[0] = 2349 2349 + (dbri->mm.ctrl[elem - 4] >> shift) & mask; 2350 2350 + } 2351 2351 + 2352 2352 + if (invert == 1) { 2353 2353 + ucontrol->value.integer.value[0] = 2354 2354 + mask - ucontrol->value.integer.value[0]; 2355 2355 + } 2356 2356 + return 0; 2357 2357 + } 2358 2358 + 2359 2359 + static int snd_cs4215_put_single(snd_kcontrol_t * kcontrol, 2360 2360 + snd_ctl_elem_value_t * ucontrol) 2361 2361 + { 2362 2362 + snd_dbri_t *dbri = snd_kcontrol_chip(kcontrol); 2363 2363 + unsigned long flags; 2364 2364 + int elem = kcontrol->private_value & 0xff; 2365 2365 + int shift = (kcontrol->private_value >> 8) & 0xff; 2366 2366 + int mask = (kcontrol->private_value >> 16) & 0xff; 2367 2367 + int invert = (kcontrol->private_value >> 24) & 1; 2368 2368 + int changed = 0; 2369 2369 + unsigned short val; 2370 2370 + snd_assert(dbri != NULL, return -EINVAL); 2371 2371 + 2372 2372 + val = (ucontrol->value.integer.value[0] & mask); 2373 2373 + if (invert == 1) 2374 2374 + val = mask - val; 2375 2375 + val <<= shift; 2376 2376 + 2377 2377 + if (elem < 4) { 2378 2378 + dbri->mm.data[elem] = (dbri->mm.data[elem] & 2379 2379 + ~(mask << shift)) | val; 2380 2380 + changed = (val != dbri->mm.data[elem]); 2381 2381 + } else { 2382 2382 + dbri->mm.ctrl[elem - 4] = (dbri->mm.ctrl[elem - 4] & 2383 2383 + ~(mask << shift)) | val; 2384 2384 + changed = (val != dbri->mm.ctrl[elem - 4]); 2385 2385 + } 2386 2386 + 2387 2387 + dprintk(D_GEN, "put_single: mask=0x%x, changed=%d, " 2388 2388 + "mixer-value=%ld, mm-value=0x%x\n", 2389 2389 + mask, changed, ucontrol->value.integer.value[0], 2390 2390 + dbri->mm.data[elem & 3]); 2391 2391 + 2392 2392 + if (changed) { 2393 2393 + /* First mute outputs, and wait 1/8000 sec (125 us) 2394 2394 + * to make sure this takes. This avoids clicking noises. 2395 2395 + */ 2396 2396 + spin_lock_irqsave(&dbri->lock, flags); 2397 2397 + 2398 2398 + cs4215_setdata(dbri, 1); 2399 2399 + udelay(125); 2400 2400 + cs4215_setdata(dbri, 0); 2401 2401 + 2402 2402 + spin_unlock_irqrestore(&dbri->lock, flags); 2403 2403 + } 2404 2404 + return changed; 2405 2405 + } 2406 2406 + 2407 2407 + /* Entries 0-3 map to the 4 data timeslots, entries 4-7 map to the 4 control 2408 2408 + timeslots. Shift is the bit offset in the timeslot, mask defines the 2409 2409 + number of bits. invert is a boolean for use with attenuation. 2410 2410 + */ 2411 2411 + #define CS4215_SINGLE(xname, entry, shift, mask, invert) \ 2412 2412 + { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 2413 2413 + .info = snd_cs4215_info_single, \ 2414 2414 + .get = snd_cs4215_get_single, .put = snd_cs4215_put_single, \ 2415 2415 + .private_value = entry | (shift << 8) | (mask << 16) | (invert << 24) }, 2416 2416 + 2417 2417 + static snd_kcontrol_new_t dbri_controls[] __devinitdata = { 2418 2418 + { 2419 2419 + .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 2420 2420 + .name = "Playback Volume", 2421 2421 + .info = snd_cs4215_info_volume, 2422 2422 + .get = snd_cs4215_get_volume, 2423 2423 + .put = snd_cs4215_put_volume, 2424 2424 + .private_value = DBRI_PLAY, 2425 2425 + }, 2426 2426 + CS4215_SINGLE("Headphone switch", 0, 7, 1, 0) 2427 2427 + CS4215_SINGLE("Line out switch", 0, 6, 1, 0) 2428 2428 + CS4215_SINGLE("Speaker switch", 1, 6, 1, 0) 2429 2429 + { 2430 2430 + .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 2431 2431 + .name = "Capture Volume", 2432 2432 + .info = snd_cs4215_info_volume, 2433 2433 + .get = snd_cs4215_get_volume, 2434 2434 + .put = snd_cs4215_put_volume, 2435 2435 + .private_value = DBRI_REC, 2436 2436 + }, 2437 2437 + /* FIXME: mic/line switch */ 2438 2438 + CS4215_SINGLE("Line in switch", 2, 4, 1, 0) 2439 2439 + CS4215_SINGLE("High Pass Filter switch", 5, 7, 1, 0) 2440 2440 + CS4215_SINGLE("Monitor Volume", 3, 4, 0xf, 1) 2441 2441 + CS4215_SINGLE("Mic boost", 4, 4, 1, 1) 2442 2442 + }; 2443 2443 + 2444 2444 + #define NUM_CS4215_CONTROLS (sizeof(dbri_controls)/sizeof(snd_kcontrol_new_t)) 2445 2445 + 2446 2446 + static int __init snd_dbri_mixer(snd_dbri_t * dbri) 2447 2447 + { 2448 2448 + snd_card_t *card; 2449 2449 + int idx, err; 2450 2450 + 2451 2451 + snd_assert(dbri != NULL && dbri->card != NULL, return -EINVAL); 2452 2452 + 2453 2453 + card = dbri->card; 2454 2454 + strcpy(card->mixername, card->shortname); 2455 2455 + 2456 2456 + for (idx = 0; idx < NUM_CS4215_CONTROLS; idx++) { 2457 2457 + if ((err = snd_ctl_add(card, 2458 2458 + snd_ctl_new1(&dbri_controls[idx], 2459 2459 + dbri))) < 0) 2460 2460 + return err; 2461 2461 + } 2462 2462 + 2463 2463 + for (idx = DBRI_REC; idx < DBRI_NO_STREAMS; idx++) { 2464 2464 + dbri->stream_info[idx].left_gain = 0; 2465 2465 + dbri->stream_info[idx].right_gain = 0; 2466 2466 + dbri->stream_info[idx].balance = DBRI_MID_BALANCE; 2467 2467 + } 2468 2468 + 2469 2469 + return 0; 2470 2470 + } 2471 2471 + 2472 2472 + /**************************************************************************** 2473 2473 + /proc interface 2474 2474 + ****************************************************************************/ 2475 2475 + static void dbri_regs_read(snd_info_entry_t * entry, snd_info_buffer_t * buffer) 2476 2476 + { 2477 2477 + snd_dbri_t *dbri = entry->private_data; 2478 2478 + 2479 2479 + snd_iprintf(buffer, "REG0: 0x%x\n", sbus_readl(dbri->regs + REG0)); 2480 2480 + snd_iprintf(buffer, "REG2: 0x%x\n", sbus_readl(dbri->regs + REG2)); 2481 2481 + snd_iprintf(buffer, "REG8: 0x%x\n", sbus_readl(dbri->regs + REG8)); 2482 2482 + snd_iprintf(buffer, "REG9: 0x%x\n", sbus_readl(dbri->regs + REG9)); 2483 2483 + } 2484 2484 + 2485 2485 + #ifdef DBRI_DEBUG 2486 2486 + static void dbri_debug_read(snd_info_entry_t * entry, 2487 2487 + snd_info_buffer_t * buffer) 2488 2488 + { 2489 2489 + snd_dbri_t *dbri = entry->private_data; 2490 2490 + int pipe; 2491 2491 + snd_iprintf(buffer, "debug=%d\n", dbri_debug); 2492 2492 + 2493 2493 + snd_iprintf(buffer, "CHI pipe in=%d, out=%d\n", 2494 2494 + dbri->chi_in_pipe, dbri->chi_out_pipe); 2495 2495 + for (pipe = 0; pipe < 32; pipe++) { 2496 2496 + if (pipe_active(dbri, pipe)) { 2497 2497 + struct dbri_pipe *pptr = &dbri->pipes[pipe]; 2498 2498 + snd_iprintf(buffer, 2499 2499 + "Pipe %d: %s SDP=0x%x desc=%d, " 2500 2500 + "len=%d @ %d prev: %d next %d\n", 2501 2501 + pipe, 2502 2502 + (pptr->direction == 2503 2503 + PIPEinput ? "input" : "output"), pptr->sdp, 2504 2504 + pptr->desc, pptr->length, pptr->cycle, 2505 2505 + pptr->prevpipe, pptr->nextpipe); 2506 2506 + } 2507 2507 + } 2508 2508 + } 2509 2509 + 2510 2510 + static void dbri_debug_write(snd_info_entry_t * entry, 2511 2511 + snd_info_buffer_t * buffer) 2512 2512 + { 2513 2513 + char line[80]; 2514 2514 + int i; 2515 2515 + 2516 2516 + if (snd_info_get_line(buffer, line, 80) == 0) { 2517 2517 + sscanf(line, "%d\n", &i); 2518 2518 + dbri_debug = i & 0x3f; 2519 2519 + } 2520 2520 + } 2521 2521 + #endif 2522 2522 + 2523 2523 + void snd_dbri_proc(snd_dbri_t * dbri) 2524 2524 + { 2525 2525 + snd_info_entry_t *entry; 2526 2526 + int err; 2527 2527 + 2528 2528 + err = snd_card_proc_new(dbri->card, "regs", &entry); 2529 2529 + snd_info_set_text_ops(entry, dbri, 1024, dbri_regs_read); 2530 2530 + 2531 2531 + #ifdef DBRI_DEBUG 2532 2532 + err = snd_card_proc_new(dbri->card, "debug", &entry); 2533 2533 + snd_info_set_text_ops(entry, dbri, 4096, dbri_debug_read); 2534 2534 + entry->mode = S_IFREG | S_IRUGO | S_IWUSR; /* Writable for root */ 2535 2535 + entry->c.text.write_size = 256; 2536 2536 + entry->c.text.write = dbri_debug_write; 2537 2537 + #endif 2538 2538 + } 2539 2539 + 2540 2540 + /* 2541 2541 + **************************************************************************** 2542 2542 + **************************** Initialization ******************************** 2543 2543 + **************************************************************************** 2544 2544 + */ 2545 2545 + static void snd_dbri_free(snd_dbri_t * dbri); 2546 2546 + 2547 2547 + static int __init snd_dbri_create(snd_card_t * card, 2548 2548 + struct sbus_dev *sdev, 2549 2549 + struct linux_prom_irqs *irq, int dev) 2550 2550 + { 2551 2551 + snd_dbri_t *dbri = card->private_data; 2552 2552 + int err; 2553 2553 + 2554 2554 + spin_lock_init(&dbri->lock); 2555 2555 + dbri->card = card; 2556 2556 + dbri->sdev = sdev; 2557 2557 + dbri->irq = irq->pri; 2558 2558 + dbri->dbri_version = sdev->prom_name[9]; 2559 2559 + 2560 2560 + dbri->dma = sbus_alloc_consistent(sdev, sizeof(struct dbri_dma), 2561 2561 + &dbri->dma_dvma); 2562 2562 + memset((void *)dbri->dma, 0, sizeof(struct dbri_dma)); 2563 2563 + 2564 2564 + dprintk(D_GEN, "DMA Cmd Block 0x%p (0x%08x)\n", 2565 2565 + dbri->dma, dbri->dma_dvma); 2566 2566 + 2567 2567 + /* Map the registers into memory. */ 2568 2568 + dbri->regs_size = sdev->reg_addrs[0].reg_size; 2569 2569 + dbri->regs = sbus_ioremap(&sdev->resource[0], 0, 2570 2570 + dbri->regs_size, "DBRI Registers"); 2571 2571 + if (!dbri->regs) { 2572 2572 + printk(KERN_ERR "DBRI: could not allocate registers\n"); 2573 2573 + sbus_free_consistent(sdev, sizeof(struct dbri_dma), 2574 2574 + (void *)dbri->dma, dbri->dma_dvma); 2575 2575 + return -EIO; 2576 2576 + } 2577 2577 + 2578 2578 + err = request_irq(dbri->irq, snd_dbri_interrupt, SA_SHIRQ, 2579 2579 + "DBRI audio", dbri); 2580 2580 + if (err) { 2581 2581 + printk(KERN_ERR "DBRI: Can't get irq %d\n", dbri->irq); 2582 2582 + sbus_iounmap(dbri->regs, dbri->regs_size); 2583 2583 + sbus_free_consistent(sdev, sizeof(struct dbri_dma), 2584 2584 + (void *)dbri->dma, dbri->dma_dvma); 2585 2585 + return err; 2586 2586 + } 2587 2587 + 2588 2588 + /* Do low level initialization of the DBRI and CS4215 chips */ 2589 2589 + dbri_initialize(dbri); 2590 2590 + err = cs4215_init(dbri); 2591 2591 + if (err) { 2592 2592 + snd_dbri_free(dbri); 2593 2593 + return err; 2594 2594 + } 2595 2595 + 2596 2596 + dbri->next = dbri_list; 2597 2597 + dbri_list = dbri; 2598 2598 + 2599 2599 + return 0; 2600 2600 + } 2601 2601 + 2602 2602 + static void snd_dbri_free(snd_dbri_t * dbri) 2603 2603 + { 2604 2604 + dprintk(D_GEN, "snd_dbri_free\n"); 2605 2605 + dbri_reset(dbri); 2606 2606 + 2607 2607 + if (dbri->irq) 2608 2608 + free_irq(dbri->irq, dbri); 2609 2609 + 2610 2610 + if (dbri->regs) 2611 2611 + sbus_iounmap(dbri->regs, dbri->regs_size); 2612 2612 + 2613 2613 + if (dbri->dma) 2614 2614 + sbus_free_consistent(dbri->sdev, sizeof(struct dbri_dma), 2615 2615 + (void *)dbri->dma, dbri->dma_dvma); 2616 2616 + } 2617 2617 + 2618 2618 + static int __init dbri_attach(int prom_node, struct sbus_dev *sdev) 2619 2619 + { 2620 2620 + snd_dbri_t *dbri; 2621 2621 + struct linux_prom_irqs irq; 2622 2622 + struct resource *rp; 2623 2623 + snd_card_t *card; 2624 2624 + static int dev = 0; 2625 2625 + int err; 2626 2626 + 2627 2627 + if (sdev->prom_name[9] < 'e') { 2628 2628 + printk(KERN_ERR "DBRI: unsupported chip version %c found.\n", 2629 2629 + sdev->prom_name[9]); 2630 2630 + return -EIO; 2631 2631 + } 2632 2632 + 2633 2633 + if (dev >= SNDRV_CARDS) 2634 2634 + return -ENODEV; 2635 2635 + if (!enable[dev]) { 2636 2636 + dev++; 2637 2637 + return -ENOENT; 2638 2638 + } 2639 2639 + 2640 2640 + prom_getproperty(prom_node, "intr", (char *)&irq, sizeof(irq)); 2641 2641 + 2642 2642 + card = snd_card_new(index[dev], id[dev], THIS_MODULE, 2643 2643 + sizeof(snd_dbri_t)); 2644 2644 + if (card == NULL) 2645 2645 + return -ENOMEM; 2646 2646 + 2647 2647 + strcpy(card->driver, "DBRI"); 2648 2648 + strcpy(card->shortname, "Sun DBRI"); 2649 2649 + rp = &sdev->resource[0]; 2650 2650 + sprintf(card->longname, "%s at 0x%02lx:0x%08lx, irq %s", 2651 2651 + card->shortname, 2652 2652 + rp->flags & 0xffL, rp->start, __irq_itoa(irq.pri)); 2653 2653 + 2654 2654 + if ((err = snd_dbri_create(card, sdev, &irq, dev)) < 0) { 2655 2655 + snd_card_free(card); 2656 2656 + return err; 2657 2657 + } 2658 2658 + 2659 2659 + dbri = (snd_dbri_t *) card->private_data; 2660 2660 + if ((err = snd_dbri_pcm(dbri)) < 0) { 2661 2661 + snd_dbri_free(dbri); 2662 2662 + snd_card_free(card); 2663 2663 + return err; 2664 2664 + } 2665 2665 + 2666 2666 + if ((err = snd_dbri_mixer(dbri)) < 0) { 2667 2667 + snd_dbri_free(dbri); 2668 2668 + snd_card_free(card); 2669 2669 + return err; 2670 2670 + } 2671 2671 + 2672 2672 + /* /proc file handling */ 2673 2673 + snd_dbri_proc(dbri); 2674 2674 + 2675 2675 + if ((err = snd_card_register(card)) < 0) { 2676 2676 + snd_dbri_free(dbri); 2677 2677 + snd_card_free(card); 2678 2678 + return err; 2679 2679 + } 2680 2680 + 2681 2681 + printk(KERN_INFO "audio%d at %p (irq %d) is DBRI(%c)+CS4215(%d)\n", 2682 2682 + dev, dbri->regs, 2683 2683 + dbri->irq, dbri->dbri_version, dbri->mm.version); 2684 2684 + dev++; 2685 2685 + 2686 2686 + return 0; 2687 2687 + } 2688 2688 + 2689 2689 + /* Probe for the dbri chip and then attach the driver. */ 2690 2690 + static int __init dbri_init(void) 2691 2691 + { 2692 2692 + struct sbus_bus *sbus; 2693 2693 + struct sbus_dev *sdev; 2694 2694 + int found = 0; 2695 2695 + 2696 2696 + /* Probe each SBUS for the DBRI chip(s). */ 2697 2697 + for_all_sbusdev(sdev, sbus) { 2698 2698 + /* 2699 2699 + * The version is coded in the last character 2700 2700 + */ 2701 2701 + if (!strncmp(sdev->prom_name, "SUNW,DBRI", 9)) { 2702 2702 + dprintk(D_GEN, "DBRI: Found %s in SBUS slot %d\n", 2703 2703 + sdev->prom_name, sdev->slot); 2704 2704 + 2705 2705 + if (dbri_attach(sdev->prom_node, sdev) == 0) 2706 2706 + found++; 2707 2707 + } 2708 2708 + } 2709 2709 + 2710 2710 + return (found > 0) ? 0 : -EIO; 2711 2711 + } 2712 2712 + 2713 2713 + static void __exit dbri_exit(void) 2714 2714 + { 2715 2715 + snd_dbri_t *this = dbri_list; 2716 2716 + 2717 2717 + while (this != NULL) { 2718 2718 + snd_dbri_t *next = this->next; 2719 2719 + snd_card_t *card = this->card; 2720 2720 + 2721 2721 + snd_dbri_free(this); 2722 2722 + snd_card_free(card); 2723 2723 + this = next; 2724 2724 + } 2725 2725 + dbri_list = NULL; 2726 2726 + } 2727 2727 + 2728 2728 + module_init(dbri_init); 2729 2729 + module_exit(dbri_exit);

+62 -43

sound/usb/usbaudio.c

reviewed

··· 153 153 unsigned int format; /* USB data format */ 154 154 unsigned int datapipe; /* the data i/o pipe */ 155 155 unsigned int syncpipe; /* 1 - async out or adaptive in */ 156 156 + unsigned int datainterval; /* log_2 of data packet interval */ 156 157 unsigned int syncinterval; /* P for adaptive mode, 0 otherwise */ 157 158 unsigned int freqn; /* nominal sampling rate in fs/fps in Q16.16 format */ 158 159 unsigned int freqm; /* momentary sampling rate in fs/fps in Q16.16 format */ ··· 519 518 if (subs->fill_max) 520 519 counts = subs->maxframesize; /* fixed */ 521 520 else { 522 522 - subs->phase = (subs->phase & 0xffff) + subs->freqm; 521 521 + subs->phase = (subs->phase & 0xffff) 522 522 + + (subs->freqm << subs->datainterval); 523 523 counts = subs->phase >> 16; 524 524 if (counts > subs->maxframesize) 525 525 counts = subs->maxframesize; ··· 792 790 */ 793 791 static int wait_clear_urbs(snd_usb_substream_t *subs) 794 792 { 795 795 - int timeout = HZ; 793 793 + unsigned long end_time = jiffies + msecs_to_jiffies(1000); 796 794 unsigned int i; 797 795 int alive; 798 796 ··· 812 810 break; 813 811 set_current_state(TASK_UNINTERRUPTIBLE); 814 812 schedule_timeout(1); 815 815 - } while (--timeout > 0); 813 813 + } while (time_before(jiffies, end_time)); 816 814 if (alive) 817 815 snd_printk(KERN_ERR "timeout: still %d active urbs..\n", alive); 818 816 return 0; ··· 901 899 else 902 900 subs->freqn = get_usb_high_speed_rate(rate); 903 901 subs->freqm = subs->freqn; 904 904 - subs->freqmax = subs->freqn + (subs->freqn >> 2); /* max. allowed frequency */ 905 905 - subs->phase = 0; 906 906 - 907 907 - /* calculate the max. size of packet */ 908 908 - maxsize = ((subs->freqmax + 0xffff) * (frame_bits >> 3)) >> 16; 909 909 - if (subs->maxpacksize && maxsize > subs->maxpacksize) { 910 910 - //snd_printd(KERN_DEBUG "maxsize %d is greater than defined size %d\n", 911 911 - // maxsize, subs->maxpacksize); 902 902 + /* calculate max. frequency */ 903 903 + if (subs->maxpacksize) { 904 904 + /* whatever fits into a max. size packet */ 912 905 maxsize = subs->maxpacksize; 906 906 + subs->freqmax = (maxsize / (frame_bits >> 3)) 907 907 + << (16 - subs->datainterval); 908 908 + } else { 909 909 + /* no max. packet size: just take 25% higher than nominal */ 910 910 + subs->freqmax = subs->freqn + (subs->freqn >> 2); 911 911 + maxsize = ((subs->freqmax + 0xffff) * (frame_bits >> 3)) 912 912 + >> (16 - subs->datainterval); 913 913 } 914 914 + subs->phase = 0; 914 915 915 916 if (subs->fill_max) 916 917 subs->curpacksize = subs->maxpacksize; ··· 923 918 if (snd_usb_get_speed(subs->dev) == USB_SPEED_FULL) 924 919 urb_packs = nrpacks; 925 920 else 926 926 - urb_packs = nrpacks * 8; 921 921 + urb_packs = (nrpacks * 8) >> subs->datainterval; 927 922 928 923 /* allocate a temporary buffer for playback */ 929 924 if (is_playback) { ··· 996 991 u->urb->pipe = subs->datapipe; 997 992 u->urb->transfer_flags = URB_ISO_ASAP; 998 993 u->urb->number_of_packets = u->packets; 999 999 - u->urb->interval = 1; 994 994 + u->urb->interval = 1 << subs->datainterval; 1000 995 u->urb->context = u; 1001 996 u->urb->complete = snd_usb_complete_callback(snd_complete_urb); 1002 997 } ··· 1200 1195 subs->datapipe = usb_sndisocpipe(dev, ep); 1201 1196 else 1202 1197 subs->datapipe = usb_rcvisocpipe(dev, ep); 1198 1198 + if (snd_usb_get_speed(subs->dev) == USB_SPEED_HIGH && 1199 1199 + get_endpoint(alts, 0)->bInterval >= 1 && 1200 1200 + get_endpoint(alts, 0)->bInterval <= 4) 1201 1201 + subs->datainterval = get_endpoint(alts, 0)->bInterval - 1; 1202 1202 + else 1203 1203 + subs->datainterval = 0; 1203 1204 subs->syncpipe = subs->syncinterval = 0; 1204 1205 subs->maxpacksize = fmt->maxpacksize; 1205 1206 subs->fill_max = 0; ··· 2408 2397 if (chip->usb_id == USB_ID(0x041e, 0x3000) || 2409 2398 chip->usb_id == USB_ID(0x041e, 0x3020)) { 2410 2399 if (fmt[3] == USB_FORMAT_TYPE_I && 2411 2411 - stream == SNDRV_PCM_STREAM_PLAYBACK && 2412 2400 fp->rates != SNDRV_PCM_RATE_48000 && 2413 2401 fp->rates != SNDRV_PCM_RATE_96000) 2414 2414 - return -1; /* use 48k only */ 2402 2402 + return -1; 2415 2403 } 2416 2404 #endif 2417 2405 return 0; ··· 2502 2492 fp->altset_idx = i; 2503 2493 fp->endpoint = get_endpoint(alts, 0)->bEndpointAddress; 2504 2494 fp->ep_attr = get_endpoint(alts, 0)->bmAttributes; 2505 2505 - /* FIXME: decode wMaxPacketSize of high bandwith endpoints */ 2506 2495 fp->maxpacksize = le16_to_cpu(get_endpoint(alts, 0)->wMaxPacketSize); 2496 2496 + if (snd_usb_get_speed(dev) == USB_SPEED_HIGH) 2497 2497 + fp->maxpacksize = (((fp->maxpacksize >> 11) & 3) + 1) 2498 2498 + * (fp->maxpacksize & 0x7ff); 2507 2499 fp->attributes = csep[3]; 2508 2500 2509 2501 /* some quirks for attributes here */ ··· 2735 2723 * to detect the sample rate is by looking at wMaxPacketSize. 2736 2724 */ 2737 2725 static int create_ua700_ua25_quirk(snd_usb_audio_t *chip, 2738 2738 - struct usb_interface *iface) 2726 2726 + struct usb_interface *iface, 2727 2727 + const snd_usb_audio_quirk_t *quirk) 2739 2728 { 2740 2729 static const struct audioformat ua_format = { 2741 2730 .format = SNDRV_PCM_FORMAT_S24_3LE, ··· 2827 2814 /* 2828 2815 * Create a stream for an Edirol UA-1000 interface. 2829 2816 */ 2830 2830 - static int create_ua1000_quirk(snd_usb_audio_t *chip, struct usb_interface *iface) 2817 2817 + static int create_ua1000_quirk(snd_usb_audio_t *chip, 2818 2818 + struct usb_interface *iface, 2819 2819 + const snd_usb_audio_quirk_t *quirk) 2831 2820 { 2832 2821 static const struct audioformat ua1000_format = { 2833 2822 .format = SNDRV_PCM_FORMAT_S32_LE, ··· 2906 2891 return 0; 2907 2892 } 2908 2893 2894 2894 + static int ignore_interface_quirk(snd_usb_audio_t *chip, 2895 2895 + struct usb_interface *iface, 2896 2896 + const snd_usb_audio_quirk_t *quirk) 2897 2897 + { 2898 2898 + return 0; 2899 2899 + } 2900 2900 + 2909 2901 2910 2902 /* 2911 2903 * boot quirks ··· 2948 2926 2949 2927 static int snd_usb_audigy2nx_boot_quirk(struct usb_device *dev) 2950 2928 { 2951 2951 - #if 0 2952 2952 - /* TODO: enable this when high speed synchronization actually works */ 2953 2929 u8 buf = 1; 2954 2930 2955 2931 snd_usb_ctl_msg(dev, usb_rcvctrlpipe(dev, 0), 0x2a, ··· 2959 2939 1, 2000, NULL, 0, 1000); 2960 2940 return -ENODEV; 2961 2941 } 2962 2962 - #endif 2963 2942 return 0; 2964 2943 } 2965 2944 ··· 2975 2956 struct usb_interface *iface, 2976 2957 const snd_usb_audio_quirk_t *quirk) 2977 2958 { 2978 2978 - switch (quirk->type) { 2979 2979 - case QUIRK_MIDI_FIXED_ENDPOINT: 2980 2980 - case QUIRK_MIDI_YAMAHA: 2981 2981 - case QUIRK_MIDI_MIDIMAN: 2982 2982 - case QUIRK_MIDI_NOVATION: 2983 2983 - case QUIRK_MIDI_MOTU: 2984 2984 - case QUIRK_MIDI_EMAGIC: 2985 2985 - return snd_usb_create_midi_interface(chip, iface, quirk); 2986 2986 - case QUIRK_COMPOSITE: 2987 2987 - return create_composite_quirk(chip, iface, quirk); 2988 2988 - case QUIRK_AUDIO_FIXED_ENDPOINT: 2989 2989 - return create_fixed_stream_quirk(chip, iface, quirk); 2990 2990 - case QUIRK_AUDIO_STANDARD_INTERFACE: 2991 2991 - case QUIRK_MIDI_STANDARD_INTERFACE: 2992 2992 - return create_standard_interface_quirk(chip, iface, quirk); 2993 2993 - case QUIRK_AUDIO_EDIROL_UA700_UA25: 2994 2994 - return create_ua700_ua25_quirk(chip, iface); 2995 2995 - case QUIRK_AUDIO_EDIROL_UA1000: 2996 2996 - return create_ua1000_quirk(chip, iface); 2997 2997 - case QUIRK_IGNORE_INTERFACE: 2998 2998 - return 0; 2999 2999 - default: 2959 2959 + typedef int (*quirk_func_t)(snd_usb_audio_t *, struct usb_interface *, 2960 2960 + const snd_usb_audio_quirk_t *); 2961 2961 + static const quirk_func_t quirk_funcs[] = { 2962 2962 + [QUIRK_IGNORE_INTERFACE] = ignore_interface_quirk, 2963 2963 + [QUIRK_COMPOSITE] = create_composite_quirk, 2964 2964 + [QUIRK_MIDI_STANDARD_INTERFACE] = snd_usb_create_midi_interface, 2965 2965 + [QUIRK_MIDI_FIXED_ENDPOINT] = snd_usb_create_midi_interface, 2966 2966 + [QUIRK_MIDI_YAMAHA] = snd_usb_create_midi_interface, 2967 2967 + [QUIRK_MIDI_MIDIMAN] = snd_usb_create_midi_interface, 2968 2968 + [QUIRK_MIDI_NOVATION] = snd_usb_create_midi_interface, 2969 2969 + [QUIRK_MIDI_RAW] = snd_usb_create_midi_interface, 2970 2970 + [QUIRK_MIDI_EMAGIC] = snd_usb_create_midi_interface, 2971 2971 + [QUIRK_MIDI_MIDITECH] = snd_usb_create_midi_interface, 2972 2972 + [QUIRK_AUDIO_STANDARD_INTERFACE] = create_standard_interface_quirk, 2973 2973 + [QUIRK_AUDIO_FIXED_ENDPOINT] = create_fixed_stream_quirk, 2974 2974 + [QUIRK_AUDIO_EDIROL_UA700_UA25] = create_ua700_ua25_quirk, 2975 2975 + [QUIRK_AUDIO_EDIROL_UA1000] = create_ua1000_quirk, 2976 2976 + }; 2977 2977 + 2978 2978 + if (quirk->type < QUIRK_TYPE_COUNT) { 2979 2979 + return quirk_funcs[quirk->type](chip, iface, quirk); 2980 2980 + } else { 3000 2981 snd_printd(KERN_ERR "invalid quirk type %d\n", quirk->type); 3001 2982 return -ENXIO; 3002 2983 }

+22 -16

sound/usb/usbaudio.h

reviewed

··· 153 153 #define QUIRK_NO_INTERFACE -2 154 154 #define QUIRK_ANY_INTERFACE -1 155 155 156 156 - /* quirk type */ 157 157 - #define QUIRK_MIDI_FIXED_ENDPOINT 0 158 158 - #define QUIRK_MIDI_YAMAHA 1 159 159 - #define QUIRK_MIDI_MIDIMAN 2 160 160 - #define QUIRK_COMPOSITE 3 161 161 - #define QUIRK_AUDIO_FIXED_ENDPOINT 4 162 162 - #define QUIRK_AUDIO_STANDARD_INTERFACE 5 163 163 - #define QUIRK_MIDI_STANDARD_INTERFACE 6 164 164 - #define QUIRK_AUDIO_EDIROL_UA700_UA25 7 165 165 - #define QUIRK_AUDIO_EDIROL_UA1000 8 166 166 - #define QUIRK_IGNORE_INTERFACE 9 167 167 - #define QUIRK_MIDI_NOVATION 10 168 168 - #define QUIRK_MIDI_MOTU 11 169 169 - #define QUIRK_MIDI_EMAGIC 12 156 156 + enum quirk_type { 157 157 + QUIRK_IGNORE_INTERFACE, 158 158 + QUIRK_COMPOSITE, 159 159 + QUIRK_MIDI_STANDARD_INTERFACE, 160 160 + QUIRK_MIDI_FIXED_ENDPOINT, 161 161 + QUIRK_MIDI_YAMAHA, 162 162 + QUIRK_MIDI_MIDIMAN, 163 163 + QUIRK_MIDI_NOVATION, 164 164 + QUIRK_MIDI_RAW, 165 165 + QUIRK_MIDI_EMAGIC, 166 166 + QUIRK_MIDI_MIDITECH, 167 167 + QUIRK_AUDIO_STANDARD_INTERFACE, 168 168 + QUIRK_AUDIO_FIXED_ENDPOINT, 169 169 + QUIRK_AUDIO_EDIROL_UA700_UA25, 170 170 + QUIRK_AUDIO_EDIROL_UA1000, 171 171 + 172 172 + QUIRK_TYPE_COUNT 173 173 + }; 170 174 171 175 typedef struct snd_usb_audio_quirk snd_usb_audio_quirk_t; 172 176 typedef struct snd_usb_midi_endpoint_info snd_usb_midi_endpoint_info_t; ··· 179 175 const char *vendor_name; 180 176 const char *product_name; 181 177 int16_t ifnum; 182 182 - int16_t type; 178 178 + uint16_t type; 183 179 const void *data; 184 180 }; 185 181 ··· 209 205 210 206 /* for QUIRK_IGNORE_INTERFACE, data is NULL */ 211 207 212 212 - /* for QUIRK_MIDI_NOVATION and _MOTU, data is NULL */ 208 208 + /* for QUIRK_MIDI_NOVATION and _RAW, data is NULL */ 213 209 214 210 /* for QUIRK_MIDI_EMAGIC, data points to a snd_usb_midi_endpoint_info 215 211 * structure (out_cables and in_cables only) */ 212 212 + 213 213 + /* for QUIRK_MIDI_MIDITECH, data is NULL */ 216 214 217 215 /* 218 216 */

+12 -9

sound/usb/usbmidi.c

reviewed

··· 524 524 }; 525 525 526 526 /* 527 527 - * Mark of the Unicorn USB MIDI protocol: raw MIDI. 527 527 + * "raw" protocol: used by the MOTU FastLane. 528 528 */ 529 529 530 530 - static void snd_usbmidi_motu_input(snd_usb_midi_in_endpoint_t* ep, 531 531 - uint8_t* buffer, int buffer_length) 530 530 + static void snd_usbmidi_raw_input(snd_usb_midi_in_endpoint_t* ep, 531 531 + uint8_t* buffer, int buffer_length) 532 532 { 533 533 snd_usbmidi_input_data(ep, 0, buffer, buffer_length); 534 534 } 535 535 536 536 - static void snd_usbmidi_motu_output(snd_usb_midi_out_endpoint_t* ep) 536 536 + static void snd_usbmidi_raw_output(snd_usb_midi_out_endpoint_t* ep) 537 537 { 538 538 int count; 539 539 ··· 549 549 ep->urb->transfer_buffer_length = count; 550 550 } 551 551 552 552 - static struct usb_protocol_ops snd_usbmidi_motu_ops = { 553 553 - .input = snd_usbmidi_motu_input, 554 554 - .output = snd_usbmidi_motu_output, 552 552 + static struct usb_protocol_ops snd_usbmidi_raw_ops = { 553 553 + .input = snd_usbmidi_raw_input, 554 554 + .output = snd_usbmidi_raw_output, 555 555 }; 556 556 557 557 /* ··· 1505 1505 umidi->usb_protocol_ops = &snd_usbmidi_novation_ops; 1506 1506 err = snd_usbmidi_detect_per_port_endpoints(umidi, endpoints); 1507 1507 break; 1508 1508 - case QUIRK_MIDI_MOTU: 1509 1509 - umidi->usb_protocol_ops = &snd_usbmidi_motu_ops; 1508 1508 + case QUIRK_MIDI_RAW: 1509 1509 + umidi->usb_protocol_ops = &snd_usbmidi_raw_ops; 1510 1510 err = snd_usbmidi_detect_per_port_endpoints(umidi, endpoints); 1511 1511 break; 1512 1512 case QUIRK_MIDI_EMAGIC: ··· 1514 1514 memcpy(&endpoints[0], quirk->data, 1515 1515 sizeof(snd_usb_midi_endpoint_info_t)); 1516 1516 err = snd_usbmidi_detect_endpoints(umidi, &endpoints[0], 1); 1517 1517 + break; 1518 1518 + case QUIRK_MIDI_MIDITECH: 1519 1519 + err = snd_usbmidi_detect_per_port_endpoints(umidi, endpoints); 1517 1520 break; 1518 1521 default: 1519 1522 snd_printd(KERN_ERR "invalid quirk type %d\n", quirk->type);

+27 -2

sound/usb/usbquirks.h

reviewed

··· 116 116 YAMAHA_DEVICE(0x103a, NULL), 117 117 YAMAHA_DEVICE(0x103b, NULL), 118 118 YAMAHA_DEVICE(0x103c, NULL), 119 119 + YAMAHA_DEVICE(0x103d, NULL), 119 120 YAMAHA_DEVICE(0x2000, "DGP-7"), 120 121 YAMAHA_DEVICE(0x2001, "DGP-5"), 121 122 YAMAHA_DEVICE(0x2002, NULL), ··· 1260 1259 /* Mark of the Unicorn devices */ 1261 1260 { 1262 1261 /* thanks to Robert A. Lerche <ral 'at' msbit.com> */ 1263 1263 - USB_DEVICE(0x07fd, 0x0001), 1262 1262 + .match_flags = USB_DEVICE_ID_MATCH_VENDOR | 1263 1263 + USB_DEVICE_ID_MATCH_PRODUCT | 1264 1264 + USB_DEVICE_ID_MATCH_DEV_SUBCLASS, 1265 1265 + .idVendor = 0x07fd, 1266 1266 + .idProduct = 0x0001, 1267 1267 + .bDeviceSubClass = 2, 1264 1268 .driver_info = (unsigned long) & (const snd_usb_audio_quirk_t) { 1265 1269 .vendor_name = "MOTU", 1266 1270 .product_name = "Fastlane", ··· 1274 1268 .data = & (const snd_usb_audio_quirk_t[]) { 1275 1269 { 1276 1270 .ifnum = 0, 1277 1277 - .type = QUIRK_MIDI_MOTU 1271 1271 + .type = QUIRK_MIDI_RAW 1278 1272 }, 1279 1273 { 1280 1274 .ifnum = 1, ··· 1375 1369 .product_name = "ReMOTE25", 1376 1370 .ifnum = 0, 1377 1371 .type = QUIRK_MIDI_NOVATION 1372 1372 + } 1373 1373 + }, 1374 1374 + 1375 1375 + { 1376 1376 + USB_DEVICE(0x4752, 0x0011), 1377 1377 + .driver_info = (unsigned long) & (const snd_usb_audio_quirk_t) { 1378 1378 + .vendor_name = "Miditech", 1379 1379 + .product_name = "Midistart-2", 1380 1380 + .ifnum = 0, 1381 1381 + .type = QUIRK_MIDI_MIDITECH 1382 1382 + } 1383 1383 + }, 1384 1384 + { 1385 1385 + USB_DEVICE(0x7104, 0x2202), 1386 1386 + .driver_info = (unsigned long) & (const snd_usb_audio_quirk_t) { 1387 1387 + .vendor_name = "Miditech", 1388 1388 + .product_name = "MidiStudio-2", 1389 1389 + .ifnum = 0, 1390 1390 + .type = QUIRK_MIDI_MIDITECH 1378 1391 } 1379 1392 }, 1380 1393

+1 -2

sound/usb/usx2y/usX2Yhwdep.c

reviewed

··· 232 232 if (err) 233 233 return err; 234 234 if (dsp->index == 1) { 235 235 - set_current_state(TASK_UNINTERRUPTIBLE); 236 236 - schedule_timeout(HZ/4); // give the device some time 235 235 + msleep(250); // give the device some time 237 236 err = usX2Y_AsyncSeq04_init(priv); 238 237 if (err) { 239 238 snd_printk("usX2Y_AsyncSeq04_init error \n");

+2 -4

sound/usb/usx2y/usx2yhwdeppcm.c

reviewed

··· 50 50 Currently rawusb dma pcm buffer transport (this file) is only available to snd-usb-usx2y. 51 51 */ 52 52 53 53 + #include <linux/delay.h> 53 54 #include "usbusx2yaudio.c" 54 55 55 56 #if defined(USX2Y_NRPACKS_VARIABLE) || (!defined(USX2Y_NRPACKS_VARIABLE) && USX2Y_NRPACKS == 1) ··· 521 520 usX2Y->hwdep_pcm_shm->playback_iso_start = -1; 522 521 if (atomic_read(&subs->state) < state_PREPARED) { 523 522 while (usX2Y_iso_frames_per_buffer(runtime, usX2Y) > usX2Y->hwdep_pcm_shm->captured_iso_frames) { 524 524 - signed long timeout; 525 523 snd_printd("Wait: iso_frames_per_buffer=%i,captured_iso_frames=%i\n", usX2Y_iso_frames_per_buffer(runtime, usX2Y), usX2Y->hwdep_pcm_shm->captured_iso_frames); 526 526 - set_current_state(TASK_INTERRUPTIBLE); 527 527 - timeout = schedule_timeout(HZ/100 + 1); 528 528 - if (signal_pending(current)) { 524 524 + if (msleep_interruptible(10)) { 529 525 err = -ERESTARTSYS; 530 526 goto up_prepare_mutex; 531 527 }