Merge branch 'bnxt_en-updates-for-net-next'

+43 -14

drivers/net/ethernet/broadcom/bnxt/bnxt.c

··· 265 265 [BNXT_CTX_CA1] = DBG_LOG_BUFFER_FLUSH_REQ_TYPE_CA1_TRACE, 266 266 [BNXT_CTX_CA2] = DBG_LOG_BUFFER_FLUSH_REQ_TYPE_CA2_TRACE, 267 267 [BNXT_CTX_RIGP1] = DBG_LOG_BUFFER_FLUSH_REQ_TYPE_RIGP1_TRACE, 268 + [BNXT_CTX_KONG] = DBG_LOG_BUFFER_FLUSH_REQ_TYPE_AFM_KONG_HWRM_TRACE, 269 + [BNXT_CTX_QPC] = DBG_LOG_BUFFER_FLUSH_REQ_TYPE_ERR_QPC_TRACE, 268 270 }; 269 271 270 272 static struct workqueue_struct *bnxt_pf_wq; ··· 6838 6836 req->dflt_ring_grp = cpu_to_le16(bp->grp_info[grp_idx].fw_grp_id); 6839 6837 req->lb_rule = cpu_to_le16(0xffff); 6840 6838 vnic_mru: 6841 - vnic->mru = bp->dev->mtu + ETH_HLEN + VLAN_HLEN; 6839 + vnic->mru = bp->dev->mtu + VLAN_ETH_HLEN; 6842 6840 req->mru = cpu_to_le16(vnic->mru); 6843 6841 6844 6842 req->vnic_id = cpu_to_le16(vnic->fw_vnic_id); ··· 9152 9150 return rc; 9153 9151 } 9154 9152 9155 - static int bnxt_backing_store_cfg_v2(struct bnxt *bp, u32 ena) 9153 + static int bnxt_backing_store_cfg_v2(struct bnxt *bp) 9156 9154 { 9157 9155 struct bnxt_ctx_mem_info *ctx = bp->ctx; 9158 9156 struct bnxt_ctx_mem_type *ctxm; ··· 9160 9158 int rc = 0; 9161 9159 u16 type; 9162 9160 9163 - for (type = BNXT_CTX_SRT; type <= BNXT_CTX_RIGP1; type++) { 9161 + for (type = BNXT_CTX_SRT; type <= BNXT_CTX_QPC; type++) { 9164 9162 ctxm = &ctx->ctx_arr[type]; 9165 9163 if (!bnxt_bs_trace_avail(bp, type)) 9166 9164 continue; ··· 9178 9176 } 9179 9177 9180 9178 if (last_type == BNXT_CTX_INV) { 9181 - if (!ena) 9179 + for (type = 0; type < BNXT_CTX_MAX; type++) { 9180 + ctxm = &ctx->ctx_arr[type]; 9181 + if (ctxm->mem_valid) 9182 + last_type = type; 9183 + } 9184 + if (last_type == BNXT_CTX_INV) 9182 9185 return 0; 9183 - else if (ena & FUNC_BACKING_STORE_CFG_REQ_ENABLES_TIM) 9184 - last_type = BNXT_CTX_MAX - 1; 9185 - else 9186 - last_type = BNXT_CTX_L2_MAX - 1; 9187 9186 } 9188 9187 ctx->ctx_arr[last_type].last = 1; 9189 9188 ··· 9311 9308 if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED)) 9312 9309 return 0; 9313 9310 9311 + ena = 0; 9312 + if (!(bp->flags & BNXT_FLAG_CHIP_P5_PLUS)) 9313 + goto skip_legacy; 9314 + 9314 9315 ctxm = &ctx->ctx_arr[BNXT_CTX_QP]; 9315 9316 l2_qps = ctxm->qp_l2_entries; 9316 9317 qp1_qps = ctxm->qp_qp1_entries; ··· 9323 9316 ctxm = &ctx->ctx_arr[BNXT_CTX_SRQ]; 9324 9317 srqs = ctxm->srq_l2_entries; 9325 9318 max_srqs = ctxm->max_entries; 9326 - ena = 0; 9327 9319 if ((bp->flags & BNXT_FLAG_ROCE_CAP) && !is_kdump_kernel()) { 9328 9320 pg_lvl = 2; 9329 9321 if (BNXT_SW_RES_LMT(bp)) { ··· 9416 9410 ena |= FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_SP << i; 9417 9411 ena |= FUNC_BACKING_STORE_CFG_REQ_DFLT_ENABLES; 9418 9412 9413 + skip_legacy: 9419 9414 if (bp->fw_cap & BNXT_FW_CAP_BACKING_STORE_V2) 9420 - rc = bnxt_backing_store_cfg_v2(bp, ena); 9415 + rc = bnxt_backing_store_cfg_v2(bp); 9421 9416 else 9422 9417 rc = bnxt_hwrm_func_backing_store_cfg(bp, ena); 9423 9418 if (rc) { ··· 9632 9625 9633 9626 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp) 9634 9627 { 9628 + u32 flags, flags_ext, flags_ext2, flags_ext3; 9629 + struct bnxt_hw_resc *hw_resc = &bp->hw_resc; 9635 9630 struct hwrm_func_qcaps_output *resp; 9636 9631 struct hwrm_func_qcaps_input *req; 9637 - struct bnxt_hw_resc *hw_resc = &bp->hw_resc; 9638 - u32 flags, flags_ext, flags_ext2; 9639 9632 int rc; 9640 9633 9641 9634 rc = hwrm_req_init(bp, req, HWRM_FUNC_QCAPS); ··· 9701 9694 if (BNXT_PF(bp) && 9702 9695 (flags_ext2 & FUNC_QCAPS_RESP_FLAGS_EXT2_ROCE_VF_RESOURCE_MGMT_SUPPORTED)) 9703 9696 bp->fw_cap |= BNXT_FW_CAP_ROCE_VF_RESC_MGMT_SUPPORTED; 9697 + 9698 + flags_ext3 = le32_to_cpu(resp->flags_ext3); 9699 + if (flags_ext3 & FUNC_QCAPS_RESP_FLAGS_EXT3_ROCE_VF_DYN_ALLOC_SUPPORT) 9700 + bp->fw_cap |= BNXT_FW_CAP_ROCE_VF_DYN_ALLOC_SUPPORT; 9704 9701 9705 9702 bp->tx_push_thresh = 0; 9706 9703 if ((flags & FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED) && ··· 14748 14737 return false; 14749 14738 } 14750 14739 14740 + static void bnxt_hwrm_pfcwd_qcaps(struct bnxt *bp) 14741 + { 14742 + struct hwrm_queue_pfcwd_timeout_qcaps_output *resp; 14743 + struct hwrm_queue_pfcwd_timeout_qcaps_input *req; 14744 + int rc; 14745 + 14746 + bp->max_pfcwd_tmo_ms = 0; 14747 + rc = hwrm_req_init(bp, req, HWRM_QUEUE_PFCWD_TIMEOUT_QCAPS); 14748 + if (rc) 14749 + return; 14750 + resp = hwrm_req_hold(bp, req); 14751 + rc = hwrm_req_send_silent(bp, req); 14752 + if (!rc) 14753 + bp->max_pfcwd_tmo_ms = le16_to_cpu(resp->max_pfcwd_timeout); 14754 + hwrm_req_drop(bp, req); 14755 + } 14756 + 14751 14757 static int bnxt_fw_init_one_p1(struct bnxt *bp) 14752 14758 { 14753 14759 int rc; ··· 14842 14814 if (bnxt_fw_pre_resv_vnics(bp)) 14843 14815 bp->fw_cap |= BNXT_FW_CAP_PRE_RESV_VNICS; 14844 14816 14817 + bnxt_hwrm_pfcwd_qcaps(bp); 14845 14818 bnxt_hwrm_func_qcfg(bp); 14846 14819 bnxt_hwrm_vnic_qcaps(bp); 14847 14820 bnxt_hwrm_port_led_qcaps(bp); ··· 16104 16075 napi_enable_locked(&bnapi->napi); 16105 16076 bnxt_db_nq_arm(bp, &cpr->cp_db, cpr->cp_raw_cons); 16106 16077 16107 - mru = bp->dev->mtu + ETH_HLEN + VLAN_HLEN; 16078 + mru = bp->dev->mtu + VLAN_ETH_HLEN; 16108 16079 for (i = 0; i < bp->nr_vnics; i++) { 16109 16080 vnic = &bp->vnic_info[i]; 16110 16081 ··· 16185 16156 struct bnxt *bp = netdev_priv(dev); 16186 16157 16187 16158 if (BNXT_PF(bp)) 16188 - bnxt_sriov_disable(bp); 16159 + __bnxt_sriov_disable(bp); 16189 16160 16190 16161 bnxt_rdma_aux_device_del(bp); 16191 16162

+8 -1

drivers/net/ethernet/broadcom/bnxt/bnxt.h

··· 1968 1968 #define BNXT_CTX_CA1 FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CA1_TRACE 1969 1969 #define BNXT_CTX_CA2 FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CA2_TRACE 1970 1970 #define BNXT_CTX_RIGP1 FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_RIGP1_TRACE 1971 + #define BNXT_CTX_KONG FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_AFM_KONG_HWRM_TRACE 1972 + #define BNXT_CTX_QPC FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_ERR_QPC_TRACE 1971 1973 1972 1974 #define BNXT_CTX_MAX (BNXT_CTX_TIM + 1) 1973 1975 #define BNXT_CTX_L2_MAX (BNXT_CTX_FTQM + 1) 1974 - #define BNXT_CTX_V2_MAX (BNXT_CTX_RIGP1 + 1) 1976 + #define BNXT_CTX_V2_MAX (BNXT_CTX_QPC + 1) 1975 1977 #define BNXT_CTX_INV ((u16)-1) 1976 1978 1977 1979 struct bnxt_ctx_mem_info { ··· 2426 2424 u8 max_q; 2427 2425 u8 num_tc; 2428 2426 2427 + u16 max_pfcwd_tmo_ms; 2428 + 2429 2429 u8 tph_mode; 2430 2430 2431 2431 unsigned int current_interval; ··· 2481 2477 #define BNXT_FW_CAP_ENABLE_RDMA_SRIOV BIT_ULL(5) 2482 2478 #define BNXT_FW_CAP_ROCE_VF_RESC_MGMT_SUPPORTED BIT_ULL(6) 2483 2479 #define BNXT_FW_CAP_KONG_MB_CHNL BIT_ULL(7) 2480 + #define BNXT_FW_CAP_ROCE_VF_DYN_ALLOC_SUPPORT BIT_ULL(8) 2484 2481 #define BNXT_FW_CAP_OVS_64BIT_HANDLE BIT_ULL(10) 2485 2482 #define BNXT_FW_CAP_TRUSTED_VF BIT_ULL(11) 2486 2483 #define BNXT_FW_CAP_ERROR_RECOVERY BIT_ULL(13) ··· 2526 2521 #define BNXT_SUPPORTS_MULTI_RSS_CTX(bp) \ 2527 2522 (BNXT_PF(bp) && BNXT_SUPPORTS_NTUPLE_VNIC(bp) && \ 2528 2523 ((bp)->rss_cap & BNXT_RSS_CAP_MULTI_RSS_CTX)) 2524 + #define BNXT_ROCE_VF_DYN_ALLOC_CAP(bp) \ 2525 + ((bp)->fw_cap & BNXT_FW_CAP_ROCE_VF_DYN_ALLOC_SUPPORT) 2529 2526 #define BNXT_SUPPORTS_QUEUE_API(bp) \ 2530 2527 (BNXT_PF(bp) && BNXT_SUPPORTS_NTUPLE_VNIC(bp) && \ 2531 2528 ((bp)->fw_cap & BNXT_FW_CAP_VNIC_RE_FLUSH))

+3 -1

drivers/net/ethernet/broadcom/bnxt/bnxt_coredump.c

··· 36 36 [BNXT_CTX_CA1] = BNXT_CTX_MEM_SEG_CA1, 37 37 [BNXT_CTX_CA2] = BNXT_CTX_MEM_SEG_CA2, 38 38 [BNXT_CTX_RIGP1] = BNXT_CTX_MEM_SEG_RIGP1, 39 + [BNXT_CTX_KONG] = BNXT_CTX_MEM_SEG_KONG, 40 + [BNXT_CTX_QPC] = BNXT_CTX_MEM_SEG_QPC, 39 41 }; 40 42 41 43 static int bnxt_dbg_hwrm_log_buffer_flush(struct bnxt *bp, u16 type, u32 flags, ··· 361 359 362 360 if (buf) 363 361 buf += offset; 364 - for (type = 0 ; type <= BNXT_CTX_RIGP1; type++) { 362 + for (type = 0; type < BNXT_CTX_V2_MAX; type++) { 365 363 struct bnxt_ctx_mem_type *ctxm = &ctx->ctx_arr[type]; 366 364 bool trace = bnxt_bs_trace_avail(bp, type); 367 365 u32 seg_id = bnxt_bstore_to_seg_id[type];

+2

drivers/net/ethernet/broadcom/bnxt/bnxt_coredump.h

··· 102 102 #define BNXT_CTX_MEM_SEG_CA1 0x9 103 103 #define BNXT_CTX_MEM_SEG_CA2 0xa 104 104 #define BNXT_CTX_MEM_SEG_RIGP1 0xb 105 + #define BNXT_CTX_MEM_SEG_QPC 0xc 106 + #define BNXT_CTX_MEM_SEG_KONG 0xd 105 107 106 108 #define BNXT_CRASH_DUMP_LEN (8 << 20) 107 109

-13

drivers/net/ethernet/broadcom/bnxt/bnxt_devlink.c

··· 40 40 struct bnxt *bp = bnxt_get_bp_from_dl(dl); 41 41 int rc; 42 42 43 - if (!BNXT_PF(bp)) { 44 - NL_SET_ERR_MSG_MOD(extack, 45 - "flash update not supported from a VF"); 46 - return -EPERM; 47 - } 48 - 49 43 devlink_flash_update_status_notify(dl, "Preparing to flash", NULL, 0, 0); 50 44 rc = bnxt_flash_package_from_fw_obj(bp->dev, params->fw, 0, extack); 51 45 if (!rc) ··· 1074 1080 static int bnxt_hwrm_nvm_req(struct bnxt *bp, u32 param_id, void *msg, 1075 1081 union devlink_param_value *val) 1076 1082 { 1077 - struct hwrm_nvm_get_variable_input *req = msg; 1078 1083 const struct bnxt_dl_nvm_param *nvm_param; 1079 1084 int i; 1080 - 1081 - /* Get/Set NVM CFG parameter is supported only on PFs */ 1082 - if (BNXT_VF(bp)) { 1083 - hwrm_req_drop(bp, req); 1084 - return -EPERM; 1085 - } 1086 1085 1087 1086 for (i = 0; i < ARRAY_SIZE(nvm_params); i++) { 1088 1087 nvm_param = &nvm_params[i];

+44 -1

drivers/net/ethernet/broadcom/bnxt/bnxt_ethtool.c

··· 4399 4399 return 0; 4400 4400 } 4401 4401 4402 + static int bnxt_hwrm_pfcwd_qcfg(struct bnxt *bp, u16 *val) 4403 + { 4404 + struct hwrm_queue_pfcwd_timeout_qcfg_output *resp; 4405 + struct hwrm_queue_pfcwd_timeout_qcfg_input *req; 4406 + int rc; 4407 + 4408 + rc = hwrm_req_init(bp, req, HWRM_QUEUE_PFCWD_TIMEOUT_QCFG); 4409 + if (rc) 4410 + return rc; 4411 + resp = hwrm_req_hold(bp, req); 4412 + rc = hwrm_req_send(bp, req); 4413 + if (!rc) 4414 + *val = le16_to_cpu(resp->pfcwd_timeout_value); 4415 + hwrm_req_drop(bp, req); 4416 + return rc; 4417 + } 4418 + 4419 + static int bnxt_hwrm_pfcwd_cfg(struct bnxt *bp, u16 val) 4420 + { 4421 + struct hwrm_queue_pfcwd_timeout_cfg_input *req; 4422 + int rc; 4423 + 4424 + rc = hwrm_req_init(bp, req, HWRM_QUEUE_PFCWD_TIMEOUT_CFG); 4425 + if (rc) 4426 + return rc; 4427 + req->pfcwd_timeout_value = cpu_to_le16(val); 4428 + rc = hwrm_req_send(bp, req); 4429 + return rc; 4430 + } 4431 + 4402 4432 static int bnxt_set_tunable(struct net_device *dev, 4403 4433 const struct ethtool_tunable *tuna, 4404 4434 const void *data) 4405 4435 { 4406 4436 struct bnxt *bp = netdev_priv(dev); 4407 - u32 rx_copybreak; 4437 + u32 rx_copybreak, val; 4408 4438 4409 4439 switch (tuna->id) { 4410 4440 case ETHTOOL_RX_COPYBREAK: ··· 4447 4417 bp->rx_copybreak = rx_copybreak; 4448 4418 } 4449 4419 return 0; 4420 + case ETHTOOL_PFC_PREVENTION_TOUT: 4421 + if (BNXT_VF(bp) || !bp->max_pfcwd_tmo_ms) 4422 + return -EOPNOTSUPP; 4423 + 4424 + val = *(u16 *)data; 4425 + if (val > bp->max_pfcwd_tmo_ms && 4426 + val != PFC_STORM_PREVENTION_AUTO) 4427 + return -EINVAL; 4428 + return bnxt_hwrm_pfcwd_cfg(bp, val); 4450 4429 default: 4451 4430 return -EOPNOTSUPP; 4452 4431 } ··· 4470 4431 case ETHTOOL_RX_COPYBREAK: 4471 4432 *(u32 *)data = bp->rx_copybreak; 4472 4433 break; 4434 + case ETHTOOL_PFC_PREVENTION_TOUT: 4435 + if (!bp->max_pfcwd_tmo_ms) 4436 + return -EOPNOTSUPP; 4437 + return bnxt_hwrm_pfcwd_qcfg(bp, data); 4473 4438 default: 4474 4439 return -EOPNOTSUPP; 4475 4440 }

+18 -3

drivers/net/ethernet/broadcom/bnxt/bnxt_sriov.c

··· 541 541 if (rc) 542 542 goto err; 543 543 544 + /* In case of VF Dynamic resource allocation, driver will provision 545 + * maximum resources to all the VFs. FW will dynamically allocate 546 + * resources to VFs on the fly, so always divide the resources by 1. 547 + */ 548 + if (BNXT_ROCE_VF_DYN_ALLOC_CAP(bp)) 549 + num_vfs = 1; 550 + 544 551 cfg_req->fid = cpu_to_le16(0xffff); 545 552 cfg_req->enables2 = 546 553 cpu_to_le32(FUNC_CFG_REQ_ENABLES2_ROCE_MAX_AV_PER_VF | ··· 741 734 FUNC_CFG_REQ_ENABLES_NUM_VNICS | 742 735 FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS); 743 736 744 - mtu = bp->dev->mtu + ETH_HLEN + VLAN_HLEN; 737 + mtu = bp->dev->mtu + VLAN_ETH_HLEN; 745 738 req->mru = cpu_to_le16(mtu); 746 739 req->admin_mtu = cpu_to_le16(mtu); 747 740 ··· 926 919 return rc; 927 920 } 928 921 929 - void bnxt_sriov_disable(struct bnxt *bp) 922 + void __bnxt_sriov_disable(struct bnxt *bp) 930 923 { 931 924 u16 num_vfs = pci_num_vf(bp->pdev); 932 925 ··· 950 943 devl_unlock(bp->dl); 951 944 952 945 bnxt_free_vf_resources(bp); 946 + } 947 + 948 + static void bnxt_sriov_disable(struct bnxt *bp) 949 + { 950 + if (!pci_num_vf(bp->pdev)) 951 + return; 952 + 953 + __bnxt_sriov_disable(bp); 953 954 954 955 /* Reclaim all resources for the PF. */ 955 956 rtnl_lock(); ··· 1336 1321 return 0; 1337 1322 } 1338 1323 1339 - void bnxt_sriov_disable(struct bnxt *bp) 1324 + void __bnxt_sriov_disable(struct bnxt *bp) 1340 1325 { 1341 1326 } 1342 1327

+1 -1

drivers/net/ethernet/broadcom/bnxt/bnxt_sriov.h

··· 38 38 int bnxt_set_vf_trust(struct net_device *dev, int vf_id, bool trust); 39 39 int bnxt_sriov_configure(struct pci_dev *pdev, int num_vfs); 40 40 int bnxt_cfg_hw_sriov(struct bnxt *bp, int *num_vfs, bool reset); 41 - void bnxt_sriov_disable(struct bnxt *); 41 + void __bnxt_sriov_disable(struct bnxt *bp); 42 42 void bnxt_hwrm_exec_fwd_req(struct bnxt *); 43 43 void bnxt_update_vf_mac(struct bnxt *); 44 44 int bnxt_approve_mac(struct bnxt *, const u8 *, bool);

+61

include/linux/bnxt/hsi.h

··· 6751 6751 u8 valid; 6752 6752 }; 6753 6753 6754 + /* hwrm_queue_pfcwd_timeout_qcaps_input (size:128b/16B) */ 6755 + struct hwrm_queue_pfcwd_timeout_qcaps_input { 6756 + __le16 req_type; 6757 + __le16 cmpl_ring; 6758 + __le16 seq_id; 6759 + __le16 target_id; 6760 + __le64 resp_addr; 6761 + }; 6762 + 6763 + /* hwrm_queue_pfcwd_timeout_qcaps_output (size:128b/16B) */ 6764 + struct hwrm_queue_pfcwd_timeout_qcaps_output { 6765 + __le16 error_code; 6766 + __le16 req_type; 6767 + __le16 seq_id; 6768 + __le16 resp_len; 6769 + __le16 max_pfcwd_timeout; 6770 + u8 unused_0[5]; 6771 + u8 valid; 6772 + }; 6773 + 6774 + /* hwrm_queue_pfcwd_timeout_cfg_input (size:192b/24B) */ 6775 + struct hwrm_queue_pfcwd_timeout_cfg_input { 6776 + __le16 req_type; 6777 + __le16 cmpl_ring; 6778 + __le16 seq_id; 6779 + __le16 target_id; 6780 + __le64 resp_addr; 6781 + __le16 pfcwd_timeout_value; 6782 + u8 unused_0[6]; 6783 + }; 6784 + 6785 + /* hwrm_queue_pfcwd_timeout_cfg_output (size:128b/16B) */ 6786 + struct hwrm_queue_pfcwd_timeout_cfg_output { 6787 + __le16 error_code; 6788 + __le16 req_type; 6789 + __le16 seq_id; 6790 + __le16 resp_len; 6791 + u8 unused_0[7]; 6792 + u8 valid; 6793 + }; 6794 + 6795 + /* hwrm_queue_pfcwd_timeout_qcfg_input (size:128b/16B) */ 6796 + struct hwrm_queue_pfcwd_timeout_qcfg_input { 6797 + __le16 req_type; 6798 + __le16 cmpl_ring; 6799 + __le16 seq_id; 6800 + __le16 target_id; 6801 + __le64 resp_addr; 6802 + }; 6803 + 6804 + /* hwrm_queue_pfcwd_timeout_qcfg_output (size:128b/16B) */ 6805 + struct hwrm_queue_pfcwd_timeout_qcfg_output { 6806 + __le16 error_code; 6807 + __le16 req_type; 6808 + __le16 seq_id; 6809 + __le16 resp_len; 6810 + __le16 pfcwd_timeout_value; 6811 + u8 unused_0[5]; 6812 + u8 valid; 6813 + }; 6814 + 6754 6815 /* hwrm_vnic_alloc_input (size:192b/24B) */ 6755 6816 struct hwrm_vnic_alloc_input { 6756 6817 __le16 req_type;

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