Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC fixes from Olof Johansson:
"A set of fixes for ARM platforms for 3.12. Among them:
- A fix for build breakage in the MTD subsystem for some PXA devices.
David Woodhouse has this patch in his for-next branch but has not
been responding to our requests to send it up so here it is. I
should have amended the commit message to describe the build
failure for CONFIG_OF=n setups, but forgot and now it's down in the
stack of commits.
- Added device-tree for the BeagleBone Black. Turns out people have
been using the older "regualar" bone DT for the newer boards, and
there's risk of damaging hardware that way.
- Misc DT and regular fixes for OMAP.
- Fix to make the ST-Ericsson "snowball" boards boot with
multi_v7_defconfig, and enable one of the ST-E reference boards on
the same config.
- Kconfig cleanup for u300 to hide submenus when the platform isn't
enabled.
- Enable ARM_ATAG_DTB_COMPAT to let firmware override command line
when booting with an appended devicetree on non-DT-enabled firmware
(needed to boot snowball)"
* tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (26 commits)
ARM: multi_v7: add HREFv60 to multi_v7 defconfig
ARM: OMAP2+: mux: fix trivial typo in name
ARM: OMAP4 SMP: Corrected a typo fucntions to functions
ARM: OMAP4: cpuidle: fix: call cpu_cluster_pm_exit conditionally
mailbox: remove unnecessary platform_set_drvdata()
ARM: mach-omap2: gpmc: Fix warning when CONFIG_ARM_LPAE=y
ARM: OMAP: fix return value check in omap_device_build_from_dt()
ARM: OMAP4: Fix clock_get error for GPMC during boot
ARM: sa1100: collie.c: fall back to jedec_probe flash detection
ARM: u300: hide submenus
ARM: dts: igep00x0: Add pinmux configuration for MCBSP2
ARM: dts: Fix muxing and regulator for wl12xx on the SDIO bus for blaze
ARM: dts: Fix muxing and regulator for wl12xx on the SDIO bus for pandaboard
mtd: nand: pxa3xx: Remove unneeded ifdef CONFIG_OF
ARM: multi_v7_defconfig: enable ARM_ATAG_DTB_COMPAT
ARM: ux500: disable outer cache debug
ARM: dts: OMAP5: fix ocp2scp DTS data
ARM: dts: OMAP5: fix reg property size
ARM: dts: am335x-bone*: add DT for BeagleBone Black
ARM: dts: omap3-beagle-xm: fix string error in compatible property
...
+418
-289
+1
arch/arm/boot/dts/Makefile
+1
arch/arm/boot/dts/Makefile
+262
arch/arm/boot/dts/am335x-bone-common.dtsi
+262
arch/arm/boot/dts/am335x-bone-common.dtsi
···
1
+
/*
2
+
* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
3
+
*
4
+
* This program is free software; you can redistribute it and/or modify
5
+
* it under the terms of the GNU General Public License version 2 as
6
+
* published by the Free Software Foundation.
7
+
*/
8
+
9
+
/ {
10
+
model = "TI AM335x BeagleBone";
11
+
compatible = "ti,am335x-bone", "ti,am33xx";
12
+
13
+
cpus {
14
+
cpu@0 {
15
+
cpu0-supply = <&dcdc2_reg>;
16
+
};
17
+
};
18
+
19
+
memory {
20
+
device_type = "memory";
21
+
reg = <0x80000000 0x10000000>; /* 256 MB */
22
+
};
23
+
24
+
am33xx_pinmux: pinmux@44e10800 {
25
+
pinctrl-names = "default";
26
+
pinctrl-0 = <&clkout2_pin>;
27
+
28
+
user_leds_s0: user_leds_s0 {
29
+
pinctrl-single,pins = <
30
+
0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a5.gpio1_21 */
31
+
0x58 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a6.gpio1_22 */
32
+
0x5c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a7.gpio1_23 */
33
+
0x60 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a8.gpio1_24 */
34
+
>;
35
+
};
36
+
37
+
i2c0_pins: pinmux_i2c0_pins {
38
+
pinctrl-single,pins = <
39
+
0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */
40
+
0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */
41
+
>;
42
+
};
43
+
44
+
uart0_pins: pinmux_uart0_pins {
45
+
pinctrl-single,pins = <
46
+
0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
47
+
0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
48
+
>;
49
+
};
50
+
51
+
clkout2_pin: pinmux_clkout2_pin {
52
+
pinctrl-single,pins = <
53
+
0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */
54
+
>;
55
+
};
56
+
57
+
cpsw_default: cpsw_default {
58
+
pinctrl-single,pins = <
59
+
/* Slave 1 */
60
+
0x110 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxerr.mii1_rxerr */
61
+
0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txen.mii1_txen */
62
+
0x118 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxdv.mii1_rxdv */
63
+
0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd3.mii1_txd3 */
64
+
0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd2.mii1_txd2 */
65
+
0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd1.mii1_txd1 */
66
+
0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd0.mii1_txd0 */
67
+
0x12c (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_txclk.mii1_txclk */
68
+
0x130 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxclk.mii1_rxclk */
69
+
0x134 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd3.mii1_rxd3 */
70
+
0x138 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd2.mii1_rxd2 */
71
+
0x13c (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd1.mii1_rxd1 */
72
+
0x140 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd0.mii1_rxd0 */
73
+
>;
74
+
};
75
+
76
+
cpsw_sleep: cpsw_sleep {
77
+
pinctrl-single,pins = <
78
+
/* Slave 1 reset value */
79
+
0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7)
80
+
0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
81
+
0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
82
+
0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
83
+
0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
84
+
0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
85
+
0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
86
+
0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
87
+
0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
88
+
0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
89
+
0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
90
+
0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
91
+
0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
92
+
>;
93
+
};
94
+
95
+
davinci_mdio_default: davinci_mdio_default {
96
+
pinctrl-single,pins = <
97
+
/* MDIO */
98
+
0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
99
+
0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
100
+
>;
101
+
};
102
+
103
+
davinci_mdio_sleep: davinci_mdio_sleep {
104
+
pinctrl-single,pins = <
105
+
/* MDIO reset value */
106
+
0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
107
+
0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
108
+
>;
109
+
};
110
+
};
111
+
112
+
ocp {
113
+
uart0: serial@44e09000 {
114
+
pinctrl-names = "default";
115
+
pinctrl-0 = <&uart0_pins>;
116
+
117
+
status = "okay";
118
+
};
119
+
120
+
musb: usb@47400000 {
121
+
status = "okay";
122
+
123
+
control@44e10000 {
124
+
status = "okay";
125
+
};
126
+
127
+
usb-phy@47401300 {
128
+
status = "okay";
129
+
};
130
+
131
+
usb-phy@47401b00 {
132
+
status = "okay";
133
+
};
134
+
135
+
usb@47401000 {
136
+
status = "okay";
137
+
};
138
+
139
+
usb@47401800 {
140
+
status = "okay";
141
+
dr_mode = "host";
142
+
};
143
+
144
+
dma-controller@07402000 {
145
+
status = "okay";
146
+
};
147
+
};
148
+
149
+
i2c0: i2c@44e0b000 {
150
+
pinctrl-names = "default";
151
+
pinctrl-0 = <&i2c0_pins>;
152
+
153
+
status = "okay";
154
+
clock-frequency = <400000>;
155
+
156
+
tps: tps@24 {
157
+
reg = <0x24>;
158
+
};
159
+
160
+
};
161
+
};
162
+
163
+
leds {
164
+
pinctrl-names = "default";
165
+
pinctrl-0 = <&user_leds_s0>;
166
+
167
+
compatible = "gpio-leds";
168
+
169
+
led@2 {
170
+
label = "beaglebone:green:heartbeat";
171
+
gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>;
172
+
linux,default-trigger = "heartbeat";
173
+
default-state = "off";
174
+
};
175
+
176
+
led@3 {
177
+
label = "beaglebone:green:mmc0";
178
+
gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>;
179
+
linux,default-trigger = "mmc0";
180
+
default-state = "off";
181
+
};
182
+
183
+
led@4 {
184
+
label = "beaglebone:green:usr2";
185
+
gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>;
186
+
default-state = "off";
187
+
};
188
+
189
+
led@5 {
190
+
label = "beaglebone:green:usr3";
191
+
gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>;
192
+
default-state = "off";
193
+
};
194
+
};
195
+
};
196
+
197
+
/include/ "tps65217.dtsi"
198
+
199
+
&tps {
200
+
regulators {
201
+
dcdc1_reg: regulator@0 {
202
+
regulator-always-on;
203
+
};
204
+
205
+
dcdc2_reg: regulator@1 {
206
+
/* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
207
+
regulator-name = "vdd_mpu";
208
+
regulator-min-microvolt = <925000>;
209
+
regulator-max-microvolt = <1325000>;
210
+
regulator-boot-on;
211
+
regulator-always-on;
212
+
};
213
+
214
+
dcdc3_reg: regulator@2 {
215
+
/* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
216
+
regulator-name = "vdd_core";
217
+
regulator-min-microvolt = <925000>;
218
+
regulator-max-microvolt = <1150000>;
219
+
regulator-boot-on;
220
+
regulator-always-on;
221
+
};
222
+
223
+
ldo1_reg: regulator@3 {
224
+
regulator-always-on;
225
+
};
226
+
227
+
ldo2_reg: regulator@4 {
228
+
regulator-always-on;
229
+
};
230
+
231
+
ldo3_reg: regulator@5 {
232
+
regulator-always-on;
233
+
};
234
+
235
+
ldo4_reg: regulator@6 {
236
+
regulator-always-on;
237
+
};
238
+
};
239
+
};
240
+
241
+
&cpsw_emac0 {
242
+
phy_id = <&davinci_mdio>, <0>;
243
+
phy-mode = "mii";
244
+
};
245
+
246
+
&cpsw_emac1 {
247
+
phy_id = <&davinci_mdio>, <1>;
248
+
phy-mode = "mii";
249
+
};
250
+
251
+
&mac {
252
+
pinctrl-names = "default", "sleep";
253
+
pinctrl-0 = <&cpsw_default>;
254
+
pinctrl-1 = <&cpsw_sleep>;
255
+
256
+
};
257
+
258
+
&davinci_mdio {
259
+
pinctrl-names = "default", "sleep";
260
+
pinctrl-0 = <&davinci_mdio_default>;
261
+
pinctrl-1 = <&davinci_mdio_sleep>;
262
+
};
+1
-255
arch/arm/boot/dts/am335x-bone.dts
+1
-255
arch/arm/boot/dts/am335x-bone.dts
···
8
8
/dts-v1/;
9
9
10
10
#include "am33xx.dtsi"
11
-
12
-
/ {
13
-
model = "TI AM335x BeagleBone";
14
-
compatible = "ti,am335x-bone", "ti,am33xx";
15
-
16
-
cpus {
17
-
cpu@0 {
18
-
cpu0-supply = <&dcdc2_reg>;
19
-
};
20
-
};
21
-
22
-
memory {
23
-
device_type = "memory";
24
-
reg = <0x80000000 0x10000000>; /* 256 MB */
25
-
};
26
-
27
-
am33xx_pinmux: pinmux@44e10800 {
28
-
pinctrl-names = "default";
29
-
pinctrl-0 = <&clkout2_pin>;
30
-
31
-
user_leds_s0: user_leds_s0 {
32
-
pinctrl-single,pins = <
33
-
0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a5.gpio1_21 */
34
-
0x58 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a6.gpio1_22 */
35
-
0x5c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a7.gpio1_23 */
36
-
0x60 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a8.gpio1_24 */
37
-
>;
38
-
};
39
-
40
-
i2c0_pins: pinmux_i2c0_pins {
41
-
pinctrl-single,pins = <
42
-
0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */
43
-
0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */
44
-
>;
45
-
};
46
-
47
-
uart0_pins: pinmux_uart0_pins {
48
-
pinctrl-single,pins = <
49
-
0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
50
-
0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
51
-
>;
52
-
};
53
-
54
-
clkout2_pin: pinmux_clkout2_pin {
55
-
pinctrl-single,pins = <
56
-
0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */
57
-
>;
58
-
};
59
-
60
-
cpsw_default: cpsw_default {
61
-
pinctrl-single,pins = <
62
-
/* Slave 1 */
63
-
0x110 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxerr.mii1_rxerr */
64
-
0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txen.mii1_txen */
65
-
0x118 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxdv.mii1_rxdv */
66
-
0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd3.mii1_txd3 */
67
-
0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd2.mii1_txd2 */
68
-
0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd1.mii1_txd1 */
69
-
0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd0.mii1_txd0 */
70
-
0x12c (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_txclk.mii1_txclk */
71
-
0x130 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxclk.mii1_rxclk */
72
-
0x134 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd3.mii1_rxd3 */
73
-
0x138 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd2.mii1_rxd2 */
74
-
0x13c (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd1.mii1_rxd1 */
75
-
0x140 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd0.mii1_rxd0 */
76
-
>;
77
-
};
78
-
79
-
cpsw_sleep: cpsw_sleep {
80
-
pinctrl-single,pins = <
81
-
/* Slave 1 reset value */
82
-
0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7)
83
-
0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
84
-
0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
85
-
0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
86
-
0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
87
-
0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
88
-
0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
89
-
0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
90
-
0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
91
-
0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
92
-
0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
93
-
0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
94
-
0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
95
-
>;
96
-
};
97
-
98
-
davinci_mdio_default: davinci_mdio_default {
99
-
pinctrl-single,pins = <
100
-
/* MDIO */
101
-
0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
102
-
0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
103
-
>;
104
-
};
105
-
106
-
davinci_mdio_sleep: davinci_mdio_sleep {
107
-
pinctrl-single,pins = <
108
-
/* MDIO reset value */
109
-
0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
110
-
0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
111
-
>;
112
-
};
113
-
};
114
-
115
-
ocp {
116
-
uart0: serial@44e09000 {
117
-
pinctrl-names = "default";
118
-
pinctrl-0 = <&uart0_pins>;
119
-
120
-
status = "okay";
121
-
};
122
-
123
-
musb: usb@47400000 {
124
-
status = "okay";
125
-
126
-
control@44e10000 {
127
-
status = "okay";
128
-
};
129
-
130
-
usb-phy@47401300 {
131
-
status = "okay";
132
-
};
133
-
134
-
usb-phy@47401b00 {
135
-
status = "okay";
136
-
};
137
-
138
-
usb@47401000 {
139
-
status = "okay";
140
-
};
141
-
142
-
usb@47401800 {
143
-
status = "okay";
144
-
dr_mode = "host";
145
-
};
146
-
147
-
dma-controller@07402000 {
148
-
status = "okay";
149
-
};
150
-
};
151
-
152
-
i2c0: i2c@44e0b000 {
153
-
pinctrl-names = "default";
154
-
pinctrl-0 = <&i2c0_pins>;
155
-
156
-
status = "okay";
157
-
clock-frequency = <400000>;
158
-
159
-
tps: tps@24 {
160
-
reg = <0x24>;
161
-
};
162
-
163
-
};
164
-
};
165
-
166
-
leds {
167
-
pinctrl-names = "default";
168
-
pinctrl-0 = <&user_leds_s0>;
169
-
170
-
compatible = "gpio-leds";
171
-
172
-
led@2 {
173
-
label = "beaglebone:green:heartbeat";
174
-
gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>;
175
-
linux,default-trigger = "heartbeat";
176
-
default-state = "off";
177
-
};
178
-
179
-
led@3 {
180
-
label = "beaglebone:green:mmc0";
181
-
gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>;
182
-
linux,default-trigger = "mmc0";
183
-
default-state = "off";
184
-
};
185
-
186
-
led@4 {
187
-
label = "beaglebone:green:usr2";
188
-
gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>;
189
-
default-state = "off";
190
-
};
191
-
192
-
led@5 {
193
-
label = "beaglebone:green:usr3";
194
-
gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>;
195
-
default-state = "off";
196
-
};
197
-
};
198
-
};
199
-
200
-
/include/ "tps65217.dtsi"
201
-
202
-
&tps {
203
-
regulators {
204
-
dcdc1_reg: regulator@0 {
205
-
regulator-always-on;
206
-
};
207
-
208
-
dcdc2_reg: regulator@1 {
209
-
/* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
210
-
regulator-name = "vdd_mpu";
211
-
regulator-min-microvolt = <925000>;
212
-
regulator-max-microvolt = <1325000>;
213
-
regulator-boot-on;
214
-
regulator-always-on;
215
-
};
216
-
217
-
dcdc3_reg: regulator@2 {
218
-
/* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
219
-
regulator-name = "vdd_core";
220
-
regulator-min-microvolt = <925000>;
221
-
regulator-max-microvolt = <1150000>;
222
-
regulator-boot-on;
223
-
regulator-always-on;
224
-
};
225
-
226
-
ldo1_reg: regulator@3 {
227
-
regulator-always-on;
228
-
};
229
-
230
-
ldo2_reg: regulator@4 {
231
-
regulator-always-on;
232
-
};
233
-
234
-
ldo3_reg: regulator@5 {
235
-
regulator-always-on;
236
-
};
237
-
238
-
ldo4_reg: regulator@6 {
239
-
regulator-always-on;
240
-
};
241
-
};
242
-
};
243
-
244
-
&cpsw_emac0 {
245
-
phy_id = <&davinci_mdio>, <0>;
246
-
phy-mode = "mii";
247
-
};
248
-
249
-
&cpsw_emac1 {
250
-
phy_id = <&davinci_mdio>, <1>;
251
-
phy-mode = "mii";
252
-
};
253
-
254
-
&mac {
255
-
pinctrl-names = "default", "sleep";
256
-
pinctrl-0 = <&cpsw_default>;
257
-
pinctrl-1 = <&cpsw_sleep>;
258
-
259
-
};
260
-
261
-
&davinci_mdio {
262
-
pinctrl-names = "default", "sleep";
263
-
pinctrl-0 = <&davinci_mdio_default>;
264
-
pinctrl-1 = <&davinci_mdio_sleep>;
265
-
};
11
+
#include "am335x-bone-common.dtsi"
+17
arch/arm/boot/dts/am335x-boneblack.dts
+17
arch/arm/boot/dts/am335x-boneblack.dts
···
1
+
/*
2
+
* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
3
+
*
4
+
* This program is free software; you can redistribute it and/or modify
5
+
* it under the terms of the GNU General Public License version 2 as
6
+
* published by the Free Software Foundation.
7
+
*/
8
+
/dts-v1/;
9
+
10
+
#include "am33xx.dtsi"
11
+
#include "am335x-bone-common.dtsi"
12
+
13
+
&ldo3_reg {
14
+
regulator-min-microvolt = <1800000>;
15
+
regulator-max-microvolt = <1800000>;
16
+
regulator-always-on;
17
+
};
+3
-3
arch/arm/boot/dts/imx27.dtsi
+3
-3
arch/arm/boot/dts/imx27.dtsi
···
187
187
compatible = "fsl,imx27-cspi";
188
188
reg = <0x1000e000 0x1000>;
189
189
interrupts = <16>;
190
-
clocks = <&clks 53>, <&clks 53>;
190
+
clocks = <&clks 53>, <&clks 60>;
191
191
clock-names = "ipg", "per";
192
192
status = "disabled";
193
193
};
···
198
198
compatible = "fsl,imx27-cspi";
199
199
reg = <0x1000f000 0x1000>;
200
200
interrupts = <15>;
201
-
clocks = <&clks 52>, <&clks 52>;
201
+
clocks = <&clks 52>, <&clks 60>;
202
202
clock-names = "ipg", "per";
203
203
status = "disabled";
204
204
};
···
309
309
compatible = "fsl,imx27-cspi";
310
310
reg = <0x10017000 0x1000>;
311
311
interrupts = <6>;
312
-
clocks = <&clks 51>, <&clks 51>;
312
+
clocks = <&clks 51>, <&clks 60>;
313
313
clock-names = "ipg", "per";
314
314
status = "disabled";
315
315
};
+1
-1
arch/arm/boot/dts/imx51.dtsi
+1
-1
arch/arm/boot/dts/imx51.dtsi
+2
-2
arch/arm/boot/dts/imx6q-pinfunc.h
+2
-2
arch/arm/boot/dts/imx6q-pinfunc.h
···
207
207
#define MX6QDL_PAD_EIM_D29__ECSPI4_SS0 0x0c8 0x3dc 0x824 0x2 0x1
208
208
#define MX6QDL_PAD_EIM_D29__UART2_RTS_B 0x0c8 0x3dc 0x924 0x4 0x1
209
209
#define MX6QDL_PAD_EIM_D29__UART2_CTS_B 0x0c8 0x3dc 0x000 0x4 0x0
210
-
#define MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x0c4 0x3dc 0x000 0x4 0x0
211
-
#define MX6QDL_PAD_EIM_D29__UART2_DTE_CTS_B 0x0c4 0x3dc 0x924 0x4 0x1
210
+
#define MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x0c8 0x3dc 0x000 0x4 0x0
211
+
#define MX6QDL_PAD_EIM_D29__UART2_DTE_CTS_B 0x0c8 0x3dc 0x924 0x4 0x1
212
212
#define MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x0c8 0x3dc 0x000 0x5 0x0
213
213
#define MX6QDL_PAD_EIM_D29__IPU2_CSI1_VSYNC 0x0c8 0x3dc 0x8e4 0x6 0x0
214
214
#define MX6QDL_PAD_EIM_D29__IPU1_DI0_PIN14 0x0c8 0x3dc 0x000 0x7 0x0
+1
-1
arch/arm/boot/dts/omap3-beagle-xm.dts
+1
-1
arch/arm/boot/dts/omap3-beagle-xm.dts
+14
arch/arm/boot/dts/omap3-igep.dtsi
+14
arch/arm/boot/dts/omap3-igep.dtsi
···
48
48
>;
49
49
};
50
50
51
+
mcbsp2_pins: pinmux_mcbsp2_pins {
52
+
pinctrl-single,pins = <
53
+
0x10c (PIN_INPUT | MUX_MODE0) /* mcbsp2_fsx.mcbsp2_fsx */
54
+
0x10e (PIN_INPUT | MUX_MODE0) /* mcbsp2_clkx.mcbsp2_clkx */
55
+
0x110 (PIN_INPUT | MUX_MODE0) /* mcbsp2_dr.mcbsp2.dr */
56
+
0x112 (PIN_OUTPUT | MUX_MODE0) /* mcbsp2_dx.mcbsp2_dx */
57
+
>;
58
+
};
59
+
51
60
mmc1_pins: pinmux_mmc1_pins {
52
61
pinctrl-single,pins = <
53
62
0x114 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */
···
100
91
101
92
&i2c2 {
102
93
clock-frequency = <400000>;
94
+
};
95
+
96
+
&mcbsp2 {
97
+
pinctrl-names = "default";
98
+
pinctrl-0 = <&mcbsp2_pins>;
103
99
};
104
100
105
101
&mmc1 {
+45
-1
arch/arm/boot/dts/omap4-panda-common.dtsi
+45
-1
arch/arm/boot/dts/omap4-panda-common.dtsi
···
107
107
*/
108
108
clock-frequency = <19200000>;
109
109
};
110
+
111
+
/* regulator for wl12xx on sdio5 */
112
+
wl12xx_vmmc: wl12xx_vmmc {
113
+
pinctrl-names = "default";
114
+
pinctrl-0 = <&wl12xx_gpio>;
115
+
compatible = "regulator-fixed";
116
+
regulator-name = "vwl1271";
117
+
regulator-min-microvolt = <1800000>;
118
+
regulator-max-microvolt = <1800000>;
119
+
gpio = <&gpio2 11 0>;
120
+
startup-delay-us = <70000>;
121
+
enable-active-high;
122
+
};
110
123
};
111
124
112
125
&omap4_pmx_wkup {
···
248
235
0x1c (PIN_OUTPUT | MUX_MODE3) /* gpio_wk8 */
249
236
>;
250
237
};
238
+
239
+
/*
240
+
* wl12xx GPIO outputs for WLAN_EN, BT_EN, FM_EN, BT_WAKEUP
241
+
* REVISIT: Are the pull-ups needed for GPIO 48 and 49?
242
+
*/
243
+
wl12xx_gpio: pinmux_wl12xx_gpio {
244
+
pinctrl-single,pins = <
245
+
0x26 (PIN_OUTPUT | MUX_MODE3) /* gpmc_a19.gpio_43 */
246
+
0x2c (PIN_OUTPUT | MUX_MODE3) /* gpmc_a22.gpio_46 */
247
+
0x30 (PIN_OUTPUT_PULLUP | MUX_MODE3) /* gpmc_a24.gpio_48 */
248
+
0x32 (PIN_OUTPUT_PULLUP | MUX_MODE3) /* gpmc_a25.gpio_49 */
249
+
>;
250
+
};
251
+
252
+
/* wl12xx GPIO inputs and SDIO pins */
253
+
wl12xx_pins: pinmux_wl12xx_pins {
254
+
pinctrl-single,pins = <
255
+
0x38 (PIN_INPUT | MUX_MODE3) /* gpmc_ncs2.gpio_52 */
256
+
0x3a (PIN_INPUT | MUX_MODE3) /* gpmc_ncs3.gpio_53 */
257
+
0x108 (PIN_OUTPUT | MUX_MODE0) /* sdmmc5_clk.sdmmc5_clk */
258
+
0x10a (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_cmd.sdmmc5_cmd */
259
+
0x10c (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat0.sdmmc5_dat0 */
260
+
0x10e (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat1.sdmmc5_dat1 */
261
+
0x110 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat2.sdmmc5_dat2 */
262
+
0x112 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat3.sdmmc5_dat3 */
263
+
>;
264
+
};
251
265
};
252
266
253
267
&i2c1 {
···
354
314
};
355
315
356
316
&mmc5 {
357
-
ti,non-removable;
317
+
pinctrl-names = "default";
318
+
pinctrl-0 = <&wl12xx_pins>;
319
+
vmmc-supply = <&wl12xx_vmmc>;
320
+
non-removable;
358
321
bus-width = <4>;
322
+
cap-power-off-card;
359
323
};
360
324
361
325
&emif1 {
+38
-1
arch/arm/boot/dts/omap4-sdp.dts
+38
-1
arch/arm/boot/dts/omap4-sdp.dts
···
140
140
"DMic", "Digital Mic",
141
141
"Digital Mic", "Digital Mic1 Bias";
142
142
};
143
+
144
+
/* regulator for wl12xx on sdio5 */
145
+
wl12xx_vmmc: wl12xx_vmmc {
146
+
pinctrl-names = "default";
147
+
pinctrl-0 = <&wl12xx_gpio>;
148
+
compatible = "regulator-fixed";
149
+
regulator-name = "vwl1271";
150
+
regulator-min-microvolt = <1800000>;
151
+
regulator-max-microvolt = <1800000>;
152
+
gpio = <&gpio2 22 0>;
153
+
startup-delay-us = <70000>;
154
+
enable-active-high;
155
+
};
143
156
};
144
157
145
158
&omap4_pmx_wkup {
···
308
295
0xf0 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_sda */
309
296
>;
310
297
};
298
+
299
+
/* wl12xx GPIO output for WLAN_EN */
300
+
wl12xx_gpio: pinmux_wl12xx_gpio {
301
+
pinctrl-single,pins = <
302
+
0x3c (PIN_OUTPUT | MUX_MODE3) /* gpmc_nwp.gpio_54 */
303
+
>;
304
+
};
305
+
306
+
/* wl12xx GPIO inputs and SDIO pins */
307
+
wl12xx_pins: pinmux_wl12xx_pins {
308
+
pinctrl-single,pins = <
309
+
0x3a (PIN_INPUT | MUX_MODE3) /* gpmc_ncs3.gpio_53 */
310
+
0x108 (PIN_OUTPUT | MUX_MODE3) /* sdmmc5_clk.sdmmc5_clk */
311
+
0x10a (PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc5_cmd.sdmmc5_cmd */
312
+
0x10c (PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc5_dat0.sdmmc5_dat0 */
313
+
0x10e (PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc5_dat1.sdmmc5_dat1 */
314
+
0x110 (PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc5_dat2.sdmmc5_dat2 */
315
+
0x112 (PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc5_dat3.sdmmc5_dat3 */
316
+
>;
317
+
};
311
318
};
312
319
313
320
&i2c1 {
···
453
420
};
454
421
455
422
&mmc5 {
423
+
pinctrl-names = "default";
424
+
pinctrl-0 = <&wl12xx_pins>;
425
+
vmmc-supply = <&wl12xx_vmmc>;
426
+
non-removable;
456
427
bus-width = <4>;
457
-
ti,non-removable;
428
+
cap-power-off-card;
458
429
};
459
430
460
431
&emif1 {
+4
-3
arch/arm/boot/dts/omap5.dtsi
+4
-3
arch/arm/boot/dts/omap5.dtsi
···
637
637
omap_dwc3@4a020000 {
638
638
compatible = "ti,dwc3";
639
639
ti,hwmods = "usb_otg_ss";
640
-
reg = <0x4a020000 0x1000>;
640
+
reg = <0x4a020000 0x10000>;
641
641
interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
642
642
#address-cells = <1>;
643
643
#size-cells = <1>;
···
645
645
ranges;
646
646
dwc3@4a030000 {
647
647
compatible = "snps,dwc3";
648
-
reg = <0x4a030000 0x1000>;
648
+
reg = <0x4a030000 0x10000>;
649
649
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
650
650
usb-phy = <&usb2_phy>, <&usb3_phy>;
651
651
tx-fifo-resize;
652
652
};
653
653
};
654
654
655
-
ocp2scp {
655
+
ocp2scp@4a080000 {
656
656
compatible = "ti,omap-ocp2scp";
657
657
#address-cells = <1>;
658
658
#size-cells = <1>;
659
+
reg = <0x4a080000 0x20>;
659
660
ranges;
660
661
ti,hwmods = "ocp2scp1";
661
662
usb2_phy: usb2phy@4a084000 {
+2
arch/arm/configs/multi_v7_defconfig
+2
arch/arm/configs/multi_v7_defconfig
···
36
36
CONFIG_TEGRA_PCI=y
37
37
CONFIG_TEGRA_EMC_SCALING_ENABLE=y
38
38
CONFIG_ARCH_U8500=y
39
+
CONFIG_MACH_HREFV60=y
39
40
CONFIG_MACH_SNOWBALL=y
40
41
CONFIG_MACH_UX500_DT=y
41
42
CONFIG_ARCH_VEXPRESS=y
···
47
46
CONFIG_SMP=y
48
47
CONFIG_HIGHPTE=y
49
48
CONFIG_ARM_APPENDED_DTB=y
49
+
CONFIG_ARM_ATAG_DTB_COMPAT=y
50
50
CONFIG_NET=y
51
51
CONFIG_UNIX=y
52
52
CONFIG_INET=y
+1
arch/arm/mach-imx/clk-fixup-mux.c
+1
arch/arm/mach-imx/clk-fixup-mux.c
+1
-1
arch/arm/mach-imx/clk-imx51-imx53.c
+1
-1
arch/arm/mach-imx/clk-imx51-imx53.c
···
397
397
mx51_spdif_xtal_sel, ARRAY_SIZE(mx51_spdif_xtal_sel));
398
398
clk[spdif1_sel] = imx_clk_mux("spdif1_sel", MXC_CCM_CSCMR2, 2, 2,
399
399
spdif_sel, ARRAY_SIZE(spdif_sel));
400
-
clk[spdif1_pred] = imx_clk_divider("spdif1_podf", "spdif1_sel", MXC_CCM_CDCDR, 16, 3);
400
+
clk[spdif1_pred] = imx_clk_divider("spdif1_pred", "spdif1_sel", MXC_CCM_CDCDR, 16, 3);
401
401
clk[spdif1_podf] = imx_clk_divider("spdif1_podf", "spdif1_pred", MXC_CCM_CDCDR, 9, 6);
402
402
clk[spdif1_com_sel] = imx_clk_mux("spdif1_com_sel", MXC_CCM_CSCMR2, 5, 1,
403
403
mx51_spdif1_com_sel, ARRAY_SIZE(mx51_spdif1_com_sel));
+11
arch/arm/mach-imx/system.c
+11
arch/arm/mach-imx/system.c
···
117
117
/* Configure the L2 PREFETCH and POWER registers */
118
118
val = readl_relaxed(l2x0_base + L2X0_PREFETCH_CTRL);
119
119
val |= 0x70800000;
120
+
/*
121
+
* The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0
122
+
* The L2 cache controller(PL310) version on the i.MX6DL/SOLO/SL is r3p2
123
+
* But according to ARM PL310 errata: 752271
124
+
* ID: 752271: Double linefill feature can cause data corruption
125
+
* Fault Status: Present in: r3p0, r3p1, r3p1-50rel0. Fixed in r3p2
126
+
* Workaround: The only workaround to this erratum is to disable the
127
+
* double linefill feature. This is the default behavior.
128
+
*/
129
+
if (cpu_is_imx6q())
130
+
val &= ~(1 << 30 | 1 << 23);
120
131
writel_relaxed(val, l2x0_base + L2X0_PREFETCH_CTRL);
121
132
val = L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN;
122
133
writel_relaxed(val, l2x0_base + L2X0_POWER_CTRL);
+1
-1
arch/arm/mach-omap2/cclock44xx_data.c
+1
-1
arch/arm/mach-omap2/cclock44xx_data.c
···
1632
1632
CLK(NULL, "auxclk5_src_ck", &auxclk5_src_ck),
1633
1633
CLK(NULL, "auxclk5_ck", &auxclk5_ck),
1634
1634
CLK(NULL, "auxclkreq5_ck", &auxclkreq5_ck),
1635
-
CLK("omap-gpmc", "fck", &dummy_ck),
1635
+
CLK("50000000.gpmc", "fck", &dummy_ck),
1636
1636
CLK("omap_i2c.1", "ick", &dummy_ck),
1637
1637
CLK("omap_i2c.2", "ick", &dummy_ck),
1638
1638
CLK("omap_i2c.3", "ick", &dummy_ck),
+1
-1
arch/arm/mach-omap2/cpuidle44xx.c
+1
-1
arch/arm/mach-omap2/cpuidle44xx.c
···
143
143
* Call idle CPU cluster PM exit notifier chain
144
144
* to restore GIC and wakeupgen context.
145
145
*/
146
-
if ((cx->mpu_state == PWRDM_POWER_RET) &&
146
+
if (dev->cpu == 0 && (cx->mpu_state == PWRDM_POWER_RET) &&
147
147
(cx->mpu_logic_state == PWRDM_POWER_OFF))
148
148
cpu_cluster_pm_exit();
149
149
+2
-2
arch/arm/mach-omap2/gpmc.c
+2
-2
arch/arm/mach-omap2/gpmc.c
···
1491
1491
*/
1492
1492
ret = gpmc_cs_remap(cs, res.start);
1493
1493
if (ret < 0) {
1494
-
dev_err(&pdev->dev, "cannot remap GPMC CS %d to 0x%x\n",
1495
-
cs, res.start);
1494
+
dev_err(&pdev->dev, "cannot remap GPMC CS %d to %pa\n",
1495
+
cs, &res.start);
1496
1496
goto err;
1497
1497
}
1498
1498
+1
-1
arch/arm/mach-omap2/mux34xx.c
+1
-1
arch/arm/mach-omap2/mux34xx.c
···
620
620
"uart1_rts", "ssi1_flag_tx", NULL, NULL,
621
621
"gpio_149", NULL, NULL, "safe_mode"),
622
622
_OMAP3_MUXENTRY(UART1_RX, 151,
623
-
"uart1_rx", "ss1_wake_tx", "mcbsp1_clkr", "mcspi4_clk",
623
+
"uart1_rx", "ssi1_wake_tx", "mcbsp1_clkr", "mcspi4_clk",
624
624
"gpio_151", NULL, NULL, "safe_mode"),
625
625
_OMAP3_MUXENTRY(UART1_TX, 148,
626
626
"uart1_tx", "ssi1_dat_tx", NULL, NULL,
+1
-1
arch/arm/mach-omap2/omap-smp.c
+1
-1
arch/arm/mach-omap2/omap-smp.c
+1
-1
arch/arm/mach-omap2/omap_device.c
+1
-1
arch/arm/mach-omap2/omap_device.c
+1
-1
arch/arm/mach-sa1100/collie.c
+1
-1
arch/arm/mach-sa1100/collie.c
+5
-5
arch/arm/mach-u300/Kconfig
+5
-5
arch/arm/mach-u300/Kconfig
···
1
-
menu "ST-Ericsson AB U300/U335 Platform"
2
-
3
-
comment "ST-Ericsson Mobile Platform Products"
4
-
5
1
config ARCH_U300
6
2
bool "ST-Ericsson U300 Series" if ARCH_MULTI_V5
7
3
depends on MMU
···
21
25
help
22
26
Support for ST-Ericsson U300 series mobile platforms.
23
27
24
-
comment "ST-Ericsson U300/U335 Feature Selections"
28
+
if ARCH_U300
29
+
30
+
menu "ST-Ericsson AB U300/U335 Platform"
25
31
26
32
config MACH_U300
27
33
depends on ARCH_U300
···
51
53
SPI framework and ARM PL022 support.
52
54
53
55
endmenu
56
+
57
+
endif
+1
arch/arm/mach-ux500/cache-l2x0.c
+1
arch/arm/mach-ux500/cache-l2x0.c
-1
drivers/mailbox/mailbox-omap2.c
-1
drivers/mailbox/mailbox-omap2.c
-7
drivers/mtd/nand/pxa3xx_nand.c
-7
drivers/mtd/nand/pxa3xx_nand.c
···
1236
1236
return 0;
1237
1237
}
1238
1238
1239
-
#ifdef CONFIG_OF
1240
1239
static struct of_device_id pxa3xx_nand_dt_ids[] = {
1241
1240
{
1242
1241
.compatible = "marvell,pxa3xx-nand",
···
1283
1284
1284
1285
return 0;
1285
1286
}
1286
-
#else
1287
-
static inline int pxa3xx_nand_probe_dt(struct platform_device *pdev)
1288
-
{
1289
-
return 0;
1290
-
}
1291
-
#endif
1292
1287
1293
1288
static int pxa3xx_nand_probe(struct platform_device *pdev)
1294
1289
{