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arm64: dts: qcom: ipq8074: fix Gen3 PCIe QMP PHY

IPQ8074 comes in 2 silicon versions:
* v1 with 2x Gen2 PCIe ports and QMP PHY-s
* v2 with 1x Gen3 and 1x Gen2 PCIe ports and QMP PHY-s

v2 is the final and production version that is actually supported by the
kernel, however it looks like PCIe related nodes were added for the v1 SoC.

Now that we have Gen3 QMP PHY support, we can start fixing the PCIe support
by fixing the Gen3 QMP PHY node first.

Change the compatible to the Gen3 QMP PHY, correct the register space start
and size, add the missing misc PCS register space.

Fixes: 33057e1672fe ("ARM: dts: ipq8074: Add pcie nodes")
Signed-off-by: Robert Marko <robimarko@gmail.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230113164449.906002-2-robimarko@gmail.com

authored by

Robert Marko and committed by
Bjorn Andersson
7ba33591 100d9c94

+8 -7
+8 -7
arch/arm64/boot/dts/qcom/ipq8074.dtsi
··· 197 197 status = "disabled"; 198 198 }; 199 199 200 - pcie_qmp0: phy@86000 { 201 - compatible = "qcom,ipq8074-qmp-pcie-phy"; 202 - reg = <0x00086000 0x1c4>; 200 + pcie_qmp0: phy@84000 { 201 + compatible = "qcom,ipq8074-qmp-gen3-pcie-phy"; 202 + reg = <0x00084000 0x1bc>; 203 203 #address-cells = <1>; 204 204 #size-cells = <1>; 205 205 ranges; ··· 213 213 "common"; 214 214 status = "disabled"; 215 215 216 - pcie_phy0: phy@86200 { 217 - reg = <0x86200 0x16c>, 218 - <0x86400 0x200>, 219 - <0x86800 0x4f4>; 216 + pcie_phy0: phy@84200 { 217 + reg = <0x84200 0x16c>, 218 + <0x84400 0x200>, 219 + <0x84800 0x1f0>, 220 + <0x84c00 0xf4>; 220 221 #phy-cells = <0>; 221 222 #clock-cells = <0>; 222 223 clocks = <&gcc GCC_PCIE0_PIPE_CLK>;