Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
1
fork

Configure Feed

Select the types of activity you want to include in your feed.

phy: rockchip: naneng-combphy: Enable U3 OTG port for RK3568

The boot firmware may disable the U3 port early during boot and leave it
up to the controller or PHY driver to re-enable U3 when needed.

The Rockchip USBDP PHY driver currently does this for RK3576 and RK3588,
something the Rockchip Naneng Combo PHY driver never does for RK3568.
This may result in USB 3.0 ports being limited to only using USB 2.0 or
in special cases not working at all on RK3568.

Write to PIPE_GRF USB3OTGx_CON1 reg to ensure the U3 port is enabled
when a PHY with PHY_TYPE_USB3 mode is used.

Fixes: 7160820d742a ("phy: rockchip: add naneng combo phy for RK3568")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Link: https://lore.kernel.org/r/20250723072324.2246498-1-jonas@kwiboo.se
Signed-off-by: Vinod Koul <vkoul@kernel.org>

authored by

Jonas Karlman and committed by
Vinod Koul
7bb14b61 8209b3f7

+12
+12
drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
··· 137 137 struct combphy_reg pipe_xpcs_phy_ready; 138 138 struct combphy_reg pipe_pcie1l0_sel; 139 139 struct combphy_reg pipe_pcie1l1_sel; 140 + struct combphy_reg u3otg0_port_en; 141 + struct combphy_reg u3otg1_port_en; 140 142 }; 141 143 142 144 struct rockchip_combphy_cfg { ··· 596 594 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); 597 595 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); 598 596 rockchip_combphy_param_write(priv->phy_grf, &cfg->usb_mode_set, true); 597 + switch (priv->id) { 598 + case 0: 599 + rockchip_combphy_param_write(priv->pipe_grf, &cfg->u3otg0_port_en, true); 600 + break; 601 + case 1: 602 + rockchip_combphy_param_write(priv->pipe_grf, &cfg->u3otg1_port_en, true); 603 + break; 604 + } 599 605 break; 600 606 601 607 case PHY_TYPE_SATA: ··· 747 737 /* pipe-grf */ 748 738 .pipe_con0_for_sata = { 0x0000, 15, 0, 0x00, 0x2220 }, 749 739 .pipe_xpcs_phy_ready = { 0x0040, 2, 2, 0x00, 0x01 }, 740 + .u3otg0_port_en = { 0x0104, 15, 0, 0x0181, 0x1100 }, 741 + .u3otg1_port_en = { 0x0144, 15, 0, 0x0181, 0x1100 }, 750 742 }; 751 743 752 744 static const struct rockchip_combphy_cfg rk3568_combphy_cfgs = {