Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'powerpc-6.6-2' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux
Pull powerpc fixes from Michael Ellerman:
- A fix for breakpoint handling which was using get_user() while atomic
- Fix the Power10 HASHCHK handler which was using get_user() while
atomic
- A few build fixes for issues caused by recent changes
Thanks to Benjamin Gray, Christophe Leroy, Kajol Jain, and Naveen N Rao.
* tag 'powerpc-6.6-2' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux:
powerpc/dexcr: Move HASHCHK trap handler
powerpc/82xx: Select FSL_SOC
powerpc: Fix build issue with LD_DEAD_CODE_DATA_ELIMINATION and FTRACE_MCOUNT_USE_PATCHABLE_FUNCTION_ENTRY
powerpc/watchpoints: Annotate atomic context in more places
powerpc/watchpoint: Disable pagefaults when getting user instruction
powerpc/watchpoints: Disable preemption in thread_change_pc()
powerpc/perf/hv-24x7: Update domain value check
+60
-26
+1
-1
arch/powerpc/Kconfig
+1
-1
arch/powerpc/Kconfig
···
255
255
select HAVE_KPROBES
256
256
select HAVE_KPROBES_ON_FTRACE
257
257
select HAVE_KRETPROBES
258
-
select HAVE_LD_DEAD_CODE_DATA_ELIMINATION if HAVE_OBJTOOL_MCOUNT
258
+
select HAVE_LD_DEAD_CODE_DATA_ELIMINATION if HAVE_OBJTOOL_MCOUNT && (!ARCH_USING_PATCHABLE_FUNCTION_ENTRY || (!CC_IS_GCC || GCC_VERSION >= 110100))
259
259
select HAVE_LIVEPATCH if HAVE_DYNAMIC_FTRACE_WITH_REGS
260
260
select HAVE_MOD_ARCH_SPECIFIC
261
261
select HAVE_NMI if PERF_EVENTS || (PPC64 && PPC_BOOK3S)
+15
-1
arch/powerpc/kernel/hw_breakpoint.c
+15
-1
arch/powerpc/kernel/hw_breakpoint.c
···
230
230
struct arch_hw_breakpoint *info;
231
231
int i;
232
232
233
+
preempt_disable();
234
+
233
235
for (i = 0; i < nr_wp_slots(); i++) {
234
236
struct perf_event *bp = __this_cpu_read(bp_per_reg[i]);
235
237
236
238
if (unlikely(bp && counter_arch_bp(bp)->perf_single_step))
237
239
goto reset;
238
240
}
239
-
return;
241
+
goto out;
240
242
241
243
reset:
242
244
regs_set_return_msr(regs, regs->msr & ~MSR_SE);
···
247
245
__set_breakpoint(i, info);
248
246
info->perf_single_step = false;
249
247
}
248
+
249
+
out:
250
+
preempt_enable();
250
251
}
251
252
252
253
static bool is_larx_stcx_instr(int type)
···
368
363
}
369
364
}
370
365
366
+
/*
367
+
* Handle a DABR or DAWR exception.
368
+
*
369
+
* Called in atomic context.
370
+
*/
371
371
int hw_breakpoint_handler(struct die_args *args)
372
372
{
373
373
bool err = false;
···
500
490
501
491
/*
502
492
* Handle single-step exceptions following a DABR hit.
493
+
*
494
+
* Called in atomic context.
503
495
*/
504
496
static int single_step_dabr_instruction(struct die_args *args)
505
497
{
···
553
541
554
542
/*
555
543
* Handle debug exception notifications.
544
+
*
545
+
* Called in atomic context.
556
546
*/
557
547
int hw_breakpoint_exceptions_notify(
558
548
struct notifier_block *unused, unsigned long val, void *data)
+6
-1
arch/powerpc/kernel/hw_breakpoint_constraints.c
+6
-1
arch/powerpc/kernel/hw_breakpoint_constraints.c
···
131
131
int *type, int *size, unsigned long *ea)
132
132
{
133
133
struct instruction_op op;
134
+
int err;
134
135
135
-
if (__get_user_instr(*instr, (void __user *)regs->nip))
136
+
pagefault_disable();
137
+
err = __get_user_instr(*instr, (void __user *)regs->nip);
138
+
pagefault_enable();
139
+
140
+
if (err)
136
141
return;
137
142
138
143
analyse_instr(&op, regs, *instr);
+36
-20
arch/powerpc/kernel/traps.c
+36
-20
arch/powerpc/kernel/traps.c
···
1512
1512
return;
1513
1513
}
1514
1514
1515
-
if (cpu_has_feature(CPU_FTR_DEXCR_NPHIE) && user_mode(regs)) {
1516
-
ppc_inst_t insn;
1517
-
1518
-
if (get_user_instr(insn, (void __user *)regs->nip)) {
1519
-
_exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip);
1520
-
return;
1521
-
}
1522
-
1523
-
if (ppc_inst_primary_opcode(insn) == 31 &&
1524
-
get_xop(ppc_inst_val(insn)) == OP_31_XOP_HASHCHK) {
1525
-
_exception(SIGILL, regs, ILL_ILLOPN, regs->nip);
1526
-
return;
1527
-
}
1515
+
/* User mode considers other cases after enabling IRQs */
1516
+
if (!user_mode(regs)) {
1517
+
_exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip);
1518
+
return;
1528
1519
}
1529
-
1530
-
_exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip);
1531
-
return;
1532
1520
}
1533
1521
#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1534
1522
if (reason & REASON_TM) {
···
1549
1561
1550
1562
/*
1551
1563
* If we took the program check in the kernel skip down to sending a
1552
-
* SIGILL. The subsequent cases all relate to emulating instructions
1553
-
* which we should only do for userspace. We also do not want to enable
1554
-
* interrupts for kernel faults because that might lead to further
1555
-
* faults, and loose the context of the original exception.
1564
+
* SIGILL. The subsequent cases all relate to user space, such as
1565
+
* emulating instructions which we should only do for user space. We
1566
+
* also do not want to enable interrupts for kernel faults because that
1567
+
* might lead to further faults, and loose the context of the original
1568
+
* exception.
1556
1569
*/
1557
1570
if (!user_mode(regs))
1558
1571
goto sigill;
1559
1572
1560
1573
interrupt_cond_local_irq_enable(regs);
1574
+
1575
+
/*
1576
+
* (reason & REASON_TRAP) is mostly handled before enabling IRQs,
1577
+
* except get_user_instr() can sleep so we cannot reliably inspect the
1578
+
* current instruction in that context. Now that we know we are
1579
+
* handling a user space trap and can sleep, we can check if the trap
1580
+
* was a hashchk failure.
1581
+
*/
1582
+
if (reason & REASON_TRAP) {
1583
+
if (cpu_has_feature(CPU_FTR_DEXCR_NPHIE)) {
1584
+
ppc_inst_t insn;
1585
+
1586
+
if (get_user_instr(insn, (void __user *)regs->nip)) {
1587
+
_exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip);
1588
+
return;
1589
+
}
1590
+
1591
+
if (ppc_inst_primary_opcode(insn) == 31 &&
1592
+
get_xop(ppc_inst_val(insn)) == OP_31_XOP_HASHCHK) {
1593
+
_exception(SIGILL, regs, ILL_ILLOPN, regs->nip);
1594
+
return;
1595
+
}
1596
+
}
1597
+
1598
+
_exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip);
1599
+
return;
1600
+
}
1561
1601
1562
1602
/* (reason & REASON_ILLEGAL) would be the obvious thing here,
1563
1603
* but there seems to be a hardware bug on the 405GP (RevD)
+1
-1
arch/powerpc/perf/hv-24x7.c
+1
-1
arch/powerpc/perf/hv-24x7.c
+1
-2
arch/powerpc/platforms/82xx/Kconfig
+1
-2
arch/powerpc/platforms/82xx/Kconfig
···
2
2
menuconfig PPC_82xx
3
3
bool "82xx-based boards (PQ II)"
4
4
depends on PPC_BOOK3S_32
5
+
select FSL_SOC
5
6
6
7
if PPC_82xx
7
8
···
10
9
bool "Embedded Planet EP8248E (a.k.a. CWH-PPC-8248N-VE)"
11
10
select CPM2
12
11
select PPC_INDIRECT_PCI if PCI
13
-
select FSL_SOC
14
12
select PHYLIB if NETDEVICES
15
13
select MDIO_BITBANG if PHYLIB
16
14
help
···
22
22
bool "Keymile MGCOGE"
23
23
select CPM2
24
24
select PPC_INDIRECT_PCI if PCI
25
-
select FSL_SOC
26
25
help
27
26
This enables support for the Keymile MGCOGE board.
28
27