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clk: qcom: gcc-qcm2290: Mark RCGs shared where applicable

The vast majority of shared RCGs were not marked as such. Fix it.

Fixes: 496d1a13d405 ("clk: qcom: Add Global Clock Controller driver for QCM2290")
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230403174807.345185-1-konrad.dybcio@linaro.org

authored by

Konrad Dybcio and committed by
Bjorn Andersson 7bf654a0 f53153a3

+31 -31
+31 -31
drivers/clk/qcom/gcc-qcm2290.c
··· 650 650 .name = "gcc_usb30_prim_mock_utmi_clk_src", 651 651 .parent_data = gcc_parents_0, 652 652 .num_parents = ARRAY_SIZE(gcc_parents_0), 653 - .ops = &clk_rcg2_ops, 653 + .ops = &clk_rcg2_shared_ops, 654 654 }, 655 655 }; 656 656 ··· 686 686 .name = "gcc_camss_axi_clk_src", 687 687 .parent_data = gcc_parents_4, 688 688 .num_parents = ARRAY_SIZE(gcc_parents_4), 689 - .ops = &clk_rcg2_ops, 689 + .ops = &clk_rcg2_shared_ops, 690 690 }, 691 691 }; 692 692 ··· 706 706 .name = "gcc_camss_cci_clk_src", 707 707 .parent_data = gcc_parents_9, 708 708 .num_parents = ARRAY_SIZE(gcc_parents_9), 709 - .ops = &clk_rcg2_ops, 709 + .ops = &clk_rcg2_shared_ops, 710 710 }, 711 711 }; 712 712 ··· 728 728 .name = "gcc_camss_csi0phytimer_clk_src", 729 729 .parent_data = gcc_parents_5, 730 730 .num_parents = ARRAY_SIZE(gcc_parents_5), 731 - .ops = &clk_rcg2_ops, 731 + .ops = &clk_rcg2_shared_ops, 732 732 }, 733 733 }; 734 734 ··· 742 742 .name = "gcc_camss_csi1phytimer_clk_src", 743 743 .parent_data = gcc_parents_5, 744 744 .num_parents = ARRAY_SIZE(gcc_parents_5), 745 - .ops = &clk_rcg2_ops, 745 + .ops = &clk_rcg2_shared_ops, 746 746 }, 747 747 }; 748 748 ··· 764 764 .parent_data = gcc_parents_3, 765 765 .num_parents = ARRAY_SIZE(gcc_parents_3), 766 766 .flags = CLK_OPS_PARENT_ENABLE, 767 - .ops = &clk_rcg2_ops, 767 + .ops = &clk_rcg2_shared_ops, 768 768 }, 769 769 }; 770 770 ··· 779 779 .parent_data = gcc_parents_3, 780 780 .num_parents = ARRAY_SIZE(gcc_parents_3), 781 781 .flags = CLK_OPS_PARENT_ENABLE, 782 - .ops = &clk_rcg2_ops, 782 + .ops = &clk_rcg2_shared_ops, 783 783 }, 784 784 }; 785 785 ··· 794 794 .parent_data = gcc_parents_3, 795 795 .num_parents = ARRAY_SIZE(gcc_parents_3), 796 796 .flags = CLK_OPS_PARENT_ENABLE, 797 - .ops = &clk_rcg2_ops, 797 + .ops = &clk_rcg2_shared_ops, 798 798 }, 799 799 }; 800 800 ··· 809 809 .parent_data = gcc_parents_3, 810 810 .num_parents = ARRAY_SIZE(gcc_parents_3), 811 811 .flags = CLK_OPS_PARENT_ENABLE, 812 - .ops = &clk_rcg2_ops, 812 + .ops = &clk_rcg2_shared_ops, 813 813 }, 814 814 }; 815 815 ··· 830 830 .name = "gcc_camss_ope_ahb_clk_src", 831 831 .parent_data = gcc_parents_6, 832 832 .num_parents = ARRAY_SIZE(gcc_parents_6), 833 - .ops = &clk_rcg2_ops, 833 + .ops = &clk_rcg2_shared_ops, 834 834 }, 835 835 }; 836 836 ··· 854 854 .parent_data = gcc_parents_6, 855 855 .num_parents = ARRAY_SIZE(gcc_parents_6), 856 856 .flags = CLK_SET_RATE_PARENT, 857 - .ops = &clk_rcg2_ops, 857 + .ops = &clk_rcg2_shared_ops, 858 858 }, 859 859 }; 860 860 ··· 888 888 .name = "gcc_camss_tfe_0_clk_src", 889 889 .parent_data = gcc_parents_7, 890 890 .num_parents = ARRAY_SIZE(gcc_parents_7), 891 - .ops = &clk_rcg2_ops, 891 + .ops = &clk_rcg2_shared_ops, 892 892 }, 893 893 }; 894 894 ··· 912 912 .name = "gcc_camss_tfe_0_csid_clk_src", 913 913 .parent_data = gcc_parents_8, 914 914 .num_parents = ARRAY_SIZE(gcc_parents_8), 915 - .ops = &clk_rcg2_ops, 915 + .ops = &clk_rcg2_shared_ops, 916 916 }, 917 917 }; 918 918 ··· 926 926 .name = "gcc_camss_tfe_1_clk_src", 927 927 .parent_data = gcc_parents_7, 928 928 .num_parents = ARRAY_SIZE(gcc_parents_7), 929 - .ops = &clk_rcg2_ops, 929 + .ops = &clk_rcg2_shared_ops, 930 930 }, 931 931 }; 932 932 ··· 940 940 .name = "gcc_camss_tfe_1_csid_clk_src", 941 941 .parent_data = gcc_parents_8, 942 942 .num_parents = ARRAY_SIZE(gcc_parents_8), 943 - .ops = &clk_rcg2_ops, 943 + .ops = &clk_rcg2_shared_ops, 944 944 }, 945 945 }; 946 946 ··· 963 963 .parent_data = gcc_parents_10, 964 964 .num_parents = ARRAY_SIZE(gcc_parents_10), 965 965 .flags = CLK_OPS_PARENT_ENABLE, 966 - .ops = &clk_rcg2_ops, 966 + .ops = &clk_rcg2_shared_ops, 967 967 }, 968 968 }; 969 969 ··· 984 984 .name = "gcc_camss_top_ahb_clk_src", 985 985 .parent_data = gcc_parents_4, 986 986 .num_parents = ARRAY_SIZE(gcc_parents_4), 987 - .ops = &clk_rcg2_ops, 987 + .ops = &clk_rcg2_shared_ops, 988 988 }, 989 989 }; 990 990 ··· 1006 1006 .name = "gcc_gp1_clk_src", 1007 1007 .parent_data = gcc_parents_2, 1008 1008 .num_parents = ARRAY_SIZE(gcc_parents_2), 1009 - .ops = &clk_rcg2_ops, 1009 + .ops = &clk_rcg2_shared_ops, 1010 1010 }, 1011 1011 }; 1012 1012 ··· 1020 1020 .name = "gcc_gp2_clk_src", 1021 1021 .parent_data = gcc_parents_2, 1022 1022 .num_parents = ARRAY_SIZE(gcc_parents_2), 1023 - .ops = &clk_rcg2_ops, 1023 + .ops = &clk_rcg2_shared_ops, 1024 1024 }, 1025 1025 }; 1026 1026 ··· 1034 1034 .name = "gcc_gp3_clk_src", 1035 1035 .parent_data = gcc_parents_2, 1036 1036 .num_parents = ARRAY_SIZE(gcc_parents_2), 1037 - .ops = &clk_rcg2_ops, 1037 + .ops = &clk_rcg2_shared_ops, 1038 1038 }, 1039 1039 }; 1040 1040 ··· 1054 1054 .name = "gcc_pdm2_clk_src", 1055 1055 .parent_data = gcc_parents_0, 1056 1056 .num_parents = ARRAY_SIZE(gcc_parents_0), 1057 - .ops = &clk_rcg2_ops, 1057 + .ops = &clk_rcg2_shared_ops, 1058 1058 }, 1059 1059 }; 1060 1060 ··· 1082 1082 .name = "gcc_qupv3_wrap0_s0_clk_src", 1083 1083 .parent_data = gcc_parents_1, 1084 1084 .num_parents = ARRAY_SIZE(gcc_parents_1), 1085 - .ops = &clk_rcg2_ops, 1085 + .ops = &clk_rcg2_shared_ops, 1086 1086 }; 1087 1087 1088 1088 static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = { ··· 1098 1098 .name = "gcc_qupv3_wrap0_s1_clk_src", 1099 1099 .parent_data = gcc_parents_1, 1100 1100 .num_parents = ARRAY_SIZE(gcc_parents_1), 1101 - .ops = &clk_rcg2_ops, 1101 + .ops = &clk_rcg2_shared_ops, 1102 1102 }; 1103 1103 1104 1104 static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = { ··· 1114 1114 .name = "gcc_qupv3_wrap0_s2_clk_src", 1115 1115 .parent_data = gcc_parents_1, 1116 1116 .num_parents = ARRAY_SIZE(gcc_parents_1), 1117 - .ops = &clk_rcg2_ops, 1117 + .ops = &clk_rcg2_shared_ops, 1118 1118 }; 1119 1119 1120 1120 static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = { ··· 1130 1130 .name = "gcc_qupv3_wrap0_s3_clk_src", 1131 1131 .parent_data = gcc_parents_1, 1132 1132 .num_parents = ARRAY_SIZE(gcc_parents_1), 1133 - .ops = &clk_rcg2_ops, 1133 + .ops = &clk_rcg2_shared_ops, 1134 1134 }; 1135 1135 1136 1136 static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = { ··· 1146 1146 .name = "gcc_qupv3_wrap0_s4_clk_src", 1147 1147 .parent_data = gcc_parents_1, 1148 1148 .num_parents = ARRAY_SIZE(gcc_parents_1), 1149 - .ops = &clk_rcg2_ops, 1149 + .ops = &clk_rcg2_shared_ops, 1150 1150 }; 1151 1151 1152 1152 static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = { ··· 1162 1162 .name = "gcc_qupv3_wrap0_s5_clk_src", 1163 1163 .parent_data = gcc_parents_1, 1164 1164 .num_parents = ARRAY_SIZE(gcc_parents_1), 1165 - .ops = &clk_rcg2_ops, 1165 + .ops = &clk_rcg2_shared_ops, 1166 1166 }; 1167 1167 1168 1168 static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = { ··· 1219 1219 .name = "gcc_sdcc1_ice_core_clk_src", 1220 1220 .parent_data = gcc_parents_0, 1221 1221 .num_parents = ARRAY_SIZE(gcc_parents_0), 1222 - .ops = &clk_rcg2_ops, 1222 + .ops = &clk_rcg2_shared_ops, 1223 1223 }, 1224 1224 }; 1225 1225 ··· 1266 1266 .name = "gcc_usb30_prim_master_clk_src", 1267 1267 .parent_data = gcc_parents_0, 1268 1268 .num_parents = ARRAY_SIZE(gcc_parents_0), 1269 - .ops = &clk_rcg2_ops, 1269 + .ops = &clk_rcg2_shared_ops, 1270 1270 }, 1271 1271 }; 1272 1272 ··· 1280 1280 .name = "gcc_usb3_prim_phy_aux_clk_src", 1281 1281 .parent_data = gcc_parents_13, 1282 1282 .num_parents = ARRAY_SIZE(gcc_parents_13), 1283 - .ops = &clk_rcg2_ops, 1283 + .ops = &clk_rcg2_shared_ops, 1284 1284 }, 1285 1285 }; 1286 1286 ··· 1303 1303 .parent_data = gcc_parents_14, 1304 1304 .num_parents = ARRAY_SIZE(gcc_parents_14), 1305 1305 .flags = CLK_SET_RATE_PARENT, 1306 - .ops = &clk_rcg2_ops, 1306 + .ops = &clk_rcg2_shared_ops, 1307 1307 }, 1308 1308 }; 1309 1309