tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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ASoC: rt1321: Add RT1321 amplifier support

This patch supported RT1321 amplifier.

Signed-off-by: Shuming Fan <shumingf@realtek.com>
Link: https://patch.msgid.link/20250814092153.2733592-1-shumingf@realtek.com
Signed-off-by: Mark Brown <broonie@kernel.org>

authored by

Shuming Fan and committed by
Mark Brown 7bf9e646 0e62438e

+343 -47
+333 -47
sound/soc/codecs/rt1320-sdw.c
··· 255 255 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x03 }, 256 256 }; 257 257 258 + static const struct reg_sequence rt1321_blind_write[] = { 259 + { 0x0000c003, 0xf0 }, 260 + { 0x0000c01b, 0xfc }, 261 + { 0x0000c5c3, 0xf2 }, 262 + { 0x0000c5c2, 0x00 }, 263 + { 0x0000c5c1, 0x10 }, 264 + { 0x0000c5c0, 0x04 }, 265 + { 0x0000c5c7, 0x03 }, 266 + { 0x0000c5c6, 0x10 }, 267 + { 0x0000c526, 0x47 }, 268 + { 0x0000c5c4, 0x12 }, 269 + { 0x0000c5c5, 0x60 }, 270 + { 0x0000c520, 0x10 }, 271 + { 0x0000c521, 0x32 }, 272 + { 0x0000c5c7, 0x00 }, 273 + { 0x0000c5c8, 0x03 }, 274 + { 0x0000c5d3, 0x08 }, 275 + { 0x0000c5d2, 0x0a }, 276 + { 0x0000c5d1, 0x49 }, 277 + { 0x0000c5d0, 0x0f }, 278 + { 0x0000c580, 0x10 }, 279 + { 0x0000c581, 0x32 }, 280 + { 0x0000c582, 0x01 }, 281 + { 0x0000cb00, 0x03 }, 282 + { 0x0000cb02, 0x52 }, 283 + { 0x0000cb04, 0x80 }, 284 + { 0x0000cb0b, 0x01 }, 285 + { 0x0000c682, 0x60 }, 286 + { 0x0000c019, 0x10 }, 287 + { 0x0000c5f0, 0x01 }, 288 + { 0x0000c5f7, 0x22 }, 289 + { 0x0000c5f6, 0x22 }, 290 + { 0x0000c057, 0x51 }, 291 + { 0x0000c054, 0x55 }, 292 + { 0x0000c053, 0x55 }, 293 + { 0x0000c052, 0x55 }, 294 + { 0x0000c051, 0x01 }, 295 + { 0x0000c050, 0x15 }, 296 + { 0x0000c060, 0x99 }, 297 + { 0x0000c030, 0x55 }, 298 + { 0x0000c061, 0x55 }, 299 + { 0x0000c063, 0x55 }, 300 + { 0x0000c065, 0xa5 }, 301 + { 0x0000c06b, 0x0a }, 302 + { 0x0000ca05, 0xd6 }, 303 + { 0x0000ca07, 0x07 }, 304 + { 0x0000ca25, 0xd6 }, 305 + { 0x0000ca27, 0x07 }, 306 + { 0x0000cd00, 0x05 }, 307 + { 0x0000c604, 0x40 }, 308 + { 0x0000c609, 0x40 }, 309 + { 0x0000c046, 0xf7 }, 310 + { 0x0000c045, 0xff }, 311 + { 0x0000c044, 0xff }, 312 + { 0x0000c043, 0xff }, 313 + { 0x0000c042, 0xff }, 314 + { 0x0000c041, 0xff }, 315 + { 0x0000c040, 0xff }, 316 + { 0x0000c049, 0xff }, 317 + { 0x0000c028, 0x3f }, 318 + { 0x0000c020, 0x3f }, 319 + { 0x0000c032, 0x13 }, 320 + { 0x0000c033, 0x01 }, 321 + { 0x0000cc10, 0x01 }, 322 + { 0x0000dc20, 0x03 }, 323 + { 0x0000de03, 0x05 }, 324 + { 0x0000dc00, 0x00 }, 325 + { 0x0000c700, 0xf0 }, 326 + { 0x0000c701, 0x13 }, 327 + { 0x0000c900, 0xc3 }, 328 + { 0x0000c570, 0x08 }, 329 + { 0x0000c086, 0x02 }, 330 + { 0x0000c085, 0x7f }, 331 + { 0x0000c084, 0x00 }, 332 + { 0x0000c081, 0xff }, 333 + { 0x0000f084, 0x0f }, 334 + { 0x0000f083, 0xff }, 335 + { 0x0000f082, 0xff }, 336 + { 0x0000f081, 0xff }, 337 + { 0x0000f080, 0xff }, 338 + { 0x20003003, 0x3f }, 339 + { 0x20005818, 0x81 }, 340 + { 0x20009018, 0x81 }, 341 + { 0x2000301c, 0x81 }, 342 + { 0x0000c003, 0xc0 }, 343 + { 0x0000c047, 0x80 }, 344 + { 0x0000d541, 0x80 }, 345 + { 0x0000d487, 0x0b }, 346 + { 0x0000d487, 0x3b }, 347 + { 0x0000d486, 0xc3 }, 348 + { 0x0000d470, 0x89 }, 349 + { 0x0000d471, 0x3a }, 350 + { 0x0000d472, 0x1d }, 351 + { 0x0000d478, 0xff }, 352 + { 0x0000d479, 0x20 }, 353 + { 0x0000d47a, 0x10 }, 354 + { 0x0000d73c, 0xb7 }, 355 + { 0x0000d73d, 0xd7 }, 356 + { 0x0000d73e, 0x00 }, 357 + { 0x0000d73f, 0x10 }, 358 + { 0x3fc2dfc3, 0x00 }, 359 + { 0x3fc2dfc2, 0x00 }, 360 + { 0x3fc2dfc1, 0x00 }, 361 + { 0x3fc2dfc0, 0x07 }, 362 + { 0x3fc2dfc7, 0x00 }, 363 + { 0x3fc2dfc6, 0x00 }, 364 + { 0x3fc2dfc5, 0x00 }, 365 + { 0x3fc2dfc4, 0x01 }, 366 + { 0x3fc2df83, 0x00 }, 367 + { 0x3fc2df82, 0x00 }, 368 + { 0x3fc2df81, 0x00 }, 369 + { 0x3fc2df80, 0x00 }, 370 + { 0x0000d541, 0x40 }, 371 + { 0x0000d486, 0x43 }, 372 + { 0x1000db00, 0x03 }, 373 + { 0x1000db01, 0x00 }, 374 + { 0x1000db02, 0x10 }, 375 + { 0x1000db03, 0x00 }, 376 + { 0x1000db04, 0x00 }, 377 + { 0x1000db05, 0x45 }, 378 + { 0x1000db06, 0x12 }, 379 + { 0x1000db07, 0x09 }, 380 + { 0x1000db08, 0x00 }, 381 + { 0x1000db09, 0x00 }, 382 + { 0x1000db0a, 0x00 }, 383 + { 0x1000db0b, 0x13 }, 384 + { 0x1000db0c, 0x09 }, 385 + { 0x1000db0d, 0x00 }, 386 + { 0x1000db0e, 0x00 }, 387 + { 0x1000db0f, 0x00 }, 388 + { 0x0000d540, 0x21 }, 389 + { 0x41000189, 0x00 }, 390 + { 0x4100018a, 0x00 }, 391 + { 0x41001988, 0x00 }, 392 + { 0x41081400, 0x09 }, 393 + { 0x40801508, 0x03 }, 394 + { 0x40801588, 0x03 }, 395 + { 0x40801809, 0x00 }, 396 + { 0x4080180a, 0x00 }, 397 + { 0x4080180b, 0x00 }, 398 + { 0x4080180c, 0x00 }, 399 + { 0x40801b09, 0x00 }, 400 + { 0x40801b0a, 0x00 }, 401 + { 0x40801b0b, 0x00 }, 402 + { 0x40801b0c, 0x00 }, 403 + { 0x0000d714, 0x17 }, 404 + { 0x20009012, 0x00 }, 405 + { 0x0000dd0b, 0x0d }, 406 + { 0x0000dd0a, 0xff }, 407 + { 0x0000dd09, 0x0d }, 408 + { 0x0000dd08, 0xff }, 409 + { 0x0000d172, 0x2a }, 410 + { 0x41001988, 0x03 }, 411 + }; 412 + 258 413 static const struct reg_default rt1320_reg_defaults[] = { 259 414 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_PDE11, RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x03 }, 260 415 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_MUTE, CH_01), 0x01 }, ··· 494 339 case 0xf717 ... 0xf719: 495 340 case 0xf720 ... 0xf723: 496 341 case 0x1000cd91 ... 0x1000cd96: 342 + case RT1321_PATCH_MAIN_VER ... RT1321_PATCH_BETA_VER: 497 343 case 0x1000f008: 498 344 case 0x1000f021: 345 + case 0x2000300f: 346 + case 0x2000301c: 347 + case 0x2000900f: 348 + case 0x20009018: 349 + case 0x3fc29d80 ... 0x3fc29d83: 499 350 case 0x3fe2e000 ... 0x3fe2e003: 500 351 case 0x3fc2ab80 ... 0x3fc2abd4: 352 + case 0x3fc2bfc0 ... 0x3fc2bfc8: 353 + case 0x3fc2d300 ... 0x3fc2d354: 354 + case 0x3fc2dfc0 ... 0x3fc2dfc8: 501 355 /* 0x40801508/0x40801809/0x4080180a/0x40801909/0x4080190a */ 502 356 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_PDE11, RT1320_SDCA_CTL_REQ_POWER_STATE, 0): 503 357 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_MUTE, CH_01): ··· 557 393 case 0xc560: 558 394 case 0xc5b5 ... 0xc5b7: 559 395 case 0xc5fc ... 0xc5ff: 396 + case 0xc680 ... 0xc683: 560 397 case 0xc820: 561 398 case 0xc900: 562 399 case 0xc920: ··· 576 411 case 0xd4e5 ... 0xd4e6: 577 412 case 0xd4e8 ... 0xd4ff: 578 413 case 0xd530: 579 - case 0xd540: 414 + case 0xd540 ... 0xd541: 580 415 case 0xd543: 581 416 case 0xdb58 ... 0xdb5f: 582 417 case 0xdb60 ... 0xdb63: ··· 593 428 case 0xf01e: 594 429 case 0xf717 ... 0xf719: 595 430 case 0xf720 ... 0xf723: 596 - case 0x10000000 ... 0x10007fff: 431 + case 0x10000000 ... 0x10008fff: 597 432 case 0x1000c000 ... 0x1000dfff: 598 433 case 0x1000f008: 599 434 case 0x1000f021: 435 + case 0x2000300f: 436 + case 0x2000301c: 437 + case 0x2000900f: 438 + case 0x20009018: 600 439 case 0x3fc2ab80 ... 0x3fc2abd4: 440 + case 0x3fc2b780: 601 441 case 0x3fc2bf80 ... 0x3fc2bf83: 602 - case 0x3fc2bfc0 ... 0x3fc2bfc7: 442 + case 0x3fc2bfc0 ... 0x3fc2bfc8: 443 + case 0x3fc2d300 ... 0x3fc2d354: 444 + case 0x3fc2dfc0 ... 0x3fc2dfc8: 603 445 case 0x3fe2e000 ... 0x3fe2e003: 604 446 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_PDE11, RT1320_SDCA_CTL_ACTUAL_POWER_STATE, 0): 605 447 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT0, RT1320_SDCA_CTL_FUNC_STATUS, 0): ··· 731 559 static int rt1320_pde_transition_delay(struct rt1320_sdw_priv *rt1320, unsigned char func, 732 560 unsigned char entity, unsigned char ps) 733 561 { 734 - unsigned int delay = 1000, val; 562 + unsigned int delay = 2000, val; 735 563 736 564 pm_runtime_mark_last_busy(&rt1320->sdw_slave->dev); 737 565 ··· 762 590 struct sdw_slave *slave = rt1320->sdw_slave; 763 591 const struct firmware *patch; 764 592 const char *filename; 765 - unsigned int addr, val; 593 + unsigned int addr, val, min_addr, max_addr; 766 594 const unsigned char *ptr; 767 595 int ret, i; 768 596 769 - if (rt1320->version_id <= RT1320_VB) 770 - filename = RT1320_VAB_MCU_PATCH; 771 - else 772 - filename = RT1320_VC_MCU_PATCH; 597 + switch (rt1320->dev_id) { 598 + case RT1320_DEV_ID: 599 + if (rt1320->version_id <= RT1320_VB) 600 + filename = RT1320_VAB_MCU_PATCH; 601 + else 602 + filename = RT1320_VC_MCU_PATCH; 603 + min_addr = 0x10007000; 604 + max_addr = 0x10007fff; 605 + break; 606 + case RT1321_DEV_ID: 607 + filename = RT1321_VA_MCU_PATCH; 608 + min_addr = 0x10008000; 609 + max_addr = 0x10008fff; 610 + break; 611 + default: 612 + dev_err(&slave->dev, "%s: Unknown device ID %d\n", __func__, rt1320->dev_id); 613 + return; 614 + } 773 615 774 616 /* load the patch code here */ 775 617 ret = request_firmware(&patch, filename, &slave->dev); 776 618 if (ret) { 777 619 dev_err(&slave->dev, "%s: Failed to load %s firmware", __func__, filename); 778 620 regmap_write(rt1320->regmap, 0xc598, 0x00); 779 - regmap_write(rt1320->regmap, 0x10007000, 0x67); 780 - regmap_write(rt1320->regmap, 0x10007001, 0x80); 781 - regmap_write(rt1320->regmap, 0x10007002, 0x00); 782 - regmap_write(rt1320->regmap, 0x10007003, 0x00); 621 + regmap_write(rt1320->regmap, min_addr, 0x67); 622 + regmap_write(rt1320->regmap, min_addr + 0x1, 0x80); 623 + regmap_write(rt1320->regmap, min_addr + 0x2, 0x00); 624 + regmap_write(rt1320->regmap, min_addr + 0x3, 0x00); 625 + if (rt1320->dev_id == RT1321_DEV_ID) { 626 + regmap_write(rt1320->regmap, 0xd73c, 0x67); 627 + regmap_write(rt1320->regmap, 0xd73d, 0x80); 628 + regmap_write(rt1320->regmap, 0xd73e, 0x00); 629 + regmap_write(rt1320->regmap, 0xd73f, 0x00); 630 + } 783 631 } else { 784 632 ptr = (const unsigned char *)patch->data; 785 633 if ((patch->size % 8) == 0) { ··· 809 617 val = (ptr[i + 4] & 0xff) | (ptr[i + 5] & 0xff) << 8 | 810 618 (ptr[i + 6] & 0xff) << 16 | (ptr[i + 7] & 0xff) << 24; 811 619 812 - if (addr > 0x10007fff || addr < 0x10007000) { 620 + if (addr > max_addr || addr < min_addr) { 813 621 dev_err(&slave->dev, "%s: the address 0x%x is wrong", __func__, addr); 814 622 goto _exit_; 815 623 } ··· 879 687 } 880 688 } 881 689 690 + static void rt1321_preset(struct rt1320_sdw_priv *rt1320) 691 + { 692 + unsigned int i, reg, val, delay; 693 + 694 + for (i = 0; i < ARRAY_SIZE(rt1321_blind_write); i++) { 695 + reg = rt1321_blind_write[i].reg; 696 + val = rt1321_blind_write[i].def; 697 + delay = rt1321_blind_write[i].delay_us; 698 + 699 + if (reg == 0x3fc2dfc3) 700 + rt1320_load_mcu_patch(rt1320); 701 + 702 + regmap_write(rt1320->regmap, reg, val); 703 + 704 + if (delay) 705 + usleep_range(delay, delay + 1000); 706 + 707 + if (reg == SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0)) 708 + rt1320_pde_transition_delay(rt1320, FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, val); 709 + } 710 + } 711 + 882 712 static int rt1320_io_init(struct device *dev, struct sdw_slave *slave) 883 713 { 884 714 struct rt1320_sdw_priv *rt1320 = dev_get_drvdata(dev); ··· 927 713 if (rt1320->version_id < 0) { 928 714 regmap_read(rt1320->regmap, RT1320_DEV_VERSION_ID_1, &val); 929 715 rt1320->version_id = val; 716 + regmap_read(rt1320->regmap, RT1320_DEV_ID_0, &val); 717 + regmap_read(rt1320->regmap, RT1320_DEV_ID_1, &tmp); 718 + rt1320->dev_id = (val << 8) | tmp; 930 719 } 931 720 932 721 regmap_read(rt1320->regmap, ··· 938 721 939 722 /* initialization write */ 940 723 if ((amp_func_status & FUNCTION_NEEDS_INITIALIZATION)) { 941 - if (rt1320->version_id < RT1320_VC) 942 - rt1320_vab_preset(rt1320); 943 - else 944 - rt1320_vc_preset(rt1320); 724 + switch (rt1320->dev_id) { 725 + case RT1320_DEV_ID: 726 + if (rt1320->version_id < RT1320_VC) 727 + rt1320_vab_preset(rt1320); 728 + else 729 + rt1320_vc_preset(rt1320); 730 + break; 731 + case RT1321_DEV_ID: 732 + rt1321_preset(rt1320); 733 + break; 734 + default: 735 + dev_err(dev, "%s: Unknown device ID %d\n", __func__, rt1320->dev_id); 736 + } 945 737 946 738 regmap_write(rt1320->regmap, 947 739 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT0, RT1320_SDCA_CTL_FUNC_STATUS, 0), 948 740 FUNCTION_NEEDS_INITIALIZATION); 949 741 } 950 - if (!rt1320->first_hw_init && rt1320->version_id == RT1320_VA) { 742 + if (!rt1320->first_hw_init && rt1320->version_id == RT1320_VA && rt1320->dev_id == RT1320_DEV_ID) { 951 743 regmap_write(rt1320->regmap, SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, 952 744 RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0); 953 745 regmap_read(rt1320->regmap, RT1320_HIFI_VER_0, &val); ··· 976 750 regmap_write(rt1320->regmap, SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, 977 751 RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 3); 978 752 } 979 - dev_dbg(dev, "%s version_id=%d\n", __func__, rt1320->version_id); 753 + dev_dbg(dev, "%s version_id=%d, dev_id=0x%x\n", __func__, rt1320->version_id, rt1320->dev_id); 980 754 981 755 if (rt1320->first_hw_init) { 982 756 regcache_cache_bypass(rt1320->regmap, false); ··· 1119 893 1120 894 /* check all channels */ 1121 895 for (i = 0; i < p->count; i++) { 1122 - if (i < 2) { 896 + switch (rt1320->dev_id) { 897 + case RT1320_DEV_ID: 898 + if (i < 2) { 899 + reg_base = SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_01); 900 + regmap_read(rt1320->mbq_regmap, reg_base + i, &regvalue[i]); 901 + } else { 902 + reg_base = SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_VOLUME, CH_01); 903 + regmap_read(rt1320->mbq_regmap, reg_base + i - 2, &regvalue[i]); 904 + } 905 + break; 906 + case RT1321_DEV_ID: 1123 907 reg_base = SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_01); 1124 908 regmap_read(rt1320->mbq_regmap, reg_base + i, &regvalue[i]); 1125 - } else { 1126 - reg_base = SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_VOLUME, CH_01); 1127 - regmap_read(rt1320->mbq_regmap, reg_base + i - 2, &regvalue[i]); 909 + break; 1128 910 } 1129 911 1130 912 gain_val[i] = ucontrol->value.integer.value[i]; ··· 1149 915 return 0; 1150 916 1151 917 for (i = 0; i < p->count; i++) { 1152 - if (i < 2) { 918 + switch (rt1320->dev_id) { 919 + case RT1320_DEV_ID: 920 + if (i < 2) { 921 + reg_base = SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_01); 922 + err = regmap_write(rt1320->mbq_regmap, reg_base + i, gain_val[i]); 923 + } else { 924 + reg_base = SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_VOLUME, CH_01); 925 + err = regmap_write(rt1320->mbq_regmap, reg_base + i - 2, gain_val[i]); 926 + } 927 + break; 928 + case RT1321_DEV_ID: 1153 929 reg_base = SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_01); 1154 930 err = regmap_write(rt1320->mbq_regmap, reg_base + i, gain_val[i]); 1155 - } else { 1156 - reg_base = SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_VOLUME, CH_01); 1157 - err = regmap_write(rt1320->mbq_regmap, reg_base + i - 2, gain_val[i]); 931 + break; 1158 932 } 1159 933 1160 934 if (err < 0) ··· 1207 965 1208 966 /* check all channels */ 1209 967 for (i = 0; i < p->count; i++) { 1210 - if (i < 2) { 968 + switch (rt1320->dev_id) { 969 + case RT1320_DEV_ID: 970 + if (i < 2) { 971 + reg_base = SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_01); 972 + regmap_read(rt1320->mbq_regmap, reg_base + i, &regvalue); 973 + } else { 974 + reg_base = SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_VOLUME, CH_01); 975 + regmap_read(rt1320->mbq_regmap, reg_base + i - 2, &regvalue); 976 + } 977 + break; 978 + case RT1321_DEV_ID: 1211 979 reg_base = SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_01); 1212 980 regmap_read(rt1320->mbq_regmap, reg_base + i, &regvalue); 1213 - } else { 1214 - reg_base = SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_VOLUME, CH_01); 1215 - regmap_read(rt1320->mbq_regmap, reg_base + i - 2, &regvalue); 981 + break; 1216 982 } 1217 983 1218 984 ctl = p->max - (((0x1e00 - regvalue) & 0xffff) / interval_offset); ··· 1238 988 for (i = 0; i < ARRAY_SIZE(rt1320->fu_mixer_mute); i++) { 1239 989 ch_mute = (rt1320->fu_dapm_mute || rt1320->fu_mixer_mute[i]) ? 0x01 : 0x00; 1240 990 1241 - if (i < 2) 991 + switch (rt1320->dev_id) { 992 + case RT1320_DEV_ID: 993 + if (i < 2) 994 + err = regmap_write(rt1320->regmap, 995 + SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, 996 + RT1320_SDCA_CTL_FU_MUTE, CH_01) + i, ch_mute); 997 + else 998 + err = regmap_write(rt1320->regmap, 999 + SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, 1000 + RT1320_SDCA_CTL_FU_MUTE, CH_01) + i - 2, ch_mute); 1001 + break; 1002 + case RT1321_DEV_ID: 1242 1003 err = regmap_write(rt1320->regmap, 1243 1004 SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, 1244 1005 RT1320_SDCA_CTL_FU_MUTE, CH_01) + i, ch_mute); 1245 - else 1246 - err = regmap_write(rt1320->regmap, 1247 - SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, 1248 - RT1320_SDCA_CTL_FU_MUTE, CH_01) + i - 2, ch_mute); 1006 + break; 1007 + default: 1008 + dev_err(&rt1320->sdw_slave->dev, "%s: Unknown device ID %d\n", __func__, rt1320->dev_id); 1009 + return -EINVAL; 1010 + } 1249 1011 if (err < 0) 1250 1012 return err; 1251 1013 } ··· 1478 1216 if (dai->id == RT1320_AIF1) 1479 1217 port_config.num = 4; 1480 1218 else if (dai->id == RT1320_AIF2) { 1481 - dmic_port_config[0].ch_mask = BIT(0) | BIT(1); 1482 - dmic_port_config[0].num = 8; 1483 - dmic_port_config[1].ch_mask = BIT(0) | BIT(1); 1484 - dmic_port_config[1].num = 10; 1219 + switch (rt1320->dev_id) { 1220 + case RT1320_DEV_ID: 1221 + dmic_port_config[0].ch_mask = BIT(0) | BIT(1); 1222 + dmic_port_config[0].num = 8; 1223 + dmic_port_config[1].ch_mask = BIT(0) | BIT(1); 1224 + dmic_port_config[1].num = 10; 1225 + break; 1226 + case RT1321_DEV_ID: 1227 + dmic_port_config[0].ch_mask = BIT(0) | BIT(1); 1228 + dmic_port_config[0].num = 8; 1229 + break; 1230 + default: 1231 + return -EINVAL; 1232 + } 1485 1233 } else 1486 1234 return -EINVAL; 1487 1235 } ··· 1499 1227 if (dai->id == RT1320_AIF1) 1500 1228 retval = sdw_stream_add_slave(rt1320->sdw_slave, &stream_config, 1501 1229 &port_config, 1, sdw_stream); 1502 - else if (dai->id == RT1320_AIF2) 1503 - retval = sdw_stream_add_slave(rt1320->sdw_slave, &stream_config, 1230 + else if (dai->id == RT1320_AIF2) { 1231 + switch (rt1320->dev_id) { 1232 + case RT1320_DEV_ID: 1233 + retval = sdw_stream_add_slave(rt1320->sdw_slave, &stream_config, 1504 1234 dmic_port_config, 2, sdw_stream); 1505 - else 1235 + break; 1236 + case RT1321_DEV_ID: 1237 + retval = sdw_stream_add_slave(rt1320->sdw_slave, &stream_config, 1238 + dmic_port_config, 1, sdw_stream); 1239 + break; 1240 + default: 1241 + dev_err(dai->dev, "%s: Unknown device ID %d\n", __func__, rt1320->dev_id); 1242 + return -EINVAL; 1243 + } 1244 + } else 1506 1245 return -EINVAL; 1507 1246 if (retval) { 1508 1247 dev_err(dai->dev, "%s: Unable to configure port\n", __func__); ··· 1555 1272 regmap_write(rt1320->regmap, 1556 1273 SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_CS113, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), 1557 1274 sampling_rate); 1558 - regmap_write(rt1320->regmap, 1559 - SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_CS14, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), 1560 - sampling_rate); 1275 + 1276 + if (rt1320->dev_id == RT1320_DEV_ID) 1277 + regmap_write(rt1320->regmap, 1278 + SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_CS14, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), 1279 + sampling_rate); 1561 1280 } 1562 1281 1563 1282 return 0; ··· 1753 1468 static const struct sdw_device_id rt1320_id[] = { 1754 1469 SDW_SLAVE_ENTRY_EXT(0x025d, 0x1320, 0x3, 0x0, 0), 1755 1470 SDW_SLAVE_ENTRY_EXT(0x025d, 0x1320, 0x3, 0x1, 0), 1471 + SDW_SLAVE_ENTRY_EXT(0x025d, 0x1321, 0x3, 0x1, 0), 1756 1472 {}, 1757 1473 }; 1758 1474 MODULE_DEVICE_TABLE(sdw, rt1320_id);
+10
sound/soc/codecs/rt1320-sdw.h
··· 14 14 #include <linux/soundwire/sdw_registers.h> 15 15 #include <sound/soc.h> 16 16 17 + #define RT1320_DEV_ID 0x6981 18 + #define RT1321_DEV_ID 0x7045 19 + 17 20 /* imp-defined registers */ 18 21 #define RT1320_DEV_VERSION_ID_1 0xc404 22 + #define RT1320_DEV_ID_1 0xc405 23 + #define RT1320_DEV_ID_0 0xc406 24 + 25 + #define RT1321_PATCH_MAIN_VER 0x1000cffe 26 + #define RT1321_PATCH_BETA_VER 0x1000cfff 19 27 20 28 #define RT1320_KR0_STATUS_CNT 0x1000f008 21 29 #define RT1320_KR0_INT_READY 0x1000f021 ··· 94 86 #define RT1320_VER_B_ID 0x07392238 95 87 #define RT1320_VAB_MCU_PATCH "realtek/rt1320/rt1320-patch-code-vab.bin" 96 88 #define RT1320_VC_MCU_PATCH "realtek/rt1320/rt1320-patch-code-vc.bin" 89 + #define RT1321_VA_MCU_PATCH "realtek/rt1320/rt1321-patch-code-va.bin" 97 90 98 91 struct rt1320_sdw_priv { 99 92 struct snd_soc_component *component; ··· 105 96 bool hw_init; 106 97 bool first_hw_init; 107 98 int version_id; 99 + unsigned int dev_id; 108 100 bool fu_dapm_mute; 109 101 bool fu_mixer_mute[4]; 110 102 };