Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
clk: qcom: dispcc-sm8450: Add SM8475 support
Add support to the SM8475 display clock controller by extending the
SM8450 display clock controller, which is almost identical but has
some minor differences.
Signed-off-by: Danila Tikhonov <danila@jiaxyga.com>
Link: https://lore.kernel.org/r/20240818204348.197788-5-danila@jiaxyga.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
authored by
Danila Tikhonov
and committed by
Bjorn Andersson
7c0e8764
20e06dc8
+64
-4
+1
-1
drivers/clk/qcom/Kconfig
+1
-1
drivers/clk/qcom/Kconfig
+63
-3
drivers/clk/qcom/dispcc-sm8450.c
+63
-3
drivers/clk/qcom/dispcc-sm8450.c
···
85
85
.user_ctl_hi_val = 0x00000805,
86
86
};
87
87
88
+
static const struct alpha_pll_config sm8475_disp_cc_pll0_config = {
89
+
.l = 0xd,
90
+
.alpha = 0x6492,
91
+
.config_ctl_val = 0x20485699,
92
+
.config_ctl_hi_val = 0x00182261,
93
+
.config_ctl_hi1_val = 0x82aa299c,
94
+
.test_ctl_val = 0x00000000,
95
+
.test_ctl_hi_val = 0x00000003,
96
+
.test_ctl_hi1_val = 0x00009000,
97
+
.test_ctl_hi2_val = 0x00000034,
98
+
.user_ctl_val = 0x00000000,
99
+
.user_ctl_hi_val = 0x00000005,
100
+
};
101
+
102
+
static struct clk_init_data sm8475_disp_cc_pll0_init = {
103
+
.name = "disp_cc_pll0",
104
+
.parent_data = &(const struct clk_parent_data) {
105
+
.index = DT_BI_TCXO,
106
+
},
107
+
.num_parents = 1,
108
+
.ops = &clk_alpha_pll_reset_lucid_ole_ops,
109
+
};
110
+
88
111
static struct clk_alpha_pll disp_cc_pll0 = {
89
112
.offset = 0x0,
90
113
.vco_table = lucid_evo_vco,
···
133
110
.config_ctl_hi1_val = 0x32AA299C,
134
111
.user_ctl_val = 0x00000000,
135
112
.user_ctl_hi_val = 0x00000805,
113
+
};
114
+
115
+
static const struct alpha_pll_config sm8475_disp_cc_pll1_config = {
116
+
.l = 0x1f,
117
+
.alpha = 0x4000,
118
+
.config_ctl_val = 0x20485699,
119
+
.config_ctl_hi_val = 0x00182261,
120
+
.config_ctl_hi1_val = 0x82aa299c,
121
+
.test_ctl_val = 0x00000000,
122
+
.test_ctl_hi_val = 0x00000003,
123
+
.test_ctl_hi1_val = 0x00009000,
124
+
.test_ctl_hi2_val = 0x00000034,
125
+
.user_ctl_val = 0x00000000,
126
+
.user_ctl_hi_val = 0x00000005,
127
+
};
128
+
129
+
static struct clk_init_data sm8475_disp_cc_pll1_init = {
130
+
.name = "disp_cc_pll1",
131
+
.parent_data = &(const struct clk_parent_data) {
132
+
.index = DT_BI_TCXO,
133
+
},
134
+
.num_parents = 1,
135
+
.ops = &clk_alpha_pll_reset_lucid_ole_ops,
136
136
};
137
137
138
138
static struct clk_alpha_pll disp_cc_pll1 = {
···
1792
1746
1793
1747
static const struct of_device_id disp_cc_sm8450_match_table[] = {
1794
1748
{ .compatible = "qcom,sm8450-dispcc" },
1749
+
{ .compatible = "qcom,sm8475-dispcc" },
1795
1750
{ }
1796
1751
};
1797
1752
MODULE_DEVICE_TABLE(of, disp_cc_sm8450_match_table);
···
1816
1769
goto err_put_rpm;
1817
1770
}
1818
1771
1819
-
clk_lucid_evo_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config);
1820
-
clk_lucid_evo_pll_configure(&disp_cc_pll1, regmap, &disp_cc_pll1_config);
1772
+
if (of_device_is_compatible(pdev->dev.of_node, "qcom,sm8475-dispcc")) {
1773
+
/* Update DISPCC PLL0 */
1774
+
disp_cc_pll0.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
1775
+
disp_cc_pll0.clkr.hw.init = &sm8475_disp_cc_pll0_init;
1776
+
1777
+
/* Update DISPCC PLL1 */
1778
+
disp_cc_pll1.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
1779
+
disp_cc_pll1.clkr.hw.init = &sm8475_disp_cc_pll1_init;
1780
+
1781
+
clk_lucid_ole_pll_configure(&disp_cc_pll0, regmap, &sm8475_disp_cc_pll0_config);
1782
+
clk_lucid_ole_pll_configure(&disp_cc_pll1, regmap, &sm8475_disp_cc_pll1_config);
1783
+
} else {
1784
+
clk_lucid_evo_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config);
1785
+
clk_lucid_evo_pll_configure(&disp_cc_pll1, regmap, &disp_cc_pll1_config);
1786
+
}
1821
1787
1822
1788
/* Enable clock gating for MDP clocks */
1823
1789
regmap_update_bits(regmap, DISP_CC_MISC_CMD, 0x10, 0x10);
···
1862
1802
1863
1803
module_platform_driver(disp_cc_sm8450_driver);
1864
1804
1865
-
MODULE_DESCRIPTION("QTI DISPCC SM8450 Driver");
1805
+
MODULE_DESCRIPTION("QTI DISPCC SM8450 / SM8475 Driver");
1866
1806
MODULE_LICENSE("GPL");