Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'perf-core-2023-04-27' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull perf updates from Ingo Molnar:
- Add Intel Granite Rapids support
- Add uncore events for Intel SPR IMC PMU
- Fix perf IRQ throttling bug
* tag 'perf-core-2023-04-27' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
perf/x86/intel/uncore: Add events for Intel SPR IMC PMU
perf/core: Fix hardlockup failure caused by perf throttle
perf/x86/cstate: Add Granite Rapids support
perf/x86/msr: Add Granite Rapids
perf/x86/intel: Add Granite Rapids
+32
-4
+14
-2
arch/x86/events/intel/core.c
+14
-2
arch/x86/events/intel/core.c
···
5470
5470
}
5471
5471
5472
5472
static umode_t
5473
+
mem_is_visible(struct kobject *kobj, struct attribute *attr, int i)
5474
+
{
5475
+
if (attr == &event_attr_mem_ld_aux.attr.attr)
5476
+
return x86_pmu.flags & PMU_FL_MEM_LOADS_AUX ? attr->mode : 0;
5477
+
5478
+
return pebs_is_visible(kobj, attr, i);
5479
+
}
5480
+
5481
+
static umode_t
5473
5482
lbr_is_visible(struct kobject *kobj, struct attribute *attr, int i)
5474
5483
{
5475
5484
return x86_pmu.lbr_nr ? attr->mode : 0;
···
5505
5496
5506
5497
static struct attribute_group group_events_mem = {
5507
5498
.name = "events",
5508
-
.is_visible = pebs_is_visible,
5499
+
.is_visible = mem_is_visible,
5509
5500
};
5510
5501
5511
5502
static struct attribute_group group_events_tsx = {
···
6495
6486
6496
6487
case INTEL_FAM6_SAPPHIRERAPIDS_X:
6497
6488
case INTEL_FAM6_EMERALDRAPIDS_X:
6489
+
x86_pmu.flags |= PMU_FL_MEM_LOADS_AUX;
6490
+
fallthrough;
6491
+
case INTEL_FAM6_GRANITERAPIDS_X:
6492
+
case INTEL_FAM6_GRANITERAPIDS_D:
6498
6493
pmem = true;
6499
6494
x86_pmu.late_ack = true;
6500
6495
memcpy(hw_cache_event_ids, spr_hw_cache_event_ids, sizeof(hw_cache_event_ids));
···
6515
6502
x86_pmu.flags |= PMU_FL_HAS_RSP_1;
6516
6503
x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
6517
6504
x86_pmu.flags |= PMU_FL_INSTR_LATENCY;
6518
-
x86_pmu.flags |= PMU_FL_MEM_LOADS_AUX;
6519
6505
6520
6506
x86_pmu.hw_config = hsw_hw_config;
6521
6507
x86_pmu.get_event_constraints = spr_get_event_constraints;
+2
arch/x86/events/intel/cstate.c
+2
arch/x86/events/intel/cstate.c
···
678
678
X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_D, &icx_cstates),
679
679
X86_MATCH_INTEL_FAM6_MODEL(SAPPHIRERAPIDS_X, &icx_cstates),
680
680
X86_MATCH_INTEL_FAM6_MODEL(EMERALDRAPIDS_X, &icx_cstates),
681
+
X86_MATCH_INTEL_FAM6_MODEL(GRANITERAPIDS_X, &icx_cstates),
682
+
X86_MATCH_INTEL_FAM6_MODEL(GRANITERAPIDS_D, &icx_cstates),
681
683
682
684
X86_MATCH_INTEL_FAM6_MODEL(TIGERLAKE_L, &icl_cstates),
683
685
X86_MATCH_INTEL_FAM6_MODEL(TIGERLAKE, &icl_cstates),
+12
arch/x86/events/intel/uncore_snbep.c
+12
arch/x86/events/intel/uncore_snbep.c
···
6068
6068
.read_counter = uncore_mmio_read_counter,
6069
6069
};
6070
6070
6071
+
static struct uncore_event_desc spr_uncore_imc_events[] = {
6072
+
INTEL_UNCORE_EVENT_DESC(clockticks, "event=0x01,umask=0x00"),
6073
+
INTEL_UNCORE_EVENT_DESC(cas_count_read, "event=0x05,umask=0xcf"),
6074
+
INTEL_UNCORE_EVENT_DESC(cas_count_read.scale, "6.103515625e-5"),
6075
+
INTEL_UNCORE_EVENT_DESC(cas_count_read.unit, "MiB"),
6076
+
INTEL_UNCORE_EVENT_DESC(cas_count_write, "event=0x05,umask=0xf0"),
6077
+
INTEL_UNCORE_EVENT_DESC(cas_count_write.scale, "6.103515625e-5"),
6078
+
INTEL_UNCORE_EVENT_DESC(cas_count_write.unit, "MiB"),
6079
+
{ /* end: all zeroes */ },
6080
+
};
6081
+
6071
6082
static struct intel_uncore_type spr_uncore_imc = {
6072
6083
SPR_UNCORE_COMMON_FORMAT(),
6073
6084
.name = "imc",
···
6086
6075
.fixed_ctr = SNR_IMC_MMIO_PMON_FIXED_CTR,
6087
6076
.fixed_ctl = SNR_IMC_MMIO_PMON_FIXED_CTL,
6088
6077
.ops = &spr_uncore_mmio_ops,
6078
+
.event_descs = spr_uncore_imc_events,
6089
6079
};
6090
6080
6091
6081
static void spr_uncore_pci_enable_event(struct intel_uncore_box *box,
+2
arch/x86/events/msr.c
+2
arch/x86/events/msr.c
+2
-2
kernel/events/core.c
+2
-2
kernel/events/core.c
···
9433
9433
hwc->interrupts = 1;
9434
9434
} else {
9435
9435
hwc->interrupts++;
9436
-
if (unlikely(throttle
9437
-
&& hwc->interrupts >= max_samples_per_tick)) {
9436
+
if (unlikely(throttle &&
9437
+
hwc->interrupts > max_samples_per_tick)) {
9438
9438
__this_cpu_inc(perf_throttled_count);
9439
9439
tick_dep_set_cpu(smp_processor_id(), TICK_DEP_BIT_PERF_EVENTS);
9440
9440
hwc->interrupts = MAX_INTERRUPTS;