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drm: renesas: rz-du: mipi_dsi: Use mHz for D-PHY frequency calculations

Pass the HSFREQ in milli-Hz to the `dphy_init()` callback to improve
precision, especially for the RZ/V2H(P) SoC, where PLL dividers require
high accuracy.

These changes prepare the driver for upcoming RZ/V2H(P) SoC support.

Co-developed-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20250609225630.502888-7-prabhakar.mahadev-lad.rj@bp.renesas.com

authored by

Lad Prabhakar and committed by
Biju Das 7c3fecdd e96bec00

+8 -5
+8 -5
drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c
··· 37 37 struct rzg2l_mipi_dsi; 38 38 39 39 struct rzg2l_mipi_dsi_hw_info { 40 - int (*dphy_init)(struct rzg2l_mipi_dsi *dsi, unsigned long hsfreq); 40 + int (*dphy_init)(struct rzg2l_mipi_dsi *dsi, u64 hsfreq_millihz); 41 41 void (*dphy_exit)(struct rzg2l_mipi_dsi *dsi); 42 42 u32 phy_reg_offset; 43 43 u32 link_reg_offset; ··· 210 210 */ 211 211 212 212 static int rzg2l_mipi_dsi_dphy_init(struct rzg2l_mipi_dsi *dsi, 213 - unsigned long hsfreq) 213 + u64 hsfreq_millihz) 214 214 { 215 + unsigned long hsfreq = DIV_ROUND_CLOSEST_ULL(hsfreq_millihz, MILLI); 215 216 const struct rzg2l_mipi_dsi_timings *dphy_timings; 216 217 unsigned int i; 217 218 u32 dphyctrl0; ··· 285 284 const struct drm_display_mode *mode) 286 285 { 287 286 unsigned long hsfreq, vclk_rate; 287 + u64 hsfreq_millihz; 288 288 unsigned int bpp; 289 289 u32 txsetr; 290 290 u32 clstptsetr; ··· 318 316 * hsclk(bit) = hsclk(byte) * 8 = hsfreq 319 317 */ 320 318 bpp = mipi_dsi_pixel_format_to_bpp(dsi->format); 321 - hsfreq = DIV_ROUND_CLOSEST_ULL(vclk_rate * bpp, dsi->lanes); 319 + hsfreq_millihz = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(vclk_rate, bpp * MILLI), dsi->lanes); 322 320 323 - ret = dsi->info->dphy_init(dsi, hsfreq); 321 + ret = dsi->info->dphy_init(dsi, hsfreq_millihz); 324 322 if (ret < 0) 325 323 goto err_phy; 326 324 ··· 328 326 txsetr = TXSETR_DLEN | TXSETR_NUMLANEUSE(dsi->lanes - 1) | TXSETR_CLEN; 329 327 rzg2l_mipi_dsi_link_write(dsi, TXSETR, txsetr); 330 328 329 + hsfreq = DIV_ROUND_CLOSEST_ULL(hsfreq_millihz, MILLI); 331 330 /* 332 331 * Global timings characteristic depends on high speed Clock Frequency 333 332 * Currently MIPI DSI-IF just supports maximum FHD@60 with: ··· 968 965 * mode->clock and format are not available. So initialize DPHY with 969 966 * timing parameters for 80Mbps. 970 967 */ 971 - ret = dsi->info->dphy_init(dsi, 80000000); 968 + ret = dsi->info->dphy_init(dsi, 80000000ULL * MILLI); 972 969 if (ret < 0) 973 970 goto err_phy; 974 971