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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
dt-bindings: phy: Add i.MX8Q HSIO SerDes PHY binding
Add i.MX8QM and i.MX8QXP HSIO SerDes PHY binding.
Introduce one HSIO configuration 'fsl,hsio-cfg', which need be set at
initialization according to board design.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/1716962565-2084-2-git-send-email-hongxing.zhu@nxp.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
authored by
Richard Zhu
and committed by
Vinod Koul
7c46101a
d3ab7955
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Documentation/devicetree/bindings/phy/fsl,imx8qm-hsio.yaml
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Documentation/devicetree/bindings/phy/fsl,imx8qm-hsio.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/phy/fsl,imx8qm-hsio.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Freescale i.MX8QM SoC series High Speed IO(HSIO) SERDES PHY
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maintainers:
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- Richard Zhu <hongxing.zhu@nxp.com>
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properties:
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compatible:
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enum:
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- fsl,imx8qm-hsio
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- fsl,imx8qxp-hsio
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reg:
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items:
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- description: Base address and length of the PHY block
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- description: HSIO control and status registers(CSR) of the PHY
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- description: HSIO CSR of the controller bound to the PHY
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- description: HSIO CSR for MISC
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reg-names:
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items:
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- const: reg
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- const: phy
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- const: ctrl
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- const: misc
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"#phy-cells":
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const: 3
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description:
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The first defines lane index.
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The second defines the type of the PHY refer to the include phy.h.
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The third defines the controller index, indicated which controller
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is bound to the lane.
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clocks:
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minItems: 5
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maxItems: 14
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clock-names:
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minItems: 5
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maxItems: 14
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fsl,hsio-cfg:
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description: |
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Specifies the use case of the HSIO module in the hardware design.
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Regarding the design of i.MX8QM HSIO subsystem, HSIO module can be
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confiured as following three use cases.
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+---------------------------------------+
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| | i.MX8QM |
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|------------------|--------------------|
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| | Lane0| Lane1| Lane2|
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|------------------|------|------|------|
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| pciea-x2-sata | PCIEA| PCIEA| SATA |
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|------------------|------|------|------|
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| pciea-x2-pcieb | PCIEA| PCIEA| PCIEB|
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|------------------|------|------|------|
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| pciea-pcieb-sata | PCIEA| PCIEB| SATA |
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+---------------------------------------+
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$ref: /schemas/types.yaml#/definitions/string
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enum: [ pciea-x2-sata, pciea-x2-pcieb, pciea-pcieb-sata]
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default: pciea-pcieb-sata
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fsl,refclk-pad-mode:
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description:
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Specifies the mode of the refclk pad used. INPUT(PHY refclock is
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provided externally via the refclk pad) or OUTPUT(PHY refclock is
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derived from SoC internal source and provided on the refclk pad).
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This property not exists means unused(PHY refclock is derived from
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SoC internal source).
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$ref: /schemas/types.yaml#/definitions/string
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enum: [ input, output, unused ]
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default: unused
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power-domains:
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minItems: 1
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maxItems: 2
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required:
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- compatible
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- reg
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- reg-names
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- "#phy-cells"
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- clocks
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- clock-names
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- fsl,hsio-cfg
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allOf:
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- if:
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properties:
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compatible:
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contains:
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enum:
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- fsl,imx8qxp-hsio
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then:
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properties:
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clock-names:
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items:
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- const: pclk0
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- const: apb_pclk0
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- const: phy0_crr
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- const: ctl0_crr
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- const: misc_crr
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power-domains:
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maxItems: 1
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- if:
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properties:
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compatible:
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contains:
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enum:
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- fsl,imx8qm-hsio
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then:
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properties:
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clock-names:
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items:
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- const: pclk0
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- const: pclk1
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- const: apb_pclk0
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- const: apb_pclk1
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- const: pclk2
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- const: epcs_tx
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- const: epcs_rx
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- const: apb_pclk2
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- const: phy0_crr
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- const: phy1_crr
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- const: ctl0_crr
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- const: ctl1_crr
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- const: ctl2_crr
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- const: misc_crr
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power-domains:
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minItems: 2
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/imx8-clock.h>
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#include <dt-bindings/clock/imx8-lpcg.h>
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#include <dt-bindings/firmware/imx/rsrc.h>
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#include <dt-bindings/phy/phy-imx8-pcie.h>
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phy@5f1a0000 {
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compatible = "fsl,imx8qxp-hsio";
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reg = <0x5f1a0000 0x10000>,
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<0x5f120000 0x10000>,
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<0x5f140000 0x10000>,
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<0x5f160000 0x10000>;
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reg-names = "reg", "phy", "ctrl", "misc";
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clocks = <&phyx1_lpcg IMX_LPCG_CLK_0>,
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<&phyx1_lpcg IMX_LPCG_CLK_4>,
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<&phyx1_crr1_lpcg IMX_LPCG_CLK_4>,
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<&pcieb_crr3_lpcg IMX_LPCG_CLK_4>,
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<&misc_crr5_lpcg IMX_LPCG_CLK_4>;
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clock-names = "pclk0", "apb_pclk0", "phy0_crr", "ctl0_crr", "misc_crr";
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power-domains = <&pd IMX_SC_R_SERDES_1>;
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#phy-cells = <3>;
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fsl,hsio-cfg = "pciea-pcieb-sata";
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fsl,refclk-pad-mode = "input";
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};
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...