tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
1
fork

Configure Feed

Select the types of activity you want to include in your feed.

misc: microchip: pci1xxxx: Add PCIe Hot reset disable support for Rev C0 and later devices

Systems that issue PCIe hot reset requests during a suspend/resume
cycle cause PCI1XXXX device revisions prior to C0 to get its GPIO
configuration registers reset to hardware default values. This results
in device inaccessibility and GPIO read/write failure. Starting with
Revision C0, support was added in the device hardware (via the Hot
Reset Disable Bit) to allow resetting only the PCIe interface and its
associated logic, but preserving the GPIO configurations during a hot
reset. This patch enables the hot reset disable feature during suspend/
resume for C0 and later revisions of the device.

mchp_pci1xxxx_gpio is an auxiliary child of mchp_pci1xxxx_gp and does
not have access to system register address space for reading the device
revision. Hence, the device revision is retrieved directly from PCIe
config space.

Signed-off-by: Rengarajan S <rengarajan.s@microchip.com>
Link: https://lore.kernel.org/r/20250513091557.3660-2-rengarajan.s@microchip.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

authored by

Rengarajan S and committed by
Greg Kroah-Hartman 7c970c65 7b386d74

+31
+31
drivers/misc/mchp_pci1xxxx/mchp_pci1xxxx_gpio.c
··· 7 7 #include <linux/gpio/driver.h> 8 8 #include <linux/bio.h> 9 9 #include <linux/mutex.h> 10 + #include <linux/pci.h> 10 11 #include <linux/kthread.h> 11 12 #include <linux/interrupt.h> 12 13 13 14 #include "mchp_pci1xxxx_gp.h" 14 15 15 16 #define PCI1XXXX_NR_PINS 93 17 + #define PCI_DEV_REV_OFFSET 0x08 16 18 #define PERI_GEN_RESET 0 17 19 #define OUT_EN_OFFSET(x) ((((x) / 32) * 4) + 0x400) 18 20 #define INP_EN_OFFSET(x) ((((x) / 32) * 4) + 0x400 + 0x10) ··· 43 41 struct gpio_chip gpio; 44 42 spinlock_t lock; 45 43 int irq_base; 44 + u8 dev_rev; 46 45 }; 46 + 47 + static int pci1xxxx_gpio_get_device_revision(struct pci1xxxx_gpio *priv) 48 + { 49 + struct device *parent = priv->aux_dev->dev.parent; 50 + struct pci_dev *pcidev = to_pci_dev(parent); 51 + int ret; 52 + u32 val; 53 + 54 + ret = pci_read_config_dword(pcidev, PCI_DEV_REV_OFFSET, &val); 55 + if (ret) 56 + return ret; 57 + 58 + priv->dev_rev = val; 59 + 60 + return 0; 61 + } 47 62 48 63 static int pci1xxxx_gpio_get_direction(struct gpio_chip *gpio, unsigned int nr) 49 64 { ··· 335 316 pci1xxx_assign_bit(priv->reg_base, PIO_GLOBAL_CONFIG_OFFSET, 336 317 17, false); 337 318 pci1xxx_assign_bit(priv->reg_base, PERI_GEN_RESET, 16, true); 319 + 320 + if (priv->dev_rev >= 0xC0) 321 + pci1xxx_assign_bit(priv->reg_base, PERI_GEN_RESET, 17, true); 322 + 338 323 spin_unlock_irqrestore(&priv->lock, flags); 339 324 340 325 return 0; ··· 355 332 pci1xxx_assign_bit(priv->reg_base, PIO_GLOBAL_CONFIG_OFFSET, 356 333 16, false); 357 334 pci1xxx_assign_bit(priv->reg_base, PERI_GEN_RESET, 16, false); 335 + 336 + if (priv->dev_rev >= 0xC0) 337 + pci1xxx_assign_bit(priv->reg_base, PERI_GEN_RESET, 17, false); 338 + 358 339 spin_unlock_irqrestore(&priv->lock, flags); 359 340 360 341 return 0; ··· 438 411 retval = pci1xxxx_gpio_setup(priv, pdata->irq_num); 439 412 440 413 if (retval < 0) 414 + return retval; 415 + 416 + retval = pci1xxxx_gpio_get_device_revision(priv); 417 + if (retval) 441 418 return retval; 442 419 443 420 dev_set_drvdata(&aux_dev->dev, priv);