arm64: dts: renesas: rzg2lc-smarc-som: Enable eMMC on SMARC platform

RZ/G2LC SoM has both 64 GB eMMC and microSD connected to SDHI0.

Both these interfaces are mutually exclusive and the SD0 device
selection is based on the XOR between GPIO_SD0_DEV_SEL and SW1[2]
switch position.

This patch sets GPIO_SD0_DEV_SEL to high in DT. Use the below switch
setting logic for device selection between eMMC and microSD slot
connected to SDHI0.

Set SW1[2] to position OFF for selecting eMMC
Set SW1[2] to position ON for selecting microSD

This patch enables eMMC on RZ/G2LC SMARC platform by default.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20220117075130.6198-1-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

authored by

Biju Das and committed by

Geert Uytterhoeven 4 years ago 7ca0ce64 f91c4c74

+142

1 changed file

expand all

arch

arm64

boot

dts

renesas

rzg2lc-smarc-som.dtsi

+142

arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi

··· 8 8 #include <dt-bindings/gpio/gpio.h> 9 9 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h> 10 10 11 + /* SW1[2] should be at OFF position to enable 64 GB eMMC */ 12 + #define EMMC 1 13 + 14 + /* 15 + * To enable uSD card on CN3, 16 + * SW1[2] should be at ON position. 17 + * Disable eMMC by setting "#define EMMC 0" above. 18 + */ 19 + #define SDHI (!EMMC) 20 + 11 21 / { 12 22 aliases { 13 23 ethernet0 = &eth0; ··· 31 21 device_type = "memory"; 32 22 /* first 128MB is reserved for secure area. */ 33 23 reg = <0x0 0x48000000 0x0 0x38000000>; 24 + }; 25 + 26 + reg_1p8v: regulator0 { 27 + compatible = "regulator-fixed"; 28 + regulator-name = "fixed-1.8V"; 29 + regulator-min-microvolt = <1800000>; 30 + regulator-max-microvolt = <1800000>; 31 + regulator-boot-on; 32 + regulator-always-on; 33 + }; 34 + 35 + reg_3p3v: regulator1 { 36 + compatible = "regulator-fixed"; 37 + regulator-name = "fixed-3.3V"; 38 + regulator-min-microvolt = <3300000>; 39 + regulator-max-microvolt = <3300000>; 40 + regulator-boot-on; 41 + regulator-always-on; 42 + }; 43 + 44 + vccq_sdhi0: regulator-vccq-sdhi0 { 45 + compatible = "regulator-gpio"; 46 + 47 + regulator-name = "SDHI0 VccQ"; 48 + regulator-min-microvolt = <1800000>; 49 + regulator-max-microvolt = <3300000>; 50 + states = <3300000 1>, <1800000 0>; 51 + regulator-boot-on; 52 + gpios = <&pinctrl RZG2L_GPIO(39, 0) GPIO_ACTIVE_HIGH>; 53 + regulator-always-on; 34 54 }; 35 55 }; 36 56 ··· 112 72 <RZG2L_PORT_PINMUX(26, 0, 1)>, /* ET0_RXD2 */ 113 73 <RZG2L_PORT_PINMUX(26, 1, 1)>; /* ET0_RXD3 */ 114 74 }; 75 + 76 + gpio-sd0-pwr-en-hog { 77 + gpio-hog; 78 + gpios = <RZG2L_GPIO(18, 1) GPIO_ACTIVE_HIGH>; 79 + output-high; 80 + line-name = "gpio_sd0_pwr_en"; 81 + }; 82 + 83 + /* 84 + * SD0 device selection is XOR between GPIO_SD0_DEV_SEL and SW1[2] 85 + * The below switch logic can be used to select the device between 86 + * eMMC and microSD, after setting GPIO_SD0_DEV_SEL to high in DT. 87 + * SW1[2] should be at OFF position to enable 64 GB eMMC 88 + * SW1[2] should be at position ON to enable uSD card CN3 89 + */ 90 + gpio-sd0-dev-sel-hog { 91 + gpio-hog; 92 + gpios = <RZG2L_GPIO(40, 2) GPIO_ACTIVE_HIGH>; 93 + output-high; 94 + line-name = "gpio_sd0_dev_sel"; 95 + }; 96 + 97 + sdhi0_emmc_pins: sd0emmc { 98 + sd0_emmc_data { 99 + pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3", 100 + "SD0_DATA4", "SD0_DATA5", "SD0_DATA6", "SD0_DATA7"; 101 + power-source = <1800>; 102 + }; 103 + 104 + sd0_emmc_ctrl { 105 + pins = "SD0_CLK", "SD0_CMD"; 106 + power-source = <1800>; 107 + }; 108 + 109 + sd0_emmc_rst { 110 + pins = "SD0_RST#"; 111 + power-source = <1800>; 112 + }; 113 + }; 114 + 115 + sdhi0_pins: sd0 { 116 + sd0_data { 117 + pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3"; 118 + power-source = <3300>; 119 + }; 120 + 121 + sd0_ctrl { 122 + pins = "SD0_CLK", "SD0_CMD"; 123 + power-source = <3300>; 124 + }; 125 + 126 + sd0_mux { 127 + pinmux = <RZG2L_PORT_PINMUX(18, 0, 1)>; /* SD0_CD */ 128 + }; 129 + }; 130 + 131 + sdhi0_pins_uhs: sd0_uhs { 132 + sd0_data_uhs { 133 + pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3"; 134 + power-source = <1800>; 135 + }; 136 + 137 + sd0_ctrl_uhs { 138 + pins = "SD0_CLK", "SD0_CMD"; 139 + power-source = <1800>; 140 + }; 141 + 142 + sd0_mux_uhs { 143 + pinmux = <RZG2L_PORT_PINMUX(18, 0, 1)>; /* SD0_CD */ 144 + }; 145 + }; 115 146 }; 147 + 148 + #if SDHI 149 + &sdhi0 { 150 + pinctrl-0 = <&sdhi0_pins>; 151 + pinctrl-1 = <&sdhi0_pins_uhs>; 152 + pinctrl-names = "default", "state_uhs"; 153 + 154 + vmmc-supply = <&reg_3p3v>; 155 + vqmmc-supply = <&vccq_sdhi0>; 156 + bus-width = <4>; 157 + sd-uhs-sdr50; 158 + sd-uhs-sdr104; 159 + status = "okay"; 160 + }; 161 + #endif 162 + 163 + #if EMMC 164 + &sdhi0 { 165 + pinctrl-0 = <&sdhi0_emmc_pins>; 166 + pinctrl-1 = <&sdhi0_emmc_pins>; 167 + pinctrl-names = "default", "state_uhs"; 168 + 169 + vmmc-supply = <&reg_3p3v>; 170 + vqmmc-supply = <&reg_1p8v>; 171 + bus-width = <8>; 172 + mmc-hs200-1_8v; 173 + non-removable; 174 + fixed-emmc-driver-type = <1>; 175 + status = "okay"; 176 + }; 177 + #endif 116 178

Configure Feed

Configure Feed