tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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iommu/riscv: Allow RISC_VIOMMU to COMPILE_TEST

This driver used to use a lot of page table constants from the architecture
code which prevented COMPILE_TEST on other architectures. Now that iommupt
provides all of the constants internally there are only two small bumps
preventing COMPILE_TEST.

- Use the generic functions for the riscv specific phys_to_pfn() and
pfn_to_phys()

- Use CONFIG_MMIOWB to block off the mmiowb() barrier

- Require 64 bit because of writeq use failing compilation on 32 bit

Tested-by: Vincent Chen <vincent.chen@sifive.com>
Acked-by: Paul Walmsley <pjw@kernel.org> # arch/riscv
Reviewed-by: Tomasz Jeznach <tjeznach@rivosinc.com>
Tested-by: Tomasz Jeznach <tjeznach@rivosinc.com>
Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>

authored by

Jason Gunthorpe and committed by
Joerg Roedel 7cd0c655 c70d20b2

+8 -4
+2 -2
drivers/iommu/riscv/Kconfig
··· 3 3 4 4 config RISCV_IOMMU 5 5 bool "RISC-V IOMMU Support" 6 - depends on RISCV && 64BIT 6 + default RISCV 7 7 depends on GENERIC_MSI_IRQ 8 - default y 8 + depends on (RISCV || COMPILE_TEST) && 64BIT 9 9 select IOMMU_API 10 10 select GENERIC_PT 11 11 select IOMMU_PT
+3 -1
drivers/iommu/riscv/iommu-bits.h
··· 17 17 #include <linux/types.h> 18 18 #include <linux/bitfield.h> 19 19 #include <linux/bits.h> 20 + #include <asm/page.h> 20 21 21 22 /* 22 23 * Chapter 5: Memory Mapped register interface ··· 719 718 static inline void riscv_iommu_cmd_inval_set_addr(struct riscv_iommu_command *cmd, 720 719 u64 addr) 721 720 { 722 - cmd->dword1 = FIELD_PREP(RISCV_IOMMU_CMD_IOTINVAL_ADDR, phys_to_pfn(addr)); 721 + cmd->dword1 = 722 + FIELD_PREP(RISCV_IOMMU_CMD_IOTINVAL_ADDR, PHYS_PFN(addr)); 723 723 cmd->dword0 |= RISCV_IOMMU_CMD_IOTINVAL_AV; 724 724 } 725 725
+3 -1
drivers/iommu/riscv/iommu.c
··· 160 160 if (FIELD_GET(RISCV_IOMMU_PPN_FIELD, qb)) { 161 161 const size_t queue_size = entry_size << (logsz + 1); 162 162 163 - queue->phys = pfn_to_phys(FIELD_GET(RISCV_IOMMU_PPN_FIELD, qb)); 163 + queue->phys = PFN_PHYS(FIELD_GET(RISCV_IOMMU_PPN_FIELD, qb)); 164 164 queue->base = devm_ioremap(iommu->dev, queue->phys, queue_size); 165 165 } else { 166 166 do { ··· 436 436 * 6. Make sure the doorbell write to the device has finished before updating 437 437 * the shadow tail index in normal memory. 'fence o, w' 438 438 */ 439 + #ifdef CONFIG_MMIOWB 439 440 mmiowb(); 441 + #endif 440 442 atomic_inc(&queue->tail); 441 443 442 444 /* 7. Complete submission and restore local interrupts */