Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux

+19 -16

drivers/gpu/drm/drm_crtc.c

··· 43 43 #include "drm_crtc_internal.h" 44 44 #include "drm_internal.h" 45 45 46 - static struct drm_framebuffer *add_framebuffer_internal(struct drm_device *dev, 47 - struct drm_mode_fb_cmd2 *r, 48 - struct drm_file *file_priv); 46 + static struct drm_framebuffer * 47 + internal_framebuffer_create(struct drm_device *dev, 48 + struct drm_mode_fb_cmd2 *r, 49 + struct drm_file *file_priv); 49 50 50 51 /* Avoid boilerplate. I'm tired of typing. */ 51 52 #define DRM_ENUM_NAME_FN(fnname, list) \ ··· 2909 2908 */ 2910 2909 if (req->flags & DRM_MODE_CURSOR_BO) { 2911 2910 if (req->handle) { 2912 - fb = add_framebuffer_internal(dev, &fbreq, file_priv); 2911 + fb = internal_framebuffer_create(dev, &fbreq, file_priv); 2913 2912 if (IS_ERR(fb)) { 2914 2913 DRM_DEBUG_KMS("failed to wrap cursor buffer in drm framebuffer\n"); 2915 2914 return PTR_ERR(fb); 2916 2915 } 2917 - 2918 - drm_framebuffer_reference(fb); 2919 2916 } else { 2920 2917 fb = NULL; 2921 2918 } ··· 3266 3267 return 0; 3267 3268 } 3268 3269 3269 - static struct drm_framebuffer *add_framebuffer_internal(struct drm_device *dev, 3270 - struct drm_mode_fb_cmd2 *r, 3271 - struct drm_file *file_priv) 3270 + static struct drm_framebuffer * 3271 + internal_framebuffer_create(struct drm_device *dev, 3272 + struct drm_mode_fb_cmd2 *r, 3273 + struct drm_file *file_priv) 3272 3274 { 3273 3275 struct drm_mode_config *config = &dev->mode_config; 3274 3276 struct drm_framebuffer *fb; ··· 3301 3301 return fb; 3302 3302 } 3303 3303 3304 - mutex_lock(&file_priv->fbs_lock); 3305 - r->fb_id = fb->base.id; 3306 - list_add(&fb->filp_head, &file_priv->fbs); 3307 - DRM_DEBUG_KMS("[FB:%d]\n", fb->base.id); 3308 - mutex_unlock(&file_priv->fbs_lock); 3309 - 3310 3304 return fb; 3311 3305 } 3312 3306 ··· 3322 3328 int drm_mode_addfb2(struct drm_device *dev, 3323 3329 void *data, struct drm_file *file_priv) 3324 3330 { 3331 + struct drm_mode_fb_cmd2 *r = data; 3325 3332 struct drm_framebuffer *fb; 3326 3333 3327 3334 if (!drm_core_check_feature(dev, DRIVER_MODESET)) 3328 3335 return -EINVAL; 3329 3336 3330 - fb = add_framebuffer_internal(dev, data, file_priv); 3337 + fb = internal_framebuffer_create(dev, r, file_priv); 3331 3338 if (IS_ERR(fb)) 3332 3339 return PTR_ERR(fb); 3340 + 3341 + /* Transfer ownership to the filp for reaping on close */ 3342 + 3343 + DRM_DEBUG_KMS("[FB:%d]\n", fb->base.id); 3344 + mutex_lock(&file_priv->fbs_lock); 3345 + r->fb_id = fb->base.id; 3346 + list_add(&fb->filp_head, &file_priv->fbs); 3347 + mutex_unlock(&file_priv->fbs_lock); 3333 3348 3334 3349 return 0; 3335 3350 }

+8 -3

drivers/gpu/drm/drm_dp_mst_topology.c

··· 733 733 struct drm_dp_sideband_msg_tx *txmsg) 734 734 { 735 735 bool ret; 736 - mutex_lock(&mgr->qlock); 736 + 737 + /* 738 + * All updates to txmsg->state are protected by mgr->qlock, and the two 739 + * cases we check here are terminal states. For those the barriers 740 + * provided by the wake_up/wait_event pair are enough. 741 + */ 737 742 ret = (txmsg->state == DRM_DP_SIDEBAND_TX_RX || 738 743 txmsg->state == DRM_DP_SIDEBAND_TX_TIMEOUT); 739 - mutex_unlock(&mgr->qlock); 740 744 return ret; 741 745 } 742 746 ··· 1367 1363 return 0; 1368 1364 } 1369 1365 1370 - /* must be called holding qlock */ 1371 1366 static void process_single_down_tx_qlock(struct drm_dp_mst_topology_mgr *mgr) 1372 1367 { 1373 1368 struct drm_dp_sideband_msg_tx *txmsg; 1374 1369 int ret; 1370 + 1371 + WARN_ON(!mutex_is_locked(&mgr->qlock)); 1375 1372 1376 1373 /* construct a chunk from the first msg in the tx_msg queue */ 1377 1374 if (list_empty(&mgr->tx_msg_downq)) {

+20 -5

drivers/gpu/drm/i915/i915_gem.c

··· 2936 2936 req = obj->last_read_req; 2937 2937 2938 2938 /* Do this after OLR check to make sure we make forward progress polling 2939 - * on this IOCTL with a timeout <=0 (like busy ioctl) 2939 + * on this IOCTL with a timeout == 0 (like busy ioctl) 2940 2940 */ 2941 - if (args->timeout_ns <= 0) { 2941 + if (args->timeout_ns == 0) { 2942 2942 ret = -ETIME; 2943 2943 goto out; 2944 2944 } ··· 2948 2948 i915_gem_request_reference(req); 2949 2949 mutex_unlock(&dev->struct_mutex); 2950 2950 2951 - ret = __i915_wait_request(req, reset_counter, true, &args->timeout_ns, 2951 + ret = __i915_wait_request(req, reset_counter, true, 2952 + args->timeout_ns > 0 ? &args->timeout_ns : NULL, 2952 2953 file->driver_priv); 2953 2954 mutex_lock(&dev->struct_mutex); 2954 2955 i915_gem_request_unreference(req); ··· 4793 4792 if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt()) 4794 4793 return -EIO; 4795 4794 4795 + /* Double layer security blanket, see i915_gem_init() */ 4796 + intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); 4797 + 4796 4798 if (dev_priv->ellc_size) 4797 4799 I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf)); 4798 4800 ··· 4828 4824 for_each_ring(ring, dev_priv, i) { 4829 4825 ret = ring->init_hw(ring); 4830 4826 if (ret) 4831 - return ret; 4827 + goto out; 4832 4828 } 4833 4829 4834 4830 for (i = 0; i < NUM_L3_SLICES(dev); i++) ··· 4845 4841 DRM_ERROR("Context enable failed %d\n", ret); 4846 4842 i915_gem_cleanup_ringbuffer(dev); 4847 4843 4848 - return ret; 4844 + goto out; 4849 4845 } 4850 4846 4847 + out: 4848 + intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); 4851 4849 return ret; 4852 4850 } 4853 4851 ··· 4883 4877 dev_priv->gt.stop_ring = intel_logical_ring_stop; 4884 4878 } 4885 4879 4880 + /* This is just a security blanket to placate dragons. 4881 + * On some systems, we very sporadically observe that the first TLBs 4882 + * used by the CS may be stale, despite us poking the TLB reset. If 4883 + * we hold the forcewake during initialisation these problems 4884 + * just magically go away. 4885 + */ 4886 + intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); 4887 + 4886 4888 ret = i915_gem_init_userptr(dev); 4887 4889 if (ret) 4888 4890 goto out_unlock; ··· 4917 4903 } 4918 4904 4919 4905 out_unlock: 4906 + intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); 4920 4907 mutex_unlock(&dev->struct_mutex); 4921 4908 4922 4909 return ret;

+1 -1

drivers/gpu/drm/i915/intel_display.c

··· 9716 9716 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; 9717 9717 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 9718 9718 9719 - WARN_ON(!in_irq()); 9719 + WARN_ON(!in_interrupt()); 9720 9720 9721 9721 if (crtc == NULL) 9722 9722 return;

+7 -1

drivers/gpu/drm/i915/intel_uncore.c

··· 1048 1048 1049 1049 /* We need to init first for ECOBUS access and then 1050 1050 * determine later if we want to reinit, in case of MT access is 1051 - * not working 1051 + * not working. In this stage we don't know which flavour this 1052 + * ivb is, so it is better to reset also the gen6 fw registers 1053 + * before the ecobus check. 1052 1054 */ 1055 + 1056 + __raw_i915_write32(dev_priv, FORCEWAKE, 0); 1057 + __raw_posting_read(dev_priv, ECOBUS); 1058 + 1053 1059 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER, 1054 1060 FORCEWAKE_MT, FORCEWAKE_MT_ACK); 1055 1061

+44 -22

drivers/gpu/drm/radeon/radeon_fence.c

··· 1030 1030 return test_bit(FENCE_FLAG_SIGNALED_BIT, &fence->base.flags); 1031 1031 } 1032 1032 1033 + struct radeon_wait_cb { 1034 + struct fence_cb base; 1035 + struct task_struct *task; 1036 + }; 1037 + 1038 + static void 1039 + radeon_fence_wait_cb(struct fence *fence, struct fence_cb *cb) 1040 + { 1041 + struct radeon_wait_cb *wait = 1042 + container_of(cb, struct radeon_wait_cb, base); 1043 + 1044 + wake_up_process(wait->task); 1045 + } 1046 + 1033 1047 static signed long radeon_fence_default_wait(struct fence *f, bool intr, 1034 1048 signed long t) 1035 1049 { 1036 1050 struct radeon_fence *fence = to_radeon_fence(f); 1037 1051 struct radeon_device *rdev = fence->rdev; 1038 - bool signaled; 1052 + struct radeon_wait_cb cb; 1039 1053 1040 - fence_enable_sw_signaling(&fence->base); 1054 + cb.task = current; 1041 1055 1042 - /* 1043 - * This function has to return -EDEADLK, but cannot hold 1044 - * exclusive_lock during the wait because some callers 1045 - * may already hold it. This means checking needs_reset without 1046 - * lock, and not fiddling with any gpu internals. 1047 - * 1048 - * The callback installed with fence_enable_sw_signaling will 1049 - * run before our wait_event_*timeout call, so we will see 1050 - * both the signaled fence and the changes to needs_reset. 1051 - */ 1056 + if (fence_add_callback(f, &cb.base, radeon_fence_wait_cb)) 1057 + return t; 1052 1058 1053 - if (intr) 1054 - t = wait_event_interruptible_timeout(rdev->fence_queue, 1055 - ((signaled = radeon_test_signaled(fence)) || 1056 - rdev->needs_reset), t); 1057 - else 1058 - t = wait_event_timeout(rdev->fence_queue, 1059 - ((signaled = radeon_test_signaled(fence)) || 1060 - rdev->needs_reset), t); 1059 + while (t > 0) { 1060 + if (intr) 1061 + set_current_state(TASK_INTERRUPTIBLE); 1062 + else 1063 + set_current_state(TASK_UNINTERRUPTIBLE); 1061 1064 1062 - if (t > 0 && !signaled) 1063 - return -EDEADLK; 1065 + /* 1066 + * radeon_test_signaled must be called after 1067 + * set_current_state to prevent a race with wake_up_process 1068 + */ 1069 + if (radeon_test_signaled(fence)) 1070 + break; 1071 + 1072 + if (rdev->needs_reset) { 1073 + t = -EDEADLK; 1074 + break; 1075 + } 1076 + 1077 + t = schedule_timeout(t); 1078 + 1079 + if (t > 0 && intr && signal_pending(current)) 1080 + t = -ERESTARTSYS; 1081 + } 1082 + 1083 + __set_current_state(TASK_RUNNING); 1084 + fence_remove_callback(f, &cb.base); 1085 + 1064 1086 return t; 1065 1087 } 1066 1088

+2 -4

drivers/gpu/drm/radeon/si.c

··· 7130 7130 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~UPLL_BYPASS_EN_MASK); 7131 7131 7132 7132 if (!vclk || !dclk) { 7133 - /* keep the Bypass mode, put PLL to sleep */ 7134 - WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK); 7133 + /* keep the Bypass mode */ 7135 7134 return 0; 7136 7135 } 7137 7136 ··· 7146 7147 /* set VCO_MODE to 1 */ 7147 7148 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_VCO_MODE_MASK, ~UPLL_VCO_MODE_MASK); 7148 7149 7149 - /* toggle UPLL_SLEEP to 1 then back to 0 */ 7150 - WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK); 7150 + /* disable sleep mode */ 7151 7151 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_SLEEP_MASK); 7152 7152 7153 7153 /* deassert UPLL_RESET */

+41 -37

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

··· 725 725 goto out_err1; 726 726 } 727 727 728 - ret = ttm_bo_init_mm(&dev_priv->bdev, TTM_PL_VRAM, 729 - (dev_priv->vram_size >> PAGE_SHIFT)); 730 - if (unlikely(ret != 0)) { 731 - DRM_ERROR("Failed initializing memory manager for VRAM.\n"); 732 - goto out_err2; 733 - } 734 - 735 - dev_priv->has_gmr = true; 736 - if (((dev_priv->capabilities & (SVGA_CAP_GMR | SVGA_CAP_GMR2)) == 0) || 737 - refuse_dma || ttm_bo_init_mm(&dev_priv->bdev, VMW_PL_GMR, 738 - VMW_PL_GMR) != 0) { 739 - DRM_INFO("No GMR memory available. " 740 - "Graphics memory resources are very limited.\n"); 741 - dev_priv->has_gmr = false; 742 - } 743 - 744 - if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) { 745 - dev_priv->has_mob = true; 746 - if (ttm_bo_init_mm(&dev_priv->bdev, VMW_PL_MOB, 747 - VMW_PL_MOB) != 0) { 748 - DRM_INFO("No MOB memory available. " 749 - "3D will be disabled.\n"); 750 - dev_priv->has_mob = false; 751 - } 752 - } 753 - 754 728 dev_priv->mmio_mtrr = arch_phys_wc_add(dev_priv->mmio_start, 755 729 dev_priv->mmio_size); 756 730 ··· 787 813 goto out_no_fman; 788 814 } 789 815 816 + 817 + ret = ttm_bo_init_mm(&dev_priv->bdev, TTM_PL_VRAM, 818 + (dev_priv->vram_size >> PAGE_SHIFT)); 819 + if (unlikely(ret != 0)) { 820 + DRM_ERROR("Failed initializing memory manager for VRAM.\n"); 821 + goto out_no_vram; 822 + } 823 + 824 + dev_priv->has_gmr = true; 825 + if (((dev_priv->capabilities & (SVGA_CAP_GMR | SVGA_CAP_GMR2)) == 0) || 826 + refuse_dma || ttm_bo_init_mm(&dev_priv->bdev, VMW_PL_GMR, 827 + VMW_PL_GMR) != 0) { 828 + DRM_INFO("No GMR memory available. " 829 + "Graphics memory resources are very limited.\n"); 830 + dev_priv->has_gmr = false; 831 + } 832 + 833 + if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) { 834 + dev_priv->has_mob = true; 835 + if (ttm_bo_init_mm(&dev_priv->bdev, VMW_PL_MOB, 836 + VMW_PL_MOB) != 0) { 837 + DRM_INFO("No MOB memory available. " 838 + "3D will be disabled.\n"); 839 + dev_priv->has_mob = false; 840 + } 841 + } 842 + 790 843 vmw_kms_save_vga(dev_priv); 791 844 792 845 /* Start kms and overlay systems, needs fifo. */ ··· 839 838 vmw_kms_close(dev_priv); 840 839 out_no_kms: 841 840 vmw_kms_restore_vga(dev_priv); 841 + if (dev_priv->has_mob) 842 + (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_MOB); 843 + if (dev_priv->has_gmr) 844 + (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR); 845 + (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM); 846 + out_no_vram: 842 847 vmw_fence_manager_takedown(dev_priv->fman); 843 848 out_no_fman: 844 849 if (dev_priv->capabilities & SVGA_CAP_IRQMASK) ··· 860 853 iounmap(dev_priv->mmio_virt); 861 854 out_err3: 862 855 arch_phys_wc_del(dev_priv->mmio_mtrr); 863 - if (dev_priv->has_mob) 864 - (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_MOB); 865 - if (dev_priv->has_gmr) 866 - (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR); 867 - (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM); 868 - out_err2: 869 856 (void)ttm_bo_device_release(&dev_priv->bdev); 870 857 out_err1: 871 858 vmw_ttm_global_release(dev_priv); ··· 888 887 } 889 888 vmw_kms_close(dev_priv); 890 889 vmw_overlay_close(dev_priv); 890 + 891 + if (dev_priv->has_mob) 892 + (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_MOB); 893 + if (dev_priv->has_gmr) 894 + (void)ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR); 895 + (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM); 896 + 891 897 vmw_fence_manager_takedown(dev_priv->fman); 892 898 if (dev_priv->capabilities & SVGA_CAP_IRQMASK) 893 899 drm_irq_uninstall(dev_priv->dev); ··· 906 898 ttm_object_device_release(&dev_priv->tdev); 907 899 iounmap(dev_priv->mmio_virt); 908 900 arch_phys_wc_del(dev_priv->mmio_mtrr); 909 - if (dev_priv->has_mob) 910 - (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_MOB); 911 - if (dev_priv->has_gmr) 912 - (void)ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR); 913 - (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM); 914 901 (void)ttm_bo_device_release(&dev_priv->bdev); 915 902 vmw_ttm_global_release(dev_priv); 916 903 ··· 1238 1235 { 1239 1236 struct drm_device *dev = pci_get_drvdata(pdev); 1240 1237 1238 + pci_disable_device(pdev); 1241 1239 drm_put_dev(dev); 1242 1240 } 1243 1241

+9 -9

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

··· 890 890 ret = vmw_user_dmabuf_lookup(sw_context->fp->tfile, handle, &vmw_bo); 891 891 if (unlikely(ret != 0)) { 892 892 DRM_ERROR("Could not find or use MOB buffer.\n"); 893 - return -EINVAL; 893 + ret = -EINVAL; 894 + goto out_no_reloc; 894 895 } 895 896 bo = &vmw_bo->base; 896 897 ··· 915 914 916 915 out_no_reloc: 917 916 vmw_dmabuf_unreference(&vmw_bo); 918 - vmw_bo_p = NULL; 917 + *vmw_bo_p = NULL; 919 918 return ret; 920 919 } 921 920 ··· 952 951 ret = vmw_user_dmabuf_lookup(sw_context->fp->tfile, handle, &vmw_bo); 953 952 if (unlikely(ret != 0)) { 954 953 DRM_ERROR("Could not find or use GMR region.\n"); 955 - return -EINVAL; 954 + ret = -EINVAL; 955 + goto out_no_reloc; 956 956 } 957 957 bo = &vmw_bo->base; 958 958 ··· 976 974 977 975 out_no_reloc: 978 976 vmw_dmabuf_unreference(&vmw_bo); 979 - vmw_bo_p = NULL; 977 + *vmw_bo_p = NULL; 980 978 return ret; 981 979 } 982 980 ··· 2782 2780 NULL, arg->command_size, arg->throttle_us, 2783 2781 (void __user *)(unsigned long)arg->fence_rep, 2784 2782 NULL); 2785 - 2783 + ttm_read_unlock(&dev_priv->reservation_sem); 2786 2784 if (unlikely(ret != 0)) 2787 - goto out_unlock; 2785 + return ret; 2788 2786 2789 2787 vmw_kms_cursor_post_execbuf(dev_priv); 2790 2788 2791 - out_unlock: 2792 - ttm_read_unlock(&dev_priv->reservation_sem); 2793 - return ret; 2789 + return 0; 2794 2790 }

+3 -11

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

··· 2033 2033 int i; 2034 2034 struct drm_mode_config *mode_config = &dev->mode_config; 2035 2035 2036 - ret = ttm_read_lock(&dev_priv->reservation_sem, true); 2037 - if (unlikely(ret != 0)) 2038 - return ret; 2039 - 2040 2036 if (!arg->num_outputs) { 2041 2037 struct drm_vmw_rect def_rect = {0, 0, 800, 600}; 2042 2038 vmw_du_update_layout(dev_priv, 1, &def_rect); 2043 - goto out_unlock; 2039 + return 0; 2044 2040 } 2045 2041 2046 2042 rects_size = arg->num_outputs * sizeof(struct drm_vmw_rect); 2047 2043 rects = kcalloc(arg->num_outputs, sizeof(struct drm_vmw_rect), 2048 2044 GFP_KERNEL); 2049 - if (unlikely(!rects)) { 2050 - ret = -ENOMEM; 2051 - goto out_unlock; 2052 - } 2045 + if (unlikely(!rects)) 2046 + return -ENOMEM; 2053 2047 2054 2048 user_rects = (void __user *)(unsigned long)arg->rects; 2055 2049 ret = copy_from_user(rects, user_rects, rects_size); ··· 2068 2074 2069 2075 out_free: 2070 2076 kfree(rects); 2071 - out_unlock: 2072 - ttm_read_unlock(&dev_priv->reservation_sem); 2073 2077 return ret; 2074 2078 }

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