Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'pci-v6.15-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci
Pull pci updates from Bjorn Helgaas:
"Enumeration:
- Enable Configuration RRS SV, which makes device readiness visible,
early instead of during child bus scanning (Bjorn Helgaas)
- Log debug messages about reset methods being used (Bjorn Helgaas)
- Avoid reset when it has been disabled via sysfs (Nishanth
Aravamudan)
- Add common pci-ep-bus.yaml schema for exporting several peripherals
of a single PCI function via devicetree (Andrea della Porta)
- Create DT nodes for PCI host bridges to enable loading device tree
overlays to create platform devices for PCI devices that have
several features that require multiple drivers (Herve Codina)
Resource management:
- Enlarge devres table[] to accommodate bridge windows, ROM, IOV
BARs, etc., and validate BAR index in devres interfaces (Philipp
Stanner)
- Fix typo that repeatedly distributed resources to a bridge instead
of iterating over subordinate bridges, which resulted in too little
space to assign some BARs (Kai-Heng Feng)
- Relax bridge window tail sizing for optional resources, e.g., IOV
BARs, to avoid failures when removing and re-adding devices (Ilpo
Järvinen)
- Allow drivers to enable devices even if we haven't assigned
optional IOV resources to them (Ilpo Järvinen)
- Rework handling of optional resources (IOV BARs, ROMs) to reduce
failures if we can't allocate them (Ilpo Järvinen)
- Fix a NULL dereference in the SR-IOV VF creation error path (Shay
Drory)
- Fix s390 mmio_read/write syscalls, which didn't cause page faults
in some cases, which broke vfio-pci lazy mapping on first access
(Niklas Schnelle)
- Add pdev->non_mappable_bars to replace CONFIG_VFIO_PCI_MMAP, which
was disabled only for s390 (Niklas Schnelle)
- Support mmap of PCI resources on s390 except for ISM devices
(Niklas Schnelle)
ASPM:
- Delay pcie_link_state deallocation to avoid dangling pointers that
cause invalid references during hot-unplug (Daniel Stodden)
Power management:
- Allow PCI bridges to go to D3Hot when suspending on all non-x86
systems (Manivannan Sadhasivam)
Power control:
- Create pwrctrl devices in pci_scan_device() to make it more
symmetric with pci_pwrctrl_unregister() and make pwrctrl devices
for PCI bridges possible (Manivannan Sadhasivam)
- Unregister pwrctrl devices in pci_destroy_dev() so DOE, ASPM, etc.
can still access devices after pci_stop_dev() (Manivannan
Sadhasivam)
- If there's a pwrctrl device for a PCI device, skip scanning it
because the pwrctrl core will rescan the bus after the device is
powered on (Manivannan Sadhasivam)
- Add a pwrctrl driver for PCI slots based on voltage regulators
described via devicetree (Manivannan Sadhasivam)
Bandwidth control:
- Add set_pcie_speed.sh to TEST_PROGS to fix issue when executing the
set_pcie_cooling_state.sh test case (Yi Lai)
- Avoid a NULL pointer dereference when we run out of bus numbers to
assign for a bridge secondary bus (Lukas Wunner)
Hotplug:
- Drop superfluous pci_hotplug_slot_list, try_module_get() calls, and
NULL pointer checks (Lukas Wunner)
- Drop shpchp module init/exit logging, replace shpchp dbg() with
ctrl_dbg(), and remove unused dbg(), err(), info(), warn() wrappers
(Ilpo Järvinen)
- Drop 'shpchp_debug' module parameter in favor of standard dynamic
debugging (Ilpo Järvinen)
- Drop unused cpcihp .get_power(), .set_power() function pointers
(Guilherme Giacomo Simoes)
- Disable hotplug interrupts in portdrv only when pciehp is not
enabled to avoid issuing two hotplug commands too close together
(Feng Tang)
- Skip pciehp 'device replaced' check if the device has been removed
to address a deadlock when resuming after a device was removed
during system sleep (Lukas Wunner)
- Don't enable pciehp hotplug interupt when resuming in poll mode
(Ilpo Järvinen)
Virtualization:
- Fix bugs in 'pci=config_acs=' kernel command line parameter (Tushar
Dave)
DOE:
- Expose supported DOE features via sysfs (Alistair Francis)
- Allow DOE support to be enabled even if CXL isn't enabled (Alistair
Francis)
Endpoint framework:
- Convert PCI device data so pci-epf-test works correctly on
big-endian endpoint systems (Niklas Cassel)
- Add BAR_RESIZABLE type to endpoint framework and add DWC core
support for EPF drivers to set BAR_RESIZABLE type and size (Niklas
Cassel)
- Fix pci-epf-test double free that causes an oops if the host
reboots and PERST# deassertion restarts endpoint BAR allocation
(Christian Bruel)
- Fix endpoint BAR testing so tests can skip disabled BARs instead of
reporting them as failures (Niklas Cassel)
- Widen endpoint test BAR size variable to accommodate BARs larger
than INT_MAX (Niklas Cassel)
- Remove unused tools 'pci' build target left over after moving tests
to tools/testing/selftests/pci_endpoint (Jianfeng Liu)
Altera PCIe controller driver:
- Add DT binding and driver support for Agilex family (P-Tile,
F-Tile, R-Tile) (Matthew Gerlach and D M, Sharath Kumar)
AMD MDB PCIe controller driver:
- Add DT binding and driver for AMD MDB (Multimedia DMA Bridge)
(Thippeswamy Havalige)
Broadcom STB PCIe controller driver:
- Add BCM2712 MSI-X DT binding and interrupt controller drivers and
add softdep on irq_bcm2712_mip driver to ensure that it is loaded
first (Stanimir Varbanov)
- Expand inbound window map to 64GB so it can accommodate BCM2712
(Stanimir Varbanov)
- Add BCM2712 support and DT updates (Stanimir Varbanov)
- Apply link speed restriction before bringing link up, not after
(Jim Quinlan)
- Update Max Link Speed in Link Capabilities via the internal
writable register, not the read-only config register (Jim Quinlan)
- Handle regulator_bulk_get() error to avoid panic when we call
regulator_bulk_free() later (Jim Quinlan)
- Disable regulators only when removing the bus immediately below a
Root Port because we don't support regulators deeper in the
hierarchy (Jim Quinlan)
- Make const read-only arrays static (Colin Ian King)
Cadence PCIe endpoint driver:
- Correct MSG TLP generation so endpoints can generate INTx messages
(Hans Zhang)
Freescale i.MX6 PCIe controller driver:
- Identify the second controller on i.MX8MQ based on devicetree
'linux,pci-domain' instead of DBI 'reg' address (Richard Zhu)
- Remove imx_pcie_cpu_addr_fixup() since dwc core can now derive the
ATU input address (using parent_bus_offset) from devicetree (Frank
Li)
Freescale Layerscape PCIe controller driver:
- Drop deprecated 'num-ib-windows' and 'num-ob-windows' and
unnecessary 'status' from example (Krzysztof Kozlowski)
- Correct the syscon_regmap_lookup_by_phandle_args("fsl,pcie-scfg")
arg_count to fix probe failure on LS1043A (Ioana Ciornei)
HiSilicon STB PCIe controller driver:
- Call phy_exit() to clean up if histb_pcie_probe() fails (Christophe
JAILLET)
Intel Gateway PCIe controller driver:
- Remove intel_pcie_cpu_addr() since dwc core can now derive the ATU
input address (using parent_bus_offset) from devicetree (Frank Li)
Intel VMD host bridge driver:
- Convert vmd_dev.cfg_lock from spinlock_t to raw_spinlock_t so
pci_ops.read() will never sleep, even on PREEMPT_RT where
spinlock_t becomes a sleepable lock, to avoid calling a sleeping
function from invalid context (Ryo Takakura)
MediaTek PCIe Gen3 controller driver:
- Remove leftover mac_reset assert for Airoha EN7581 SoC (Lorenzo
Bianconi)
- Add EN7581 PBUS controller 'mediatek,pbus-csr' DT property and
program host bridge memory aperture to this syscon node (Lorenzo
Bianconi)
Qualcomm PCIe controller driver:
- Add qcom,pcie-ipq5332 binding (Varadarajan Narayanan)
- Add qcom i.MX8QM and i.MX8QXP/DXP optional DMA interrupt (Alexander
Stein)
- Add optional dma-coherent DT property for Qualcomm SA8775P (Dmitry
Baryshkov)
- Make DT iommu property required for SA8775P and prohibited for
SDX55 (Dmitry Baryshkov)
- Add DT IOMMU and DMA-related properties for Qualcomm SM8450 (Dmitry
Baryshkov)
- Add endpoint DT properties for SAR2130P and enable endpoint mode in
driver (Dmitry Baryshkov)
- Describe endpoint BAR0 and BAR2 as 64-bit only and BAR1 and BAR3 as
RESERVED (Manivannan Sadhasivam)
Rockchip DesignWare PCIe controller driver:
- Describe rk3568 and rk3588 BARs as Resizable, not Fixed (Niklas
Cassel)
Synopsys DesignWare PCIe controller driver:
- Add debugfs-based Silicon Debug, Error Injection, Statistical
Counter support for DWC (Shradha Todi)
- Add debugfs property to expose LTSSM status of DWC PCIe link (Hans
Zhang)
- Add Rockchip support for DWC debugfs features (Niklas Cassel)
- Add dw_pcie_parent_bus_offset() to look up the parent bus address
of a specified 'reg' property and return the offset from the CPU
physical address (Frank Li)
- Use dw_pcie_parent_bus_offset() to derive CPU -> ATU addr offset
via 'reg[config]' for host controllers and 'reg[addr_space]' for
endpoint controllers (Frank Li)
- Apply struct dw_pcie.parent_bus_offset in ATU users to remove use
of .cpu_addr_fixup() when programming ATU (Frank Li)
TI J721E PCIe driver:
- Correct the 'link down' interrupt bit for J784S4 (Siddharth
Vadapalli)
TI Keystone PCIe controller driver:
- Describe AM65x BARs 2 and 5 as Resizable (not Fixed) and reduce
alignment requirement from 1MB to 64KB (Niklas Cassel)
Xilinx Versal CPM PCIe controller driver:
- Free IRQ domain in probe error path to avoid leaking it
(Thippeswamy Havalige)
- Add DT .compatible "xlnx,versal-cpm5nc-host" and driver support for
Versal Net CPM5NC Root Port controller (Thippeswamy Havalige)
- Add driver support for CPM5_HOST1 (Thippeswamy Havalige)
Miscellaneous:
- Convert fsl,mpc83xx-pcie binding to YAML (J. Neuschäfer)
- Use for_each_available_child_of_node_scoped() to simplify apple,
kirin, mediatek, mt7621, tegra drivers (Zhang Zekun)"
* tag 'pci-v6.15-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci: (197 commits)
PCI: layerscape: Fix arg_count to syscon_regmap_lookup_by_phandle_args()
PCI: j721e: Fix the value of .linkdown_irq_regfield for J784S4
misc: pci_endpoint_test: Add support for PCITEST_IRQ_TYPE_AUTO
PCI: endpoint: pci-epf-test: Expose supported IRQ types in CAPS register
PCI: dw-rockchip: Endpoint mode cannot raise INTx interrupts
PCI: endpoint: Add intx_capable to epc_features struct
dt-bindings: PCI: Add common schema for devices accessible through PCI BARs
PCI: intel-gw: Remove intel_pcie_cpu_addr()
PCI: imx6: Remove imx_pcie_cpu_addr_fixup()
PCI: dwc: Use parent_bus_offset to remove need for .cpu_addr_fixup()
PCI: dwc: ep: Ensure proper iteration over outbound map windows
PCI: dwc: ep: Use devicetree 'reg[addr_space]' to derive CPU -> ATU addr offset
PCI: dwc: ep: Consolidate devicetree handling in dw_pcie_ep_get_resources()
PCI: dwc: ep: Call epc_create() early in dw_pcie_ep_init()
PCI: dwc: Use devicetree 'reg[config]' to derive CPU -> ATU addr offset
PCI: dwc: Add dw_pcie_parent_bus_offset() checking and debug
PCI: dwc: Add dw_pcie_parent_bus_offset()
PCI/bwctrl: Fix NULL pointer dereference on bus number exhaustion
PCI: xilinx-cpm: Add cpm_csr register mapping for CPM5_HOST1 variant
PCI: brcmstb: Make const read-only arrays static
...
+5062
-1464
+157
Documentation/ABI/testing/debugfs-dwc-pcie
+157
Documentation/ABI/testing/debugfs-dwc-pcie
···
1
+
What: /sys/kernel/debug/dwc_pcie_<dev>/rasdes_debug/lane_detect
2
+
Date: February 2025
3
+
Contact: Shradha Todi <shradha.t@samsung.com>
4
+
Description: (RW) Write the lane number to be checked for detection. Read
5
+
will return whether PHY indicates receiver detection on the
6
+
selected lane. The default selected lane is Lane0.
7
+
8
+
What: /sys/kernel/debug/dwc_pcie_<dev>/rasdes_debug/rx_valid
9
+
Date: February 2025
10
+
Contact: Shradha Todi <shradha.t@samsung.com>
11
+
Description: (RW) Write the lane number to be checked as valid or invalid.
12
+
Read will return the status of PIPE RXVALID signal of the
13
+
selected lane. The default selected lane is Lane0.
14
+
15
+
What: /sys/kernel/debug/dwc_pcie_<dev>/rasdes_err_inj/<error>
16
+
Date: February 2025
17
+
Contact: Shradha Todi <shradha.t@samsung.com>
18
+
Description: The "rasdes_err_inj" is a directory which can be used to inject
19
+
errors into the system. The possible errors that can be injected
20
+
are:
21
+
22
+
1) tx_lcrc - TLP LCRC error injection TX Path
23
+
2) b16_crc_dllp - 16b CRC error injection of ACK/NAK DLLP
24
+
3) b16_crc_upd_fc - 16b CRC error injection of Update-FC DLLP
25
+
4) tx_ecrc - TLP ECRC error injection TX Path
26
+
5) fcrc_tlp - TLP's FCRC error injection TX Path
27
+
6) parity_tsos - Parity error of TSOS
28
+
7) parity_skpos - Parity error on SKPOS
29
+
8) rx_lcrc - LCRC error injection RX Path
30
+
9) rx_ecrc - ECRC error injection RX Path
31
+
10) tlp_err_seq - TLPs SEQ# error
32
+
11) ack_nak_dllp_seq - DLLPS ACK/NAK SEQ# error
33
+
12) ack_nak_dllp - ACK/NAK DLLPs transmission block
34
+
13) upd_fc_dllp - UpdateFC DLLPs transmission block
35
+
14) nak_dllp - Always transmission for NAK DLLP
36
+
15) inv_sync_hdr_sym - Invert SYNC header
37
+
16) com_pad_ts1 - COM/PAD TS1 order set
38
+
17) com_pad_ts2 - COM/PAD TS2 order set
39
+
18) com_fts - COM/FTS FTS order set
40
+
19) com_idl - COM/IDL E-idle order set
41
+
20) end_edb - END/EDB symbol
42
+
21) stp_sdp - STP/SDP symbol
43
+
22) com_skp - COM/SKP SKP order set
44
+
23) posted_tlp_hdr - Posted TLP Header credit value control
45
+
24) non_post_tlp_hdr - Non-Posted TLP Header credit value control
46
+
25) cmpl_tlp_hdr - Completion TLP Header credit value control
47
+
26) posted_tlp_data - Posted TLP Data credit value control
48
+
27) non_post_tlp_data - Non-Posted TLP Data credit value control
49
+
28) cmpl_tlp_data - Completion TLP Data credit value control
50
+
29) duplicate_tlp - Generates duplicate TLPs
51
+
30) nullified_tlp - Generates Nullified TLPs
52
+
53
+
(WO) Write to the attribute will prepare controller to inject
54
+
the respective error in the next transmission of data.
55
+
56
+
Parameter required to write will change in the following ways:
57
+
58
+
- Errors 9 and 10 are sequence errors. The write command:
59
+
60
+
echo <count> <diff> > /sys/kernel/debug/dwc_pcie_<dev>/rasdes_err_inj/<error>
61
+
62
+
<count>
63
+
Number of errors to be injected
64
+
<diff>
65
+
The difference to add or subtract from natural
66
+
sequence number to generate sequence error.
67
+
Allowed range from -4095 to 4095
68
+
69
+
- Errors 23 to 28 are credit value error insertions. The write
70
+
command:
71
+
72
+
echo <count> <diff> <vc> > /sys/kernel/debug/dwc_pcie_<dev>/rasdes_err_inj/<error>
73
+
74
+
<count>
75
+
Number of errors to be injected
76
+
<diff>
77
+
The difference to add or subtract from UpdateFC
78
+
credit value. Allowed range from -4095 to 4095
79
+
<vc>
80
+
Target VC number
81
+
82
+
- All other errors. The write command:
83
+
84
+
echo <count> > /sys/kernel/debug/dwc_pcie_<dev>/rasdes_err_inj/<error>
85
+
86
+
<count>
87
+
Number of errors to be injected
88
+
89
+
What: /sys/kernel/debug/dwc_pcie_<dev>/rasdes_event_counters/<event>/counter_enable
90
+
Date: February 2025
91
+
Contact: Shradha Todi <shradha.t@samsung.com>
92
+
Description: The "rasdes_event_counters" is the directory which can be used
93
+
to collect statistical data about the number of times a certain
94
+
event has occurred in the controller. The list of possible
95
+
events are:
96
+
97
+
1) EBUF Overflow
98
+
2) EBUF Underrun
99
+
3) Decode Error
100
+
4) Running Disparity Error
101
+
5) SKP OS Parity Error
102
+
6) SYNC Header Error
103
+
7) Rx Valid De-assertion
104
+
8) CTL SKP OS Parity Error
105
+
9) 1st Retimer Parity Error
106
+
10) 2nd Retimer Parity Error
107
+
11) Margin CRC and Parity Error
108
+
12) Detect EI Infer
109
+
13) Receiver Error
110
+
14) RX Recovery Req
111
+
15) N_FTS Timeout
112
+
16) Framing Error
113
+
17) Deskew Error
114
+
18) Framing Error In L0
115
+
19) Deskew Uncompleted Error
116
+
20) Bad TLP
117
+
21) LCRC Error
118
+
22) Bad DLLP
119
+
23) Replay Number Rollover
120
+
24) Replay Timeout
121
+
25) Rx Nak DLLP
122
+
26) Tx Nak DLLP
123
+
27) Retry TLP
124
+
28) FC Timeout
125
+
29) Poisoned TLP
126
+
30) ECRC Error
127
+
31) Unsupported Request
128
+
32) Completer Abort
129
+
33) Completion Timeout
130
+
34) EBUF SKP Add
131
+
35) EBUF SKP Del
132
+
133
+
(RW) Write 1 to enable the event counter and write 0 to disable
134
+
the event counter. Read will return whether the counter is
135
+
currently enabled or disabled. Counter is disabled by default.
136
+
137
+
What: /sys/kernel/debug/dwc_pcie_<dev>/rasdes_event_counters/<event>/counter_value
138
+
Date: February 2025
139
+
Contact: Shradha Todi <shradha.t@samsung.com>
140
+
Description: (RO) Read will return the current value of the event counter.
141
+
To reset the counter, counter should be disabled first and then
142
+
enabled back using the "counter_enable" attribute.
143
+
144
+
What: /sys/kernel/debug/dwc_pcie_<dev>/rasdes_event_counters/<event>/lane_select
145
+
Date: February 2025
146
+
Contact: Shradha Todi <shradha.t@samsung.com>
147
+
Description: (RW) Some lanes in the event list are lane specific events.
148
+
These include events from 1 to 11, as well as, 34 and 35. Write
149
+
the lane number for which you wish the counter to be enabled,
150
+
disabled, or value dumped. Read will return the current
151
+
selected lane number. Lane0 is selected by default.
152
+
153
+
What: /sys/kernel/debug/dwc_pcie_<dev>/ltssm_status
154
+
Date: February 2025
155
+
Contact: Hans Zhang <18255117159@163.com>
156
+
Description: (RO) Read will return the current PCIe LTSSM state in both
157
+
string and raw value.
+29
Documentation/ABI/testing/sysfs-bus-pci
+29
Documentation/ABI/testing/sysfs-bus-pci
···
583
583
enclosure-specific indications "specific0" to "specific7",
584
584
hence the corresponding led class devices are unavailable if
585
585
the DSM interface is used.
586
+
587
+
What: /sys/bus/pci/devices/.../doe_features
588
+
Date: March 2025
589
+
Contact: Linux PCI developers <linux-pci@vger.kernel.org>
590
+
Description:
591
+
This directory contains a list of the supported Data Object
592
+
Exchange (DOE) features. The features are the file name.
593
+
The contents of each file is the raw Vendor ID and data
594
+
object feature values.
595
+
596
+
The value comes from the device and specifies the vendor and
597
+
data object type supported. The lower (RHS of the colon) is
598
+
the data object type in hex. The upper (LHS of the colon)
599
+
is the vendor ID.
600
+
601
+
As all DOE devices must support the DOE discovery feature,
602
+
if DOE is supported you will at least see the doe_discovery
603
+
file, with this contents:
604
+
605
+
# cat doe_features/doe_discovery
606
+
0001:00
607
+
608
+
If the device supports other features you will see other
609
+
files as well. For example if CMA/SPDM and secure CMA/SPDM
610
+
are supported the doe_features directory will look like
611
+
this:
612
+
613
+
# ls doe_features
614
+
0001:01 0001:02 doe_discovery
+3
-4
Documentation/PCI/endpoint/pci-endpoint.rst
+3
-4
Documentation/PCI/endpoint/pci-endpoint.rst
···
57
57
The PCI controller driver can then create a new EPC device by invoking
58
58
devm_pci_epc_create()/pci_epc_create().
59
59
60
-
* devm_pci_epc_destroy()/pci_epc_destroy()
60
+
* pci_epc_destroy()
61
61
62
-
The PCI controller driver can destroy the EPC device created by either
63
-
devm_pci_epc_create() or pci_epc_create() using devm_pci_epc_destroy() or
64
-
pci_epc_destroy().
62
+
The PCI controller driver can destroy the EPC device created by
63
+
pci_epc_create() using pci_epc_destroy().
65
64
66
65
* pci_epc_linkup()
67
66
+60
Documentation/devicetree/bindings/interrupt-controller/brcm,bcm2712-msix.yaml
+60
Documentation/devicetree/bindings/interrupt-controller/brcm,bcm2712-msix.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/interrupt-controller/brcm,bcm2712-msix.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Broadcom bcm2712 MSI-X Interrupt Peripheral support
8
+
9
+
maintainers:
10
+
- Stanimir Varbanov <svarbanov@suse.de>
11
+
12
+
description:
13
+
This interrupt controller is used to provide interrupt vectors to the
14
+
generic interrupt controller (GIC) on bcm2712. It will be used as
15
+
external MSI-X controller for PCIe root complex.
16
+
17
+
allOf:
18
+
- $ref: /schemas/interrupt-controller/msi-controller.yaml#
19
+
20
+
properties:
21
+
compatible:
22
+
const: brcm,bcm2712-mip
23
+
24
+
reg:
25
+
items:
26
+
- description: Base register address
27
+
- description: PCIe message address
28
+
29
+
"#msi-cells":
30
+
const: 0
31
+
32
+
brcm,msi-offset:
33
+
$ref: /schemas/types.yaml#/definitions/uint32
34
+
description: Shift the allocated MSI's.
35
+
36
+
unevaluatedProperties: false
37
+
38
+
required:
39
+
- compatible
40
+
- reg
41
+
- msi-controller
42
+
- msi-ranges
43
+
44
+
examples:
45
+
- |
46
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
47
+
48
+
axi {
49
+
#address-cells = <2>;
50
+
#size-cells = <2>;
51
+
52
+
msi-controller@1000130000 {
53
+
compatible = "brcm,bcm2712-mip";
54
+
reg = <0x10 0x00130000 0x00 0xc0>,
55
+
<0xff 0xfffff000 0x00 0x1000>;
56
+
msi-controller;
57
+
#msi-cells = <0>;
58
+
msi-ranges = <&gicv2 GIC_SPI 128 IRQ_TYPE_EDGE_RISING 64>;
59
+
};
60
+
};
+10
Documentation/devicetree/bindings/pci/altr,pcie-root-port.yaml
+10
Documentation/devicetree/bindings/pci/altr,pcie-root-port.yaml
···
12
12
13
13
properties:
14
14
compatible:
15
+
description: Each family of socfpga has its own implementation of the
16
+
PCI controller. The altr,pcie-root-port-1.0 is used for the Cyclone5
17
+
family of chips. The Stratix10 family of chips is supported by the
18
+
altr,pcie-root-port-2.0. The Agilex family of chips has three,
19
+
non-register compatible, variants of PCIe Hard IP referred to as the
20
+
F-Tile, P-Tile, and R-Tile, depending on the specific chip instance.
21
+
15
22
enum:
16
23
- altr,pcie-root-port-1.0
17
24
- altr,pcie-root-port-2.0
25
+
- altr,pcie-root-port-3.0-f-tile
26
+
- altr,pcie-root-port-3.0-p-tile
27
+
- altr,pcie-root-port-3.0-r-tile
18
28
19
29
reg:
20
30
items:
+121
Documentation/devicetree/bindings/pci/amd,versal2-mdb-host.yaml
+121
Documentation/devicetree/bindings/pci/amd,versal2-mdb-host.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/pci/amd,versal2-mdb-host.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: AMD Versal2 MDB(Multimedia DMA Bridge) Host Controller
8
+
9
+
maintainers:
10
+
- Thippeswamy Havalige <thippeswamy.havalige@amd.com>
11
+
12
+
allOf:
13
+
- $ref: /schemas/pci/pci-host-bridge.yaml#
14
+
- $ref: /schemas/pci/snps,dw-pcie.yaml#
15
+
16
+
properties:
17
+
compatible:
18
+
const: amd,versal2-mdb-host
19
+
20
+
reg:
21
+
items:
22
+
- description: MDB System Level Control and Status Register (SLCR) Base
23
+
- description: configuration region
24
+
- description: data bus interface
25
+
- description: address translation unit register
26
+
27
+
reg-names:
28
+
items:
29
+
- const: slcr
30
+
- const: config
31
+
- const: dbi
32
+
- const: atu
33
+
34
+
ranges:
35
+
maxItems: 2
36
+
37
+
msi-map:
38
+
maxItems: 1
39
+
40
+
interrupts:
41
+
maxItems: 1
42
+
43
+
interrupt-map-mask:
44
+
items:
45
+
- const: 0
46
+
- const: 0
47
+
- const: 0
48
+
- const: 7
49
+
50
+
interrupt-map:
51
+
maxItems: 4
52
+
53
+
"#interrupt-cells":
54
+
const: 1
55
+
56
+
interrupt-controller:
57
+
description: identifies the node as an interrupt controller
58
+
type: object
59
+
additionalProperties: false
60
+
properties:
61
+
interrupt-controller: true
62
+
63
+
"#address-cells":
64
+
const: 0
65
+
66
+
"#interrupt-cells":
67
+
const: 1
68
+
69
+
required:
70
+
- interrupt-controller
71
+
- "#address-cells"
72
+
- "#interrupt-cells"
73
+
74
+
required:
75
+
- reg
76
+
- reg-names
77
+
- interrupts
78
+
- interrupt-map
79
+
- interrupt-map-mask
80
+
- msi-map
81
+
- "#interrupt-cells"
82
+
- interrupt-controller
83
+
84
+
unevaluatedProperties: false
85
+
86
+
examples:
87
+
- |
88
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
89
+
#include <dt-bindings/interrupt-controller/irq.h>
90
+
91
+
soc {
92
+
#address-cells = <2>;
93
+
#size-cells = <2>;
94
+
pcie@ed931000 {
95
+
compatible = "amd,versal2-mdb-host";
96
+
reg = <0x0 0xed931000 0x0 0x2000>,
97
+
<0x1000 0x100000 0x0 0xff00000>,
98
+
<0x1000 0x0 0x0 0x1000>,
99
+
<0x0 0xed860000 0x0 0x2000>;
100
+
reg-names = "slcr", "config", "dbi", "atu";
101
+
ranges = <0x2000000 0x00 0xa0000000 0x00 0xa0000000 0x00 0x10000000>,
102
+
<0x43000000 0x1100 0x00 0x1100 0x00 0x00 0x1000000>;
103
+
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
104
+
interrupt-parent = <&gic>;
105
+
interrupt-map-mask = <0 0 0 7>;
106
+
interrupt-map = <0 0 0 1 &pcie_intc_0 0>,
107
+
<0 0 0 2 &pcie_intc_0 1>,
108
+
<0 0 0 3 &pcie_intc_0 2>,
109
+
<0 0 0 4 &pcie_intc_0 3>;
110
+
msi-map = <0x0 &gic_its 0x00 0x10000>;
111
+
#address-cells = <3>;
112
+
#size-cells = <2>;
113
+
#interrupt-cells = <1>;
114
+
device_type = "pci";
115
+
pcie_intc_0: interrupt-controller {
116
+
#address-cells = <0>;
117
+
#interrupt-cells = <1>;
118
+
interrupt-controller;
119
+
};
120
+
};
121
+
};
+5
-1
Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
+5
-1
Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
···
14
14
items:
15
15
- enum:
16
16
- brcm,bcm2711-pcie # The Raspberry Pi 4
17
+
- brcm,bcm2712-pcie # Raspberry Pi 5
17
18
- brcm,bcm4908-pcie
18
19
- brcm,bcm7211-pcie # Broadcom STB version of RPi4
19
20
- brcm,bcm7216-pcie # Broadcom 7216 Arm
···
102
101
103
102
reset-names:
104
103
minItems: 1
105
-
maxItems: 3
104
+
items:
105
+
- enum: [perst, rescal]
106
+
- const: bridge
107
+
- const: swinit
106
108
107
109
required:
108
110
- compatible
+4
Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
+4
Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
···
47
47
maxItems: 5
48
48
49
49
interrupts:
50
+
minItems: 1
50
51
items:
51
52
- description: builtin MSI controller.
53
+
- description: builtin DMA controller.
52
54
53
55
interrupt-names:
56
+
minItems: 1
54
57
items:
55
58
- const: msi
59
+
- const: dma
56
60
57
61
reset-gpio:
58
62
description: Should specify the GPIO for controlling the PCI bus device
-3
Documentation/devicetree/bindings/pci/fsl,layerscape-pcie-ep.yaml
-3
Documentation/devicetree/bindings/pci/fsl,layerscape-pcie-ep.yaml
+113
Documentation/devicetree/bindings/pci/fsl,mpc8xxx-pci.yaml
+113
Documentation/devicetree/bindings/pci/fsl,mpc8xxx-pci.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
5
+
$id: http://devicetree.org/schemas/pci/fsl,mpc8xxx-pci.yaml#
6
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
7
+
8
+
title: Freescale MPC83xx PCI/PCI-X/PCIe controllers
9
+
10
+
description:
11
+
Binding for the PCI/PCI-X/PCIe host bridges on MPC8xxx SoCs
12
+
13
+
maintainers:
14
+
- J. Neuschäfer <j.neuschaefer@gmx.net>
15
+
16
+
allOf:
17
+
- $ref: /schemas/pci/pci-host-bridge.yaml#
18
+
19
+
properties:
20
+
compatible:
21
+
oneOf:
22
+
- enum:
23
+
- fsl,mpc8314-pcie
24
+
- fsl,mpc8349-pci
25
+
- fsl,mpc8540-pci
26
+
- fsl,mpc8548-pcie
27
+
- fsl,mpc8641-pcie
28
+
- items:
29
+
- enum:
30
+
- fsl,mpc8308-pcie
31
+
- fsl,mpc8315-pcie
32
+
- fsl,mpc8377-pcie
33
+
- fsl,mpc8378-pcie
34
+
- const: fsl,mpc8314-pcie
35
+
- items:
36
+
- const: fsl,mpc8360-pci
37
+
- const: fsl,mpc8349-pci
38
+
- items:
39
+
- const: fsl,mpc8540-pcix
40
+
- const: fsl,mpc8540-pci
41
+
42
+
reg:
43
+
minItems: 1
44
+
items:
45
+
- description: internal registers
46
+
- description: config space access registers
47
+
48
+
clock-frequency: true
49
+
50
+
interrupts:
51
+
items:
52
+
- description: Consolidated PCI interrupt
53
+
54
+
fsl,pci-agent-force-enum:
55
+
type: boolean
56
+
description:
57
+
Typically any Freescale PCI-X bridge hardware strapped into Agent mode is
58
+
prevented from enumerating the bus. The PrPMC form-factor requires all
59
+
mezzanines to be PCI-X Agents, but one per system may still enumerate the
60
+
bus.
61
+
62
+
This property allows a PCI-X bridge to be used for bus enumeration
63
+
despite being strapped into Agent mode.
64
+
65
+
required:
66
+
- reg
67
+
- compatible
68
+
69
+
unevaluatedProperties: false
70
+
71
+
examples:
72
+
- |
73
+
#include <dt-bindings/interrupt-controller/irq.h>
74
+
75
+
pcie@e0009000 {
76
+
compatible = "fsl,mpc8315-pcie", "fsl,mpc8314-pcie";
77
+
reg = <0xe0009000 0x00001000>;
78
+
ranges = <0x02000000 0 0xa0000000 0xa0000000 0 0x10000000
79
+
0x01000000 0 0x00000000 0xb1000000 0 0x00800000>;
80
+
#address-cells = <3>;
81
+
#size-cells = <2>;
82
+
#interrupt-cells = <1>;
83
+
device_type = "pci";
84
+
bus-range = <0 255>;
85
+
interrupt-map-mask = <0xf800 0 0 7>;
86
+
interrupt-map = <0 0 0 1 &ipic 1 IRQ_TYPE_LEVEL_LOW
87
+
0 0 0 2 &ipic 1 IRQ_TYPE_LEVEL_LOW
88
+
0 0 0 3 &ipic 1 IRQ_TYPE_LEVEL_LOW
89
+
0 0 0 4 &ipic 1 IRQ_TYPE_LEVEL_LOW>;
90
+
clock-frequency = <0>;
91
+
};
92
+
93
+
- |
94
+
pci@ef008000 {
95
+
compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
96
+
reg = <0xef008000 0x1000>;
97
+
ranges = <0x02000000 0 0x80000000 0x80000000 0 0x20000000
98
+
0x01000000 0 0x00000000 0xd0000000 0 0x01000000>;
99
+
#interrupt-cells = <1>;
100
+
#size-cells = <2>;
101
+
#address-cells = <3>;
102
+
device_type = "pci";
103
+
clock-frequency = <33333333>;
104
+
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
105
+
interrupt-map = </* IDSEL */
106
+
0xe000 0 0 1 &mpic 2 1
107
+
0xe000 0 0 2 &mpic 3 1>;
108
+
interrupts-extended = <&mpic 24 2>;
109
+
bus-range = <0 0>;
110
+
fsl,pci-agent-force-enum;
111
+
};
112
+
113
+
...
-27
Documentation/devicetree/bindings/pci/fsl,pci.txt
-27
Documentation/devicetree/bindings/pci/fsl,pci.txt
···
1
-
* Bus Enumeration by Freescale PCI-X Agent
2
-
3
-
Typically any Freescale PCI-X bridge hardware strapped into Agent mode
4
-
is prevented from enumerating the bus. The PrPMC form-factor requires
5
-
all mezzanines to be PCI-X Agents, but one per system may still
6
-
enumerate the bus.
7
-
8
-
The property defined below will allow a PCI-X bridge to be used for bus
9
-
enumeration despite being strapped into Agent mode.
10
-
11
-
Required properties:
12
-
- fsl,pci-agent-force-enum : There is no value associated with this
13
-
property. The property itself is treated as a boolean.
14
-
15
-
Example:
16
-
17
-
/* PCI-X bridge known to be PrPMC Monarch */
18
-
pci0: pci@ef008000 {
19
-
fsl,pci-agent-force-enum;
20
-
#interrupt-cells = <1>;
21
-
#size-cells = <2>;
22
-
#address-cells = <3>;
23
-
compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
24
-
device_type = "pci";
25
-
...
26
-
...
27
-
};
+17
Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
+17
Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
···
109
109
power-domains:
110
110
maxItems: 1
111
111
112
+
mediatek,pbus-csr:
113
+
$ref: /schemas/types.yaml#/definitions/phandle-array
114
+
items:
115
+
- items:
116
+
- description: phandle to pbus-csr syscon
117
+
- description: offset of pbus-csr base address register
118
+
- description: offset of pbus-csr base address mask register
119
+
description:
120
+
Phandle with two arguments to the syscon node used to detect if
121
+
a given address is accessible on PCIe controller.
122
+
112
123
'#interrupt-cells':
113
124
const: 1
114
125
···
179
168
minItems: 1
180
169
maxItems: 2
181
170
171
+
mediatek,pbus-csr: false
172
+
182
173
- if:
183
174
properties:
184
175
compatible:
···
210
197
minItems: 1
211
198
maxItems: 2
212
199
200
+
mediatek,pbus-csr: false
201
+
213
202
- if:
214
203
properties:
215
204
compatible:
···
238
223
reset-names:
239
224
minItems: 1
240
225
maxItems: 2
226
+
227
+
mediatek,pbus-csr: false
241
228
242
229
- if:
243
230
properties:
+58
Documentation/devicetree/bindings/pci/pci-ep-bus.yaml
+58
Documentation/devicetree/bindings/pci/pci-ep-bus.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/pci/pci-ep-bus.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Common Properties for PCI MFD EP with Peripherals Addressable from BARs
8
+
9
+
maintainers:
10
+
- A. della Porta <andrea.porta@suse.com>
11
+
12
+
description:
13
+
Define a generic node representing a PCI endpoint which contains several sub-
14
+
peripherals. The peripherals can be accessed through one or more BARs.
15
+
This common schema is intended to be referenced from device tree bindings and
16
+
does not represent a device tree binding by itself.
17
+
18
+
properties:
19
+
'#address-cells':
20
+
const: 3
21
+
22
+
'#size-cells':
23
+
const: 2
24
+
25
+
ranges:
26
+
minItems: 1
27
+
maxItems: 6
28
+
items:
29
+
maxItems: 8
30
+
additionalItems: true
31
+
items:
32
+
- maximum: 5 # The BAR number
33
+
- const: 0
34
+
- const: 0
35
+
36
+
patternProperties:
37
+
'^pci-ep-bus@[0-5]$':
38
+
type: object
39
+
description:
40
+
One node for each BAR used by peripherals contained in the PCI endpoint.
41
+
Each node represents a bus on which peripherals are connected.
42
+
This allows for some segmentation, e.g., one peripheral is accessible
43
+
through BAR0 and another through BAR1, and you don't want the two
44
+
peripherals to be able to act on the other BAR. Alternatively, when
45
+
different peripherals need to share BARs, you can define only one node
46
+
and use a 'ranges' property to map all the used BARs.
47
+
48
+
additionalProperties: true
49
+
50
+
properties:
51
+
compatible:
52
+
const: simple-bus
53
+
54
+
required:
55
+
- compatible
56
+
57
+
additionalProperties: true
58
+
...
+74
-26
Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml
+74
-26
Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml
···
14
14
oneOf:
15
15
- enum:
16
16
- qcom,sa8775p-pcie-ep
17
+
- qcom,sar2130p-pcie-ep
17
18
- qcom,sdx55-pcie-ep
18
19
- qcom,sm8450-pcie-ep
19
20
- items:
···
45
44
46
45
clocks:
47
46
minItems: 5
48
-
maxItems: 8
47
+
maxItems: 9
49
48
50
49
clock-names:
51
50
minItems: 5
52
-
maxItems: 8
51
+
maxItems: 9
53
52
54
53
qcom,perst-regs:
55
54
description: Reference to a syscon representing TCSR followed by the two
···
76
75
- const: doorbell
77
76
- const: dma
78
77
78
+
iommus:
79
+
maxItems: 1
80
+
79
81
reset-gpios:
80
82
description: GPIO used as PERST# input signal
81
83
maxItems: 1
···
94
90
items:
95
91
- const: pcie-mem
96
92
- const: cpu-pcie
93
+
94
+
dma-coherent: true
97
95
98
96
resets:
99
97
maxItems: 1
···
132
126
133
127
allOf:
134
128
- $ref: pci-ep.yaml#
129
+
130
+
- if:
131
+
properties:
132
+
compatible:
133
+
contains:
134
+
enum:
135
+
- qcom,sar2130p-pcie-ep
136
+
then:
137
+
properties:
138
+
clocks:
139
+
items:
140
+
- description: PCIe Auxiliary clock
141
+
- description: PCIe CFG AHB clock
142
+
- description: PCIe Master AXI clock
143
+
- description: PCIe Slave AXI clock
144
+
- description: PCIe Slave Q2A AXI clock
145
+
- description: PCIe DDRSS SF TBU clock
146
+
- description: PCIe AGGRE NOC AXI clock
147
+
- description: PCIe CFG NOC AXI clock
148
+
- description: PCIe QMIP AHB clock
149
+
clock-names:
150
+
items:
151
+
- const: aux
152
+
- const: cfg
153
+
- const: bus_master
154
+
- const: bus_slave
155
+
- const: slave_q2a
156
+
- const: ddrss_sf_tbu
157
+
- const: aggre_noc_axi
158
+
- const: cnoc_sf_axi
159
+
- const: qmip_pcie_ahb
160
+
135
161
- if:
136
162
properties:
137
163
compatible:
···
173
135
then:
174
136
properties:
175
137
reg:
138
+
minItems: 6
176
139
maxItems: 6
177
140
reg-names:
141
+
minItems: 6
178
142
maxItems: 6
143
+
interrupts:
144
+
minItems: 2
145
+
maxItems: 2
146
+
interrupt-names:
147
+
minItems: 2
148
+
maxItems: 2
149
+
iommus: false
150
+
else:
151
+
properties:
152
+
reg:
153
+
minItems: 7
154
+
maxItems: 7
155
+
reg-names:
156
+
minItems: 7
157
+
maxItems: 7
158
+
interrupts:
159
+
minItems: 3
160
+
maxItems: 3
161
+
interrupt-names:
162
+
minItems: 3
163
+
maxItems: 3
164
+
required:
165
+
- iommus
166
+
167
+
- if:
168
+
properties:
169
+
compatible:
170
+
contains:
171
+
enum:
172
+
- qcom,sdx55-pcie-ep
173
+
then:
174
+
properties:
179
175
clocks:
180
176
items:
181
177
- description: PCIe Auxiliary clock
···
228
156
- const: slave_q2a
229
157
- const: sleep
230
158
- const: ref
231
-
interrupts:
232
-
maxItems: 2
233
-
interrupt-names:
234
-
maxItems: 2
235
159
236
160
- if:
237
161
properties:
···
237
169
- qcom,sm8450-pcie-ep
238
170
then:
239
171
properties:
240
-
reg:
241
-
maxItems: 6
242
-
reg-names:
243
-
maxItems: 6
244
172
clocks:
245
173
items:
246
174
- description: PCIe Auxiliary clock
···
257
193
- const: ref
258
194
- const: ddrss_sf_tbu
259
195
- const: aggre_noc_axi
260
-
interrupts:
261
-
maxItems: 2
262
-
interrupt-names:
263
-
maxItems: 2
264
196
265
197
- if:
266
198
properties:
···
266
206
- qcom,sa8775p-pcie-ep
267
207
then:
268
208
properties:
269
-
reg:
270
-
minItems: 7
271
-
maxItems: 7
272
-
reg-names:
273
-
minItems: 7
274
-
maxItems: 7
275
209
clocks:
276
210
items:
277
211
- description: PCIe Auxiliary clock
···
280
226
- const: bus_master
281
227
- const: bus_slave
282
228
- const: slave_q2a
283
-
interrupts:
284
-
minItems: 3
285
-
maxItems: 3
286
-
interrupt-names:
287
-
minItems: 3
288
-
maxItems: 3
289
229
290
230
unevaluatedProperties: false
291
231
+6
-2
Documentation/devicetree/bindings/pci/qcom,pcie.yaml
+6
-2
Documentation/devicetree/bindings/pci/qcom,pcie.yaml
···
33
33
- qcom,pcie-sdx55
34
34
- items:
35
35
- enum:
36
+
- qcom,pcie-ipq5332
36
37
- qcom,pcie-ipq5424
37
38
- const: qcom,pcie-ipq9574
38
39
- items:
···
50
49
51
50
interrupts:
52
51
minItems: 1
53
-
maxItems: 8
52
+
maxItems: 9
54
53
55
54
interrupt-names:
56
55
minItems: 1
57
-
maxItems: 8
56
+
maxItems: 9
58
57
59
58
iommu-map:
60
59
minItems: 1
···
444
443
interrupts:
445
444
minItems: 8
446
445
interrupt-names:
446
+
minItems: 8
447
447
items:
448
448
- const: msi0
449
449
- const: msi1
···
454
452
- const: msi5
455
453
- const: msi6
456
454
- const: msi7
455
+
- const: global
457
456
458
457
- if:
459
458
properties:
···
602
599
- properties:
603
600
interrupts:
604
601
minItems: 8
602
+
maxItems: 8
605
603
interrupt-names:
606
604
items:
607
605
- const: msi0
+2
Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml
+2
Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml
+1
Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml
+1
Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml
+1
-1
Documentation/devicetree/bindings/vendor-prefixes.yaml
+1
-1
Documentation/devicetree/bindings/vendor-prefixes.yaml
···
18
18
# DO NOT ADD NEW PROPERTIES TO THIS LIST
19
19
"^(at25|bm|devbus|dmacap|dsa|exynos|fsi[ab]|gpio-fan|gpio-key|gpio|gpmc|hdmi|i2c-gpio),.*": true
20
20
"^(keypad|m25p|max8952|max8997|max8998|mpmc),.*": true
21
-
"^(pinctrl-single|#pinctrl-single|PowerPC),.*": true
21
+
"^(pciclass|pinctrl-single|#pinctrl-single|PowerPC),.*": true
22
22
"^(pl022|pxa-mmc|rcar_sound|rotary-encoder|s5m8767|sdhci),.*": true
23
23
"^(simple-audio-card|st-plgpio|st-spics|ts),.*": true
24
24
+1
MAINTAINERS
+1
MAINTAINERS
···
18340
18340
F: Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml
18341
18341
F: Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml
18342
18342
F: drivers/pci/controller/dwc/*designware*
18343
+
F: include/linux/pcie-dwc.h
18343
18344
18344
18345
PCI DRIVER FOR TI DRA7XX/J721E
18345
18346
M: Vignesh Raghavendra <vigneshr@ti.com>
+1
-3
arch/s390/Kconfig
+1
-3
arch/s390/Kconfig
···
41
41
config NO_IOPORT_MAP
42
42
def_bool y
43
43
44
-
config PCI_QUIRKS
45
-
def_bool n
46
-
47
44
config ARCH_SUPPORTS_UPROBES
48
45
def_bool y
49
46
···
256
259
select PCI_DOMAINS if PCI
257
260
select PCI_MSI if PCI
258
261
select PCI_MSI_ARCH_FALLBACKS if PCI_MSI
262
+
select PCI_QUIRKS if PCI
259
263
select SPARSE_IRQ
260
264
select SWIOTLB
261
265
select SYSCTL_EXCEPTION_TRACE
+3
arch/s390/include/asm/pci.h
+3
arch/s390/include/asm/pci.h
+1
-1
arch/s390/pci/Makefile
+1
-1
arch/s390/pci/Makefile
+23
arch/s390/pci/pci_fixup.c
+23
arch/s390/pci/pci_fixup.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* Exceptions for specific devices,
4
+
*
5
+
* Copyright IBM Corp. 2025
6
+
*
7
+
* Author(s):
8
+
* Niklas Schnelle <schnelle@linux.ibm.com>
9
+
*/
10
+
#include <linux/pci.h>
11
+
12
+
static void zpci_ism_bar_no_mmap(struct pci_dev *pdev)
13
+
{
14
+
/*
15
+
* ISM's BAR is special. Drivers written for ISM know
16
+
* how to handle this but others need to be aware of their
17
+
* special nature e.g. to prevent attempts to mmap() it.
18
+
*/
19
+
pdev->non_mappable_bars = 1;
20
+
}
21
+
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_IBM,
22
+
PCI_DEVICE_ID_IBM_ISM,
23
+
zpci_ism_bar_no_mmap);
+13
-5
arch/s390/pci/pci_mmio.c
+13
-5
arch/s390/pci/pci_mmio.c
···
175
175
args.address = mmio_addr;
176
176
args.vma = vma;
177
177
ret = follow_pfnmap_start(&args);
178
-
if (ret)
179
-
goto out_unlock_mmap;
178
+
if (ret) {
179
+
fixup_user_fault(current->mm, mmio_addr, FAULT_FLAG_WRITE, NULL);
180
+
ret = follow_pfnmap_start(&args);
181
+
if (ret)
182
+
goto out_unlock_mmap;
183
+
}
180
184
181
185
io_addr = (void __iomem *)((args.pfn << PAGE_SHIFT) |
182
186
(mmio_addr & ~PAGE_MASK));
···
319
315
if (!(vma->vm_flags & (VM_IO | VM_PFNMAP)))
320
316
goto out_unlock_mmap;
321
317
ret = -EACCES;
322
-
if (!(vma->vm_flags & VM_WRITE))
318
+
if (!(vma->vm_flags & VM_READ))
323
319
goto out_unlock_mmap;
324
320
325
321
args.vma = vma;
326
322
args.address = mmio_addr;
327
323
ret = follow_pfnmap_start(&args);
328
-
if (ret)
329
-
goto out_unlock_mmap;
324
+
if (ret) {
325
+
fixup_user_fault(current->mm, mmio_addr, 0, NULL);
326
+
ret = follow_pfnmap_start(&args);
327
+
if (ret)
328
+
goto out_unlock_mmap;
329
+
}
330
330
331
331
io_addr = (void __iomem *)((args.pfn << PAGE_SHIFT) |
332
332
(mmio_addr & ~PAGE_MASK));
+61
drivers/base/core.c
+61
drivers/base/core.c
···
5172
5172
EXPORT_SYMBOL_GPL(set_secondary_fwnode);
5173
5173
5174
5174
/**
5175
+
* device_remove_of_node - Remove an of_node from a device
5176
+
* @dev: device whose device tree node is being removed
5177
+
*/
5178
+
void device_remove_of_node(struct device *dev)
5179
+
{
5180
+
dev = get_device(dev);
5181
+
if (!dev)
5182
+
return;
5183
+
5184
+
if (!dev->of_node)
5185
+
goto end;
5186
+
5187
+
if (dev->fwnode == of_fwnode_handle(dev->of_node))
5188
+
dev->fwnode = NULL;
5189
+
5190
+
of_node_put(dev->of_node);
5191
+
dev->of_node = NULL;
5192
+
5193
+
end:
5194
+
put_device(dev);
5195
+
}
5196
+
EXPORT_SYMBOL_GPL(device_remove_of_node);
5197
+
5198
+
/**
5199
+
* device_add_of_node - Add an of_node to an existing device
5200
+
* @dev: device whose device tree node is being added
5201
+
* @of_node: of_node to add
5202
+
*
5203
+
* Return: 0 on success or error code on failure.
5204
+
*/
5205
+
int device_add_of_node(struct device *dev, struct device_node *of_node)
5206
+
{
5207
+
int ret;
5208
+
5209
+
if (!of_node)
5210
+
return -EINVAL;
5211
+
5212
+
dev = get_device(dev);
5213
+
if (!dev)
5214
+
return -EINVAL;
5215
+
5216
+
if (dev->of_node) {
5217
+
dev_err(dev, "Cannot replace node %pOF with %pOF\n",
5218
+
dev->of_node, of_node);
5219
+
ret = -EBUSY;
5220
+
goto end;
5221
+
}
5222
+
5223
+
dev->of_node = of_node_get(of_node);
5224
+
5225
+
if (!dev->fwnode)
5226
+
dev->fwnode = of_fwnode_handle(of_node);
5227
+
5228
+
ret = 0;
5229
+
end:
5230
+
put_device(dev);
5231
+
return ret;
5232
+
}
5233
+
EXPORT_SYMBOL_GPL(device_add_of_node);
5234
+
5235
+
/**
5175
5236
* device_set_of_node_from_dev - reuse device-tree node of another device
5176
5237
* @dev: device whose device-tree node is being set
5177
5238
* @dev2: device whose device-tree node is being reused
+16
drivers/irqchip/Kconfig
+16
drivers/irqchip/Kconfig
···
112
112
bool
113
113
select IRQ_DOMAIN
114
114
115
+
config BCM2712_MIP
116
+
tristate "Broadcom BCM2712 MSI-X Interrupt Peripheral support"
117
+
depends on ARCH_BRCMSTB || COMPILE_TEST
118
+
default m if ARCH_BRCMSTB
119
+
depends on ARM_GIC
120
+
select GENERIC_IRQ_CHIP
121
+
select IRQ_DOMAIN_HIERARCHY
122
+
select GENERIC_MSI_IRQ
123
+
select IRQ_MSI_LIB
124
+
help
125
+
Enable support for the Broadcom BCM2712 MSI-X target peripheral
126
+
(MIP) needed by brcmstb PCIe to handle MSI-X interrupts on
127
+
Raspberry Pi 5.
128
+
129
+
If unsure say n.
130
+
115
131
config BCM6345_L1_IRQ
116
132
bool
117
133
select GENERIC_IRQ_CHIP
+1
drivers/irqchip/Makefile
+1
drivers/irqchip/Makefile
···
63
63
obj-$(CONFIG_XILINX_INTC) += irq-xilinx-intc.o
64
64
obj-$(CONFIG_IRQ_CROSSBAR) += irq-crossbar.o
65
65
obj-$(CONFIG_SOC_VF610) += irq-vf610-mscm-ir.o
66
+
obj-$(CONFIG_BCM2712_MIP) += irq-bcm2712-mip.o
66
67
obj-$(CONFIG_BCM6345_L1_IRQ) += irq-bcm6345-l1.o
67
68
obj-$(CONFIG_BCM7038_L1_IRQ) += irq-bcm7038-l1.o
68
69
obj-$(CONFIG_BCM7120_L2_IRQ) += irq-bcm7120-l2.o
+292
drivers/irqchip/irq-bcm2712-mip.c
+292
drivers/irqchip/irq-bcm2712-mip.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/*
3
+
* Copyright (C) 2024 Raspberry Pi Ltd., All Rights Reserved.
4
+
* Copyright (c) 2024 SUSE
5
+
*/
6
+
7
+
#include <linux/bitmap.h>
8
+
#include <linux/irqchip.h>
9
+
#include <linux/irqdomain.h>
10
+
#include <linux/msi.h>
11
+
#include <linux/of_address.h>
12
+
#include <linux/of_platform.h>
13
+
14
+
#include "irq-msi-lib.h"
15
+
16
+
#define MIP_INT_RAISE 0x00
17
+
#define MIP_INT_CLEAR 0x10
18
+
#define MIP_INT_CFGL_HOST 0x20
19
+
#define MIP_INT_CFGH_HOST 0x30
20
+
#define MIP_INT_MASKL_HOST 0x40
21
+
#define MIP_INT_MASKH_HOST 0x50
22
+
#define MIP_INT_MASKL_VPU 0x60
23
+
#define MIP_INT_MASKH_VPU 0x70
24
+
#define MIP_INT_STATUSL_HOST 0x80
25
+
#define MIP_INT_STATUSH_HOST 0x90
26
+
#define MIP_INT_STATUSL_VPU 0xa0
27
+
#define MIP_INT_STATUSH_VPU 0xb0
28
+
29
+
/**
30
+
* struct mip_priv - MSI-X interrupt controller data
31
+
* @lock: Used to protect bitmap alloc/free
32
+
* @base: Base address of MMIO area
33
+
* @msg_addr: PCIe MSI-X address
34
+
* @msi_base: MSI base
35
+
* @num_msis: Count of MSIs
36
+
* @msi_offset: MSI offset
37
+
* @bitmap: A bitmap for hwirqs
38
+
* @parent: Parent domain (GIC)
39
+
* @dev: A device pointer
40
+
*/
41
+
struct mip_priv {
42
+
spinlock_t lock;
43
+
void __iomem *base;
44
+
u64 msg_addr;
45
+
u32 msi_base;
46
+
u32 num_msis;
47
+
u32 msi_offset;
48
+
unsigned long *bitmap;
49
+
struct irq_domain *parent;
50
+
struct device *dev;
51
+
};
52
+
53
+
static void mip_compose_msi_msg(struct irq_data *d, struct msi_msg *msg)
54
+
{
55
+
struct mip_priv *mip = irq_data_get_irq_chip_data(d);
56
+
57
+
msg->address_hi = upper_32_bits(mip->msg_addr);
58
+
msg->address_lo = lower_32_bits(mip->msg_addr);
59
+
msg->data = d->hwirq;
60
+
}
61
+
62
+
static struct irq_chip mip_middle_irq_chip = {
63
+
.name = "MIP",
64
+
.irq_mask = irq_chip_mask_parent,
65
+
.irq_unmask = irq_chip_unmask_parent,
66
+
.irq_eoi = irq_chip_eoi_parent,
67
+
.irq_set_affinity = irq_chip_set_affinity_parent,
68
+
.irq_set_type = irq_chip_set_type_parent,
69
+
.irq_compose_msi_msg = mip_compose_msi_msg,
70
+
};
71
+
72
+
static int mip_alloc_hwirq(struct mip_priv *mip, unsigned int nr_irqs)
73
+
{
74
+
guard(spinlock)(&mip->lock);
75
+
return bitmap_find_free_region(mip->bitmap, mip->num_msis, ilog2(nr_irqs));
76
+
}
77
+
78
+
static void mip_free_hwirq(struct mip_priv *mip, unsigned int hwirq,
79
+
unsigned int nr_irqs)
80
+
{
81
+
guard(spinlock)(&mip->lock);
82
+
bitmap_release_region(mip->bitmap, hwirq, ilog2(nr_irqs));
83
+
}
84
+
85
+
static int mip_middle_domain_alloc(struct irq_domain *domain, unsigned int virq,
86
+
unsigned int nr_irqs, void *arg)
87
+
{
88
+
struct mip_priv *mip = domain->host_data;
89
+
struct irq_fwspec fwspec = {0};
90
+
unsigned int hwirq, i;
91
+
struct irq_data *irqd;
92
+
int irq, ret;
93
+
94
+
irq = mip_alloc_hwirq(mip, nr_irqs);
95
+
if (irq < 0)
96
+
return irq;
97
+
98
+
hwirq = irq + mip->msi_offset;
99
+
100
+
fwspec.fwnode = domain->parent->fwnode;
101
+
fwspec.param_count = 3;
102
+
fwspec.param[0] = 0;
103
+
fwspec.param[1] = hwirq + mip->msi_base;
104
+
fwspec.param[2] = IRQ_TYPE_EDGE_RISING;
105
+
106
+
ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, &fwspec);
107
+
if (ret)
108
+
goto err_free_hwirq;
109
+
110
+
for (i = 0; i < nr_irqs; i++) {
111
+
irqd = irq_domain_get_irq_data(domain->parent, virq + i);
112
+
irqd->chip->irq_set_type(irqd, IRQ_TYPE_EDGE_RISING);
113
+
114
+
ret = irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
115
+
&mip_middle_irq_chip, mip);
116
+
if (ret)
117
+
goto err_free;
118
+
119
+
irqd = irq_get_irq_data(virq + i);
120
+
irqd_set_single_target(irqd);
121
+
irqd_set_affinity_on_activate(irqd);
122
+
}
123
+
124
+
return 0;
125
+
126
+
err_free:
127
+
irq_domain_free_irqs_parent(domain, virq, nr_irqs);
128
+
err_free_hwirq:
129
+
mip_free_hwirq(mip, irq, nr_irqs);
130
+
return ret;
131
+
}
132
+
133
+
static void mip_middle_domain_free(struct irq_domain *domain, unsigned int virq,
134
+
unsigned int nr_irqs)
135
+
{
136
+
struct irq_data *irqd = irq_domain_get_irq_data(domain, virq);
137
+
struct mip_priv *mip;
138
+
unsigned int hwirq;
139
+
140
+
if (!irqd)
141
+
return;
142
+
143
+
mip = irq_data_get_irq_chip_data(irqd);
144
+
hwirq = irqd_to_hwirq(irqd);
145
+
irq_domain_free_irqs_parent(domain, virq, nr_irqs);
146
+
mip_free_hwirq(mip, hwirq - mip->msi_offset, nr_irqs);
147
+
}
148
+
149
+
static const struct irq_domain_ops mip_middle_domain_ops = {
150
+
.select = msi_lib_irq_domain_select,
151
+
.alloc = mip_middle_domain_alloc,
152
+
.free = mip_middle_domain_free,
153
+
};
154
+
155
+
#define MIP_MSI_FLAGS_REQUIRED (MSI_FLAG_USE_DEF_DOM_OPS | \
156
+
MSI_FLAG_USE_DEF_CHIP_OPS | \
157
+
MSI_FLAG_PCI_MSI_MASK_PARENT)
158
+
159
+
#define MIP_MSI_FLAGS_SUPPORTED (MSI_GENERIC_FLAGS_MASK | \
160
+
MSI_FLAG_MULTI_PCI_MSI | \
161
+
MSI_FLAG_PCI_MSIX)
162
+
163
+
static const struct msi_parent_ops mip_msi_parent_ops = {
164
+
.supported_flags = MIP_MSI_FLAGS_SUPPORTED,
165
+
.required_flags = MIP_MSI_FLAGS_REQUIRED,
166
+
.bus_select_token = DOMAIN_BUS_GENERIC_MSI,
167
+
.bus_select_mask = MATCH_PCI_MSI,
168
+
.prefix = "MIP-MSI-",
169
+
.init_dev_msi_info = msi_lib_init_dev_msi_info,
170
+
};
171
+
172
+
static int mip_init_domains(struct mip_priv *mip, struct device_node *np)
173
+
{
174
+
struct irq_domain *middle;
175
+
176
+
middle = irq_domain_add_hierarchy(mip->parent, 0, mip->num_msis, np,
177
+
&mip_middle_domain_ops, mip);
178
+
if (!middle)
179
+
return -ENOMEM;
180
+
181
+
irq_domain_update_bus_token(middle, DOMAIN_BUS_GENERIC_MSI);
182
+
middle->dev = mip->dev;
183
+
middle->flags |= IRQ_DOMAIN_FLAG_MSI_PARENT;
184
+
middle->msi_parent_ops = &mip_msi_parent_ops;
185
+
186
+
/*
187
+
* All MSI-X unmasked for the host, masked for the VPU, and edge-triggered.
188
+
*/
189
+
writel(0, mip->base + MIP_INT_MASKL_HOST);
190
+
writel(0, mip->base + MIP_INT_MASKH_HOST);
191
+
writel(~0, mip->base + MIP_INT_MASKL_VPU);
192
+
writel(~0, mip->base + MIP_INT_MASKH_VPU);
193
+
writel(~0, mip->base + MIP_INT_CFGL_HOST);
194
+
writel(~0, mip->base + MIP_INT_CFGH_HOST);
195
+
196
+
return 0;
197
+
}
198
+
199
+
static int mip_parse_dt(struct mip_priv *mip, struct device_node *np)
200
+
{
201
+
struct of_phandle_args args;
202
+
u64 size;
203
+
int ret;
204
+
205
+
ret = of_property_read_u32(np, "brcm,msi-offset", &mip->msi_offset);
206
+
if (ret)
207
+
mip->msi_offset = 0;
208
+
209
+
ret = of_parse_phandle_with_args(np, "msi-ranges", "#interrupt-cells",
210
+
0, &args);
211
+
if (ret)
212
+
return ret;
213
+
214
+
ret = of_property_read_u32_index(np, "msi-ranges", args.args_count + 1,
215
+
&mip->num_msis);
216
+
if (ret)
217
+
goto err_put;
218
+
219
+
ret = of_property_read_reg(np, 1, &mip->msg_addr, &size);
220
+
if (ret)
221
+
goto err_put;
222
+
223
+
mip->msi_base = args.args[1];
224
+
225
+
mip->parent = irq_find_host(args.np);
226
+
if (!mip->parent)
227
+
ret = -EINVAL;
228
+
229
+
err_put:
230
+
of_node_put(args.np);
231
+
return ret;
232
+
}
233
+
234
+
static int __init mip_of_msi_init(struct device_node *node, struct device_node *parent)
235
+
{
236
+
struct platform_device *pdev;
237
+
struct mip_priv *mip;
238
+
int ret;
239
+
240
+
pdev = of_find_device_by_node(node);
241
+
of_node_put(node);
242
+
if (!pdev)
243
+
return -EPROBE_DEFER;
244
+
245
+
mip = kzalloc(sizeof(*mip), GFP_KERNEL);
246
+
if (!mip)
247
+
return -ENOMEM;
248
+
249
+
spin_lock_init(&mip->lock);
250
+
mip->dev = &pdev->dev;
251
+
252
+
ret = mip_parse_dt(mip, node);
253
+
if (ret)
254
+
goto err_priv;
255
+
256
+
mip->base = of_iomap(node, 0);
257
+
if (!mip->base) {
258
+
ret = -ENXIO;
259
+
goto err_priv;
260
+
}
261
+
262
+
mip->bitmap = bitmap_zalloc(mip->num_msis, GFP_KERNEL);
263
+
if (!mip->bitmap) {
264
+
ret = -ENOMEM;
265
+
goto err_base;
266
+
}
267
+
268
+
ret = mip_init_domains(mip, node);
269
+
if (ret)
270
+
goto err_map;
271
+
272
+
dev_dbg(&pdev->dev, "MIP: MSI-X count: %u, base: %u, offset: %u, msg_addr: %llx\n",
273
+
mip->num_msis, mip->msi_base, mip->msi_offset, mip->msg_addr);
274
+
275
+
return 0;
276
+
277
+
err_map:
278
+
bitmap_free(mip->bitmap);
279
+
err_base:
280
+
iounmap(mip->base);
281
+
err_priv:
282
+
kfree(mip);
283
+
return ret;
284
+
}
285
+
286
+
IRQCHIP_PLATFORM_DRIVER_BEGIN(mip_msi)
287
+
IRQCHIP_MATCH("brcm,bcm2712-mip", mip_of_msi_init)
288
+
IRQCHIP_PLATFORM_DRIVER_END(mip_msi)
289
+
MODULE_DESCRIPTION("Broadcom BCM2712 MSI-X interrupt controller");
290
+
MODULE_AUTHOR("Phil Elwell <phil@raspberrypi.com>");
291
+
MODULE_AUTHOR("Stanimir Varbanov <svarbanov@suse.de>");
292
+
MODULE_LICENSE("GPL");
+70
-61
drivers/misc/pci_endpoint_test.c
+70
-61
drivers/misc/pci_endpoint_test.c
···
28
28
29
29
#define DRV_MODULE_NAME "pci-endpoint-test"
30
30
31
-
#define IRQ_TYPE_UNDEFINED -1
32
-
#define IRQ_TYPE_INTX 0
33
-
#define IRQ_TYPE_MSI 1
34
-
#define IRQ_TYPE_MSIX 2
35
-
36
31
#define PCI_ENDPOINT_TEST_MAGIC 0x0
37
32
38
33
#define PCI_ENDPOINT_TEST_COMMAND 0x4
···
66
71
67
72
#define PCI_ENDPOINT_TEST_CAPS 0x30
68
73
#define CAP_UNALIGNED_ACCESS BIT(0)
74
+
#define CAP_MSI BIT(1)
75
+
#define CAP_MSIX BIT(2)
76
+
#define CAP_INTX BIT(3)
69
77
70
78
#define PCI_DEVICE_ID_TI_AM654 0xb00c
71
79
#define PCI_DEVICE_ID_TI_J7200 0xb00f
···
86
88
#define PCI_DEVICE_ID_RENESAS_R8A774E1 0x0025
87
89
#define PCI_DEVICE_ID_RENESAS_R8A779F0 0x0031
88
90
89
-
#define PCI_VENDOR_ID_ROCKCHIP 0x1d87
90
91
#define PCI_DEVICE_ID_ROCKCHIP_RK3588 0x3588
91
92
92
93
static DEFINE_IDA(pci_endpoint_test_ida);
93
94
94
95
#define to_endpoint_test(priv) container_of((priv), struct pci_endpoint_test, \
95
96
miscdev)
96
-
97
-
static bool no_msi;
98
-
module_param(no_msi, bool, 0444);
99
-
MODULE_PARM_DESC(no_msi, "Disable MSI interrupt in pci_endpoint_test");
100
-
101
-
static int irq_type = IRQ_TYPE_MSI;
102
-
module_param(irq_type, int, 0444);
103
-
MODULE_PARM_DESC(irq_type, "IRQ mode selection in pci_endpoint_test (0 - Legacy, 1 - MSI, 2 - MSI-X)");
104
97
105
98
enum pci_barno {
106
99
BAR_0,
···
115
126
struct miscdevice miscdev;
116
127
enum pci_barno test_reg_bar;
117
128
size_t alignment;
129
+
u32 ep_caps;
118
130
const char *name;
119
131
};
120
132
···
156
166
struct pci_dev *pdev = test->pdev;
157
167
158
168
pci_free_irq_vectors(pdev);
159
-
test->irq_type = IRQ_TYPE_UNDEFINED;
169
+
test->irq_type = PCITEST_IRQ_TYPE_UNDEFINED;
160
170
}
161
171
162
172
static int pci_endpoint_test_alloc_irq_vectors(struct pci_endpoint_test *test,
···
167
177
struct device *dev = &pdev->dev;
168
178
169
179
switch (type) {
170
-
case IRQ_TYPE_INTX:
180
+
case PCITEST_IRQ_TYPE_INTX:
171
181
irq = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_INTX);
172
182
if (irq < 0) {
173
183
dev_err(dev, "Failed to get Legacy interrupt\n");
···
175
185
}
176
186
177
187
break;
178
-
case IRQ_TYPE_MSI:
188
+
case PCITEST_IRQ_TYPE_MSI:
179
189
irq = pci_alloc_irq_vectors(pdev, 1, 32, PCI_IRQ_MSI);
180
190
if (irq < 0) {
181
191
dev_err(dev, "Failed to get MSI interrupts\n");
···
183
193
}
184
194
185
195
break;
186
-
case IRQ_TYPE_MSIX:
196
+
case PCITEST_IRQ_TYPE_MSIX:
187
197
irq = pci_alloc_irq_vectors(pdev, 1, 2048, PCI_IRQ_MSIX);
188
198
if (irq < 0) {
189
199
dev_err(dev, "Failed to get MSI-X interrupts\n");
···
206
216
{
207
217
int i;
208
218
struct pci_dev *pdev = test->pdev;
209
-
struct device *dev = &pdev->dev;
210
219
211
220
for (i = 0; i < test->num_irqs; i++)
212
-
devm_free_irq(dev, pci_irq_vector(pdev, i), test);
221
+
free_irq(pci_irq_vector(pdev, i), test);
213
222
214
223
test->num_irqs = 0;
215
224
}
···
221
232
struct device *dev = &pdev->dev;
222
233
223
234
for (i = 0; i < test->num_irqs; i++) {
224
-
ret = devm_request_irq(dev, pci_irq_vector(pdev, i),
225
-
pci_endpoint_test_irqhandler,
226
-
IRQF_SHARED, test->name, test);
235
+
ret = request_irq(pci_irq_vector(pdev, i),
236
+
pci_endpoint_test_irqhandler, IRQF_SHARED,
237
+
test->name, test);
227
238
if (ret)
228
239
goto fail;
229
240
}
···
231
242
return 0;
232
243
233
244
fail:
234
-
switch (irq_type) {
235
-
case IRQ_TYPE_INTX:
245
+
switch (test->irq_type) {
246
+
case PCITEST_IRQ_TYPE_INTX:
236
247
dev_err(dev, "Failed to request IRQ %d for Legacy\n",
237
248
pci_irq_vector(pdev, i));
238
249
break;
239
-
case IRQ_TYPE_MSI:
250
+
case PCITEST_IRQ_TYPE_MSI:
240
251
dev_err(dev, "Failed to request IRQ %d for MSI %d\n",
241
252
pci_irq_vector(pdev, i),
242
253
i + 1);
243
254
break;
244
-
case IRQ_TYPE_MSIX:
255
+
case PCITEST_IRQ_TYPE_MSIX:
245
256
dev_err(dev, "Failed to request IRQ %d for MSI-X %d\n",
246
257
pci_irq_vector(pdev, i),
247
258
i + 1);
248
259
break;
249
260
}
261
+
262
+
test->num_irqs = i;
263
+
pci_endpoint_test_release_irq(test);
250
264
251
265
return ret;
252
266
}
···
264
272
};
265
273
266
274
static int pci_endpoint_test_bar_memcmp(struct pci_endpoint_test *test,
267
-
enum pci_barno barno, int offset,
268
-
void *write_buf, void *read_buf,
269
-
int size)
275
+
enum pci_barno barno,
276
+
resource_size_t offset, void *write_buf,
277
+
void *read_buf, int size)
270
278
{
271
279
memset(write_buf, bar_test_pattern[barno], size);
272
280
memcpy_toio(test->bar[barno] + offset, write_buf, size);
···
279
287
static int pci_endpoint_test_bar(struct pci_endpoint_test *test,
280
288
enum pci_barno barno)
281
289
{
282
-
int j, bar_size, buf_size, iters;
290
+
resource_size_t bar_size, offset = 0;
283
291
void *write_buf __free(kfree) = NULL;
284
292
void *read_buf __free(kfree) = NULL;
285
293
struct pci_dev *pdev = test->pdev;
294
+
int buf_size;
295
+
296
+
bar_size = pci_resource_len(pdev, barno);
297
+
if (!bar_size)
298
+
return -ENODATA;
286
299
287
300
if (!test->bar[barno])
288
301
return -ENOMEM;
289
-
290
-
bar_size = pci_resource_len(pdev, barno);
291
302
292
303
if (barno == test->test_reg_bar)
293
304
bar_size = 0x4;
···
309
314
if (!read_buf)
310
315
return -ENOMEM;
311
316
312
-
iters = bar_size / buf_size;
313
-
for (j = 0; j < iters; j++)
314
-
if (pci_endpoint_test_bar_memcmp(test, barno, buf_size * j,
315
-
write_buf, read_buf, buf_size))
317
+
while (offset < bar_size) {
318
+
if (pci_endpoint_test_bar_memcmp(test, barno, offset, write_buf,
319
+
read_buf, buf_size))
316
320
return -EIO;
321
+
offset += buf_size;
322
+
}
317
323
318
324
return 0;
319
325
}
···
378
382
static int pci_endpoint_test_bars(struct pci_endpoint_test *test)
379
383
{
380
384
enum pci_barno bar;
381
-
bool ret;
385
+
int ret;
382
386
383
387
/* Write all BARs in order (without reading). */
384
388
for (bar = 0; bar < PCI_STD_NUM_BARS; bar++)
···
394
398
for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) {
395
399
if (test->bar[bar]) {
396
400
ret = pci_endpoint_test_bars_read_bar(test, bar);
397
-
if (!ret)
401
+
if (ret)
398
402
return ret;
399
403
}
400
404
}
···
407
411
u32 val;
408
412
409
413
pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_TYPE,
410
-
IRQ_TYPE_INTX);
414
+
PCITEST_IRQ_TYPE_INTX);
411
415
pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_NUMBER, 0);
412
416
pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
413
417
COMMAND_RAISE_INTX_IRQ);
···
427
431
int ret;
428
432
429
433
pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_TYPE,
430
-
msix ? IRQ_TYPE_MSIX : IRQ_TYPE_MSI);
434
+
msix ? PCITEST_IRQ_TYPE_MSIX :
435
+
PCITEST_IRQ_TYPE_MSI);
431
436
pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_NUMBER, msi_num);
432
437
pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
433
438
msix ? COMMAND_RAISE_MSIX_IRQ :
···
504
507
if (use_dma)
505
508
flags |= FLAG_USE_DMA;
506
509
507
-
if (irq_type < IRQ_TYPE_INTX || irq_type > IRQ_TYPE_MSIX) {
510
+
if (irq_type < PCITEST_IRQ_TYPE_INTX ||
511
+
irq_type > PCITEST_IRQ_TYPE_MSIX) {
508
512
dev_err(dev, "Invalid IRQ type option\n");
509
513
return -EINVAL;
510
514
}
···
637
639
if (use_dma)
638
640
flags |= FLAG_USE_DMA;
639
641
640
-
if (irq_type < IRQ_TYPE_INTX || irq_type > IRQ_TYPE_MSIX) {
642
+
if (irq_type < PCITEST_IRQ_TYPE_INTX ||
643
+
irq_type > PCITEST_IRQ_TYPE_MSIX) {
641
644
dev_err(dev, "Invalid IRQ type option\n");
642
645
return -EINVAL;
643
646
}
···
734
735
if (use_dma)
735
736
flags |= FLAG_USE_DMA;
736
737
737
-
if (irq_type < IRQ_TYPE_INTX || irq_type > IRQ_TYPE_MSIX) {
738
+
if (irq_type < PCITEST_IRQ_TYPE_INTX ||
739
+
irq_type > PCITEST_IRQ_TYPE_MSIX) {
738
740
dev_err(dev, "Invalid IRQ type option\n");
739
741
return -EINVAL;
740
742
}
···
805
805
struct device *dev = &pdev->dev;
806
806
int ret;
807
807
808
-
if (req_irq_type < IRQ_TYPE_INTX || req_irq_type > IRQ_TYPE_MSIX) {
808
+
if (req_irq_type < PCITEST_IRQ_TYPE_INTX ||
809
+
req_irq_type > PCITEST_IRQ_TYPE_AUTO) {
809
810
dev_err(dev, "Invalid IRQ type option\n");
810
811
return -EINVAL;
812
+
}
813
+
814
+
if (req_irq_type == PCITEST_IRQ_TYPE_AUTO) {
815
+
if (test->ep_caps & CAP_MSI)
816
+
req_irq_type = PCITEST_IRQ_TYPE_MSI;
817
+
else if (test->ep_caps & CAP_MSIX)
818
+
req_irq_type = PCITEST_IRQ_TYPE_MSIX;
819
+
else if (test->ep_caps & CAP_INTX)
820
+
req_irq_type = PCITEST_IRQ_TYPE_INTX;
821
+
else
822
+
/* fallback to MSI if no caps defined */
823
+
req_irq_type = PCITEST_IRQ_TYPE_MSI;
811
824
}
812
825
813
826
if (test->irq_type == req_irq_type)
···
887
874
ret = pci_endpoint_test_set_irq(test, arg);
888
875
break;
889
876
case PCITEST_GET_IRQTYPE:
890
-
ret = irq_type;
877
+
ret = test->irq_type;
891
878
break;
892
879
case PCITEST_CLEAR_IRQ:
893
880
ret = pci_endpoint_test_clear_irq(test);
···
908
895
{
909
896
struct pci_dev *pdev = test->pdev;
910
897
struct device *dev = &pdev->dev;
911
-
u32 caps;
912
898
913
-
caps = pci_endpoint_test_readl(test, PCI_ENDPOINT_TEST_CAPS);
914
-
dev_dbg(dev, "PCI_ENDPOINT_TEST_CAPS: %#x\n", caps);
899
+
test->ep_caps = pci_endpoint_test_readl(test, PCI_ENDPOINT_TEST_CAPS);
900
+
dev_dbg(dev, "PCI_ENDPOINT_TEST_CAPS: %#x\n", test->ep_caps);
915
901
916
902
/* CAP_UNALIGNED_ACCESS is set if the EP can do unaligned access */
917
-
if (caps & CAP_UNALIGNED_ACCESS)
903
+
if (test->ep_caps & CAP_UNALIGNED_ACCESS)
918
904
test->alignment = 0;
919
905
}
920
906
···
922
910
{
923
911
int ret;
924
912
int id;
925
-
char name[24];
913
+
char name[29];
926
914
enum pci_barno bar;
927
915
void __iomem *base;
928
916
struct device *dev = &pdev->dev;
···
941
929
test->test_reg_bar = 0;
942
930
test->alignment = 0;
943
931
test->pdev = pdev;
944
-
test->irq_type = IRQ_TYPE_UNDEFINED;
945
-
946
-
if (no_msi)
947
-
irq_type = IRQ_TYPE_INTX;
932
+
test->irq_type = PCITEST_IRQ_TYPE_UNDEFINED;
948
933
949
934
data = (struct pci_endpoint_test_data *)ent->driver_data;
950
935
if (data) {
951
936
test_reg_bar = data->test_reg_bar;
952
937
test->test_reg_bar = test_reg_bar;
953
938
test->alignment = data->alignment;
954
-
irq_type = data->irq_type;
939
+
test->irq_type = data->irq_type;
955
940
}
956
941
957
942
init_completion(&test->irq_raised);
···
970
961
971
962
pci_set_master(pdev);
972
963
973
-
ret = pci_endpoint_test_alloc_irq_vectors(test, irq_type);
964
+
ret = pci_endpoint_test_alloc_irq_vectors(test, test->irq_type);
974
965
if (ret)
975
966
goto err_disable_irq;
976
967
···
1092
1083
static const struct pci_endpoint_test_data default_data = {
1093
1084
.test_reg_bar = BAR_0,
1094
1085
.alignment = SZ_4K,
1095
-
.irq_type = IRQ_TYPE_MSI,
1086
+
.irq_type = PCITEST_IRQ_TYPE_MSI,
1096
1087
};
1097
1088
1098
1089
static const struct pci_endpoint_test_data am654_data = {
1099
1090
.test_reg_bar = BAR_2,
1100
1091
.alignment = SZ_64K,
1101
-
.irq_type = IRQ_TYPE_MSI,
1092
+
.irq_type = PCITEST_IRQ_TYPE_MSI,
1102
1093
};
1103
1094
1104
1095
static const struct pci_endpoint_test_data j721e_data = {
1105
1096
.alignment = 256,
1106
-
.irq_type = IRQ_TYPE_MSI,
1097
+
.irq_type = PCITEST_IRQ_TYPE_MSI,
1107
1098
};
1108
1099
1109
1100
static const struct pci_endpoint_test_data rk3588_data = {
1110
1101
.alignment = SZ_64K,
1111
-
.irq_type = IRQ_TYPE_MSI,
1102
+
.irq_type = PCITEST_IRQ_TYPE_MSI,
1112
1103
};
1113
1104
1114
1105
/*
+4
-1
drivers/pci/Kconfig
+4
-1
drivers/pci/Kconfig
-43
drivers/pci/bus.c
-43
drivers/pci/bus.c
···
331
331
332
332
void __weak pcibios_bus_add_device(struct pci_dev *pdev) { }
333
333
334
-
/*
335
-
* Create pwrctrl devices (if required) for the PCI devices to handle the power
336
-
* state.
337
-
*/
338
-
static void pci_pwrctrl_create_devices(struct pci_dev *dev)
339
-
{
340
-
struct device_node *np = dev_of_node(&dev->dev);
341
-
struct device *parent = &dev->dev;
342
-
struct platform_device *pdev;
343
-
344
-
/*
345
-
* First ensure that we are starting from a PCI bridge and it has a
346
-
* corresponding devicetree node.
347
-
*/
348
-
if (np && pci_is_bridge(dev)) {
349
-
/*
350
-
* Now look for the child PCI device nodes and create pwrctrl
351
-
* devices for them. The pwrctrl device drivers will manage the
352
-
* power state of the devices.
353
-
*/
354
-
for_each_available_child_of_node_scoped(np, child) {
355
-
/*
356
-
* First check whether the pwrctrl device really
357
-
* needs to be created or not. This is decided
358
-
* based on at least one of the power supplies
359
-
* being defined in the devicetree node of the
360
-
* device.
361
-
*/
362
-
if (!of_pci_supply_present(child)) {
363
-
pci_dbg(dev, "skipping OF node: %s\n", child->name);
364
-
return;
365
-
}
366
-
367
-
/* Now create the pwrctrl device */
368
-
pdev = of_platform_device_create(child, NULL, parent);
369
-
if (!pdev)
370
-
pci_err(dev, "failed to create OF node: %s\n", child->name);
371
-
}
372
-
}
373
-
}
374
-
375
334
/**
376
335
* pci_bus_add_device - start driver for a single device
377
336
* @dev: device to add
···
354
395
pci_create_sysfs_dev_files(dev);
355
396
pci_proc_attach_device(dev);
356
397
pci_bridge_d3_update(dev);
357
-
358
-
pci_pwrctrl_create_devices(dev);
359
398
360
399
/*
361
400
* If the PCI device is associated with a pwrctrl device with a
+3
-2
drivers/pci/controller/cadence/pci-j721e.c
+3
-2
drivers/pci/controller/cadence/pci-j721e.c
···
355
355
static const struct j721e_pcie_data j7200_pcie_ep_data = {
356
356
.mode = PCI_MODE_EP,
357
357
.quirk_detect_quiet_flag = true,
358
+
.linkdown_irq_regfield = J7200_LINK_DOWN,
358
359
.quirk_disable_flr = true,
359
360
.max_lanes = 2,
360
361
};
···
377
376
.mode = PCI_MODE_RC,
378
377
.quirk_retrain_flag = true,
379
378
.byte_access_allowed = false,
380
-
.linkdown_irq_regfield = LINK_DOWN,
379
+
.linkdown_irq_regfield = J7200_LINK_DOWN,
381
380
.max_lanes = 4,
382
381
};
383
382
384
383
static const struct j721e_pcie_data j784s4_pcie_ep_data = {
385
384
.mode = PCI_MODE_EP,
386
-
.linkdown_irq_regfield = LINK_DOWN,
385
+
.linkdown_irq_regfield = J7200_LINK_DOWN,
387
386
.max_lanes = 4,
388
387
};
389
388
+5
-6
drivers/pci/controller/cadence/pcie-cadence-ep.c
+5
-6
drivers/pci/controller/cadence/pcie-cadence-ep.c
···
301
301
val |= interrupts;
302
302
cdns_pcie_ep_fn_writew(pcie, fn, reg, val);
303
303
304
-
/* Set MSIX BAR and offset */
304
+
/* Set MSI-X BAR and offset */
305
305
reg = cap + PCI_MSIX_TABLE;
306
306
val = offset | bir;
307
307
cdns_pcie_ep_fn_writel(pcie, fn, reg, val);
308
308
309
-
/* Set PBA BAR and offset. BAR must match MSIX BAR */
309
+
/* Set PBA BAR and offset. BAR must match MSI-X BAR */
310
310
reg = cap + PCI_MSIX_PBA;
311
311
val = (offset + (interrupts * PCI_MSIX_ENTRY_SIZE)) | bir;
312
312
cdns_pcie_ep_fn_writel(pcie, fn, reg, val);
···
352
352
spin_unlock_irqrestore(&ep->lock, flags);
353
353
354
354
offset = CDNS_PCIE_NORMAL_MSG_ROUTING(MSG_ROUTING_LOCAL) |
355
-
CDNS_PCIE_NORMAL_MSG_CODE(msg_code) |
356
-
CDNS_PCIE_MSG_NO_DATA;
355
+
CDNS_PCIE_NORMAL_MSG_CODE(msg_code);
357
356
writel(0, ep->irq_cpu_addr + offset);
358
357
}
359
358
···
572
573
573
574
/*
574
575
* Next function field in ARI_CAP_AND_CTR register for last function
575
-
* should be 0.
576
-
* Clearing Next Function Number field for the last function used.
576
+
* should be 0. Clear Next Function Number field for the last
577
+
* function used.
577
578
*/
578
579
last_fn = find_last_bit(&epc->function_num_map, BITS_PER_LONG);
579
580
reg = CDNS_PCIE_CORE_PF_I_ARI_CAP_AND_CTRL(last_fn);
+1
-1
drivers/pci/controller/cadence/pcie-cadence.h
+1
-1
drivers/pci/controller/cadence/pcie-cadence.h
+21
drivers/pci/controller/dwc/Kconfig
+21
drivers/pci/controller/dwc/Kconfig
···
6
6
config PCIE_DW
7
7
bool
8
8
9
+
config PCIE_DW_DEBUGFS
10
+
bool "DesignWare PCIe debugfs entries"
11
+
depends on DEBUG_FS
12
+
depends on PCIE_DW_HOST || PCIE_DW_EP
13
+
help
14
+
Say Y here to enable debugfs entries for the PCIe controller. These
15
+
entries provide various debug features related to the controller and
16
+
expose the RAS DES capabilities such as Silicon Debug, Error Injection
17
+
and Statistical Counters.
18
+
9
19
config PCIE_DW_HOST
10
20
bool
11
21
select PCIE_DW
···
36
26
core plus Annapurna Labs proprietary hardware wrappers. This is
37
27
required only for DT-based platforms. ACPI platforms with the
38
28
Annapurna Labs PCIe controller don't need to enable this.
29
+
30
+
config PCIE_AMD_MDB
31
+
bool "AMD MDB Versal2 PCIe controller"
32
+
depends on OF && (ARM64 || COMPILE_TEST)
33
+
depends on PCI_MSI
34
+
select PCIE_DW_HOST
35
+
help
36
+
Say Y here if you want to enable PCIe controller support on AMD
37
+
Versal2 SoCs. The AMD MDB Versal2 PCIe controller is based on
38
+
DesignWare IP and therefore the driver re-uses the DesignWare
39
+
core functions to implement the driver.
39
40
40
41
config PCI_MESON
41
42
tristate "Amlogic Meson PCIe controller"
+2
drivers/pci/controller/dwc/Makefile
+2
drivers/pci/controller/dwc/Makefile
···
1
1
# SPDX-License-Identifier: GPL-2.0
2
2
obj-$(CONFIG_PCIE_DW) += pcie-designware.o
3
+
obj-$(CONFIG_PCIE_DW_DEBUGFS) += pcie-designware-debugfs.o
3
4
obj-$(CONFIG_PCIE_DW_HOST) += pcie-designware-host.o
4
5
obj-$(CONFIG_PCIE_DW_EP) += pcie-designware-ep.o
5
6
obj-$(CONFIG_PCIE_DW_PLAT) += pcie-designware-plat.o
7
+
obj-$(CONFIG_PCIE_AMD_MDB) += pcie-amd-mdb.o
6
8
obj-$(CONFIG_PCIE_BT1) += pcie-bt1.o
7
9
obj-$(CONFIG_PCI_DRA7XX) += pci-dra7xx.o
8
10
obj-$(CONFIG_PCI_EXYNOS) += pci-exynos.o
+20
-86
drivers/pci/controller/dwc/pci-imx6.c
+20
-86
drivers/pci/controller/dwc/pci-imx6.c
···
41
41
#define IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE BIT(11)
42
42
#define IMX8MQ_GPR_PCIE_VREG_BYPASS BIT(12)
43
43
#define IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE GENMASK(11, 8)
44
-
#define IMX8MQ_PCIE2_BASE_ADDR 0x33c00000
45
44
46
45
#define IMX95_PCIE_PHY_GEN_CTRL 0x0
47
46
#define IMX95_PCIE_REF_USE_PAD BIT(17)
···
108
109
109
110
#define imx_check_flag(pci, val) (pci->drvdata->flags & val)
110
111
111
-
#define IMX_PCIE_MAX_CLKS 6
112
112
#define IMX_PCIE_MAX_INSTANCES 2
113
113
114
114
struct imx_pcie;
···
118
120
u32 flags;
119
121
int dbi_length;
120
122
const char *gpr;
121
-
const char * const *clk_names;
122
-
const u32 clks_cnt;
123
-
const u32 clks_optional_cnt;
124
123
const u32 ltssm_off;
125
124
const u32 ltssm_mask;
126
125
const u32 mode_off[IMX_PCIE_MAX_INSTANCES];
···
132
137
struct imx_pcie {
133
138
struct dw_pcie *pci;
134
139
struct gpio_desc *reset_gpiod;
135
-
struct clk_bulk_data clks[IMX_PCIE_MAX_CLKS];
140
+
struct clk_bulk_data *clks;
141
+
int num_clks;
136
142
struct regmap *iomuxc_gpr;
137
143
u16 msi_ctrl;
138
144
u32 controller_id;
···
466
470
int mult, div;
467
471
u16 val;
468
472
int i;
473
+
struct clk_bulk_data *clks = imx_pcie->clks;
469
474
470
475
if (!(imx_pcie->drvdata->flags & IMX_PCIE_FLAG_IMX_PHY))
471
476
return 0;
472
477
473
-
for (i = 0; i < imx_pcie->drvdata->clks_cnt; i++)
474
-
if (strncmp(imx_pcie->clks[i].id, "pcie_phy", 8) == 0)
475
-
phy_rate = clk_get_rate(imx_pcie->clks[i].clk);
478
+
for (i = 0; i < imx_pcie->num_clks; i++)
479
+
if (strncmp(clks[i].id, "pcie_phy", 8) == 0)
480
+
phy_rate = clk_get_rate(clks[i].clk);
476
481
477
482
switch (phy_rate) {
478
483
case 125000000:
···
665
668
struct device *dev = pci->dev;
666
669
int ret;
667
670
668
-
ret = clk_bulk_prepare_enable(imx_pcie->drvdata->clks_cnt, imx_pcie->clks);
671
+
ret = clk_bulk_prepare_enable(imx_pcie->num_clks, imx_pcie->clks);
669
672
if (ret)
670
673
return ret;
671
674
···
682
685
return 0;
683
686
684
687
err_ref_clk:
685
-
clk_bulk_disable_unprepare(imx_pcie->drvdata->clks_cnt, imx_pcie->clks);
688
+
clk_bulk_disable_unprepare(imx_pcie->num_clks, imx_pcie->clks);
686
689
687
690
return ret;
688
691
}
···
691
694
{
692
695
if (imx_pcie->drvdata->enable_ref_clk)
693
696
imx_pcie->drvdata->enable_ref_clk(imx_pcie, false);
694
-
clk_bulk_disable_unprepare(imx_pcie->drvdata->clks_cnt, imx_pcie->clks);
697
+
clk_bulk_disable_unprepare(imx_pcie->num_clks, imx_pcie->clks);
695
698
}
696
699
697
700
static int imx6sx_pcie_core_reset(struct imx_pcie *imx_pcie, bool assert)
···
1214
1217
regulator_disable(imx_pcie->vpcie);
1215
1218
}
1216
1219
1217
-
static u64 imx_pcie_cpu_addr_fixup(struct dw_pcie *pcie, u64 cpu_addr)
1218
-
{
1219
-
struct imx_pcie *imx_pcie = to_imx_pcie(pcie);
1220
-
struct dw_pcie_rp *pp = &pcie->pp;
1221
-
struct resource_entry *entry;
1222
-
1223
-
if (!(imx_pcie->drvdata->flags & IMX_PCIE_FLAG_CPU_ADDR_FIXUP))
1224
-
return cpu_addr;
1225
-
1226
-
entry = resource_list_first_type(&pp->bridge->windows, IORESOURCE_MEM);
1227
-
if (!entry)
1228
-
return cpu_addr;
1229
-
1230
-
return cpu_addr - entry->offset;
1231
-
}
1232
-
1233
1220
/*
1234
1221
* In old DWC implementations, PCIE_ATU_INHIBIT_PAYLOAD in iATU Ctrl2
1235
1222
* register is reserved, so the generic DWC implementation of sending the
···
1244
1263
static const struct dw_pcie_ops dw_pcie_ops = {
1245
1264
.start_link = imx_pcie_start_link,
1246
1265
.stop_link = imx_pcie_stop_link,
1247
-
.cpu_addr_fixup = imx_pcie_cpu_addr_fixup,
1248
1266
};
1249
1267
1250
1268
static void imx_pcie_ep_init(struct dw_pcie_ep *ep)
···
1454
1474
struct dw_pcie *pci;
1455
1475
struct imx_pcie *imx_pcie;
1456
1476
struct device_node *np;
1457
-
struct resource *dbi_base;
1458
1477
struct device_node *node = dev->of_node;
1459
-
int i, ret, req_cnt;
1478
+
int ret, domain;
1460
1479
u16 val;
1461
1480
1462
1481
imx_pcie = devm_kzalloc(dev, sizeof(*imx_pcie), GFP_KERNEL);
···
1494
1515
return PTR_ERR(imx_pcie->phy_base);
1495
1516
}
1496
1517
1497
-
pci->dbi_base = devm_platform_get_and_ioremap_resource(pdev, 0, &dbi_base);
1498
-
if (IS_ERR(pci->dbi_base))
1499
-
return PTR_ERR(pci->dbi_base);
1500
-
1501
1518
/* Fetch GPIOs */
1502
1519
imx_pcie->reset_gpiod = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);
1503
1520
if (IS_ERR(imx_pcie->reset_gpiod))
···
1501
1526
"unable to get reset gpio\n");
1502
1527
gpiod_set_consumer_name(imx_pcie->reset_gpiod, "PCIe reset");
1503
1528
1504
-
if (imx_pcie->drvdata->clks_cnt >= IMX_PCIE_MAX_CLKS)
1505
-
return dev_err_probe(dev, -ENOMEM, "clks_cnt is too big\n");
1506
-
1507
-
for (i = 0; i < imx_pcie->drvdata->clks_cnt; i++)
1508
-
imx_pcie->clks[i].id = imx_pcie->drvdata->clk_names[i];
1509
-
1510
1529
/* Fetch clocks */
1511
-
req_cnt = imx_pcie->drvdata->clks_cnt - imx_pcie->drvdata->clks_optional_cnt;
1512
-
ret = devm_clk_bulk_get(dev, req_cnt, imx_pcie->clks);
1513
-
if (ret)
1514
-
return ret;
1515
-
imx_pcie->clks[req_cnt].clk = devm_clk_get_optional(dev, "ref");
1516
-
if (IS_ERR(imx_pcie->clks[req_cnt].clk))
1517
-
return PTR_ERR(imx_pcie->clks[req_cnt].clk);
1530
+
imx_pcie->num_clks = devm_clk_bulk_get_all(dev, &imx_pcie->clks);
1531
+
if (imx_pcie->num_clks < 0)
1532
+
return dev_err_probe(dev, imx_pcie->num_clks,
1533
+
"failed to get clocks\n");
1518
1534
1519
1535
if (imx_check_flag(imx_pcie, IMX_PCIE_FLAG_HAS_PHYDRV)) {
1520
1536
imx_pcie->phy = devm_phy_get(dev, "pcie-phy");
···
1531
1565
switch (imx_pcie->drvdata->variant) {
1532
1566
case IMX8MQ:
1533
1567
case IMX8MQ_EP:
1534
-
if (dbi_base->start == IMX8MQ_PCIE2_BASE_ADDR)
1535
-
imx_pcie->controller_id = 1;
1568
+
domain = of_get_pci_domain_nr(node);
1569
+
if (domain < 0 || domain > 1)
1570
+
return dev_err_probe(dev, -ENODEV, "no \"linux,pci-domain\" property in devicetree\n");
1571
+
1572
+
imx_pcie->controller_id = domain;
1536
1573
break;
1537
1574
default:
1538
1575
break;
···
1614
1645
if (ret)
1615
1646
return ret;
1616
1647
1648
+
pci->use_parent_dt_ranges = true;
1617
1649
if (imx_pcie->drvdata->mode == DW_PCIE_EP_TYPE) {
1618
1650
ret = imx_add_pcie_ep(imx_pcie, pdev);
1619
1651
if (ret < 0)
···
1645
1675
imx_pcie_assert_core_reset(imx_pcie);
1646
1676
}
1647
1677
1648
-
static const char * const imx6q_clks[] = {"pcie_bus", "pcie", "pcie_phy"};
1649
-
static const char * const imx8mm_clks[] = {"pcie_bus", "pcie", "pcie_aux"};
1650
-
static const char * const imx8mq_clks[] = {"pcie_bus", "pcie", "pcie_phy", "pcie_aux"};
1651
-
static const char * const imx6sx_clks[] = {"pcie_bus", "pcie", "pcie_phy", "pcie_inbound_axi"};
1652
-
static const char * const imx8q_clks[] = {"mstr", "slv", "dbi"};
1653
-
static const char * const imx95_clks[] = {"pcie_bus", "pcie", "pcie_phy", "pcie_aux", "ref"};
1654
-
1655
1678
static const struct imx_pcie_drvdata drvdata[] = {
1656
1679
[IMX6Q] = {
1657
1680
.variant = IMX6Q,
···
1654
1691
IMX_PCIE_FLAG_SUPPORTS_SUSPEND,
1655
1692
.dbi_length = 0x200,
1656
1693
.gpr = "fsl,imx6q-iomuxc-gpr",
1657
-
.clk_names = imx6q_clks,
1658
-
.clks_cnt = ARRAY_SIZE(imx6q_clks),
1659
1694
.ltssm_off = IOMUXC_GPR12,
1660
1695
.ltssm_mask = IMX6Q_GPR12_PCIE_CTL_2,
1661
1696
.mode_off[0] = IOMUXC_GPR12,
···
1668
1707
IMX_PCIE_FLAG_IMX_SPEED_CHANGE |
1669
1708
IMX_PCIE_FLAG_SUPPORTS_SUSPEND,
1670
1709
.gpr = "fsl,imx6q-iomuxc-gpr",
1671
-
.clk_names = imx6sx_clks,
1672
-
.clks_cnt = ARRAY_SIZE(imx6sx_clks),
1673
1710
.ltssm_off = IOMUXC_GPR12,
1674
1711
.ltssm_mask = IMX6Q_GPR12_PCIE_CTL_2,
1675
1712
.mode_off[0] = IOMUXC_GPR12,
···
1684
1725
IMX_PCIE_FLAG_SUPPORTS_SUSPEND,
1685
1726
.dbi_length = 0x200,
1686
1727
.gpr = "fsl,imx6q-iomuxc-gpr",
1687
-
.clk_names = imx6q_clks,
1688
-
.clks_cnt = ARRAY_SIZE(imx6q_clks),
1689
1728
.ltssm_off = IOMUXC_GPR12,
1690
1729
.ltssm_mask = IMX6Q_GPR12_PCIE_CTL_2,
1691
1730
.mode_off[0] = IOMUXC_GPR12,
···
1699
1742
IMX_PCIE_FLAG_HAS_APP_RESET |
1700
1743
IMX_PCIE_FLAG_HAS_PHY_RESET,
1701
1744
.gpr = "fsl,imx7d-iomuxc-gpr",
1702
-
.clk_names = imx6q_clks,
1703
-
.clks_cnt = ARRAY_SIZE(imx6q_clks),
1704
1745
.mode_off[0] = IOMUXC_GPR12,
1705
1746
.mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
1706
1747
.enable_ref_clk = imx7d_pcie_enable_ref_clk,
···
1710
1755
IMX_PCIE_FLAG_HAS_PHY_RESET |
1711
1756
IMX_PCIE_FLAG_SUPPORTS_SUSPEND,
1712
1757
.gpr = "fsl,imx8mq-iomuxc-gpr",
1713
-
.clk_names = imx8mq_clks,
1714
-
.clks_cnt = ARRAY_SIZE(imx8mq_clks),
1715
1758
.mode_off[0] = IOMUXC_GPR12,
1716
1759
.mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
1717
1760
.mode_off[1] = IOMUXC_GPR12,
···
1723
1770
IMX_PCIE_FLAG_HAS_PHYDRV |
1724
1771
IMX_PCIE_FLAG_HAS_APP_RESET,
1725
1772
.gpr = "fsl,imx8mm-iomuxc-gpr",
1726
-
.clk_names = imx8mm_clks,
1727
-
.clks_cnt = ARRAY_SIZE(imx8mm_clks),
1728
1773
.mode_off[0] = IOMUXC_GPR12,
1729
1774
.mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
1730
1775
.enable_ref_clk = imx8mm_pcie_enable_ref_clk,
···
1733
1782
IMX_PCIE_FLAG_HAS_PHYDRV |
1734
1783
IMX_PCIE_FLAG_HAS_APP_RESET,
1735
1784
.gpr = "fsl,imx8mp-iomuxc-gpr",
1736
-
.clk_names = imx8mm_clks,
1737
-
.clks_cnt = ARRAY_SIZE(imx8mm_clks),
1738
1785
.mode_off[0] = IOMUXC_GPR12,
1739
1786
.mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
1740
1787
.enable_ref_clk = imx8mm_pcie_enable_ref_clk,
···
1742
1793
.flags = IMX_PCIE_FLAG_HAS_PHYDRV |
1743
1794
IMX_PCIE_FLAG_CPU_ADDR_FIXUP |
1744
1795
IMX_PCIE_FLAG_SUPPORTS_SUSPEND,
1745
-
.clk_names = imx8q_clks,
1746
-
.clks_cnt = ARRAY_SIZE(imx8q_clks),
1747
1796
},
1748
1797
[IMX95] = {
1749
1798
.variant = IMX95,
1750
1799
.flags = IMX_PCIE_FLAG_HAS_SERDES |
1751
1800
IMX_PCIE_FLAG_HAS_LUT |
1752
1801
IMX_PCIE_FLAG_SUPPORTS_SUSPEND,
1753
-
.clk_names = imx95_clks,
1754
-
.clks_cnt = ARRAY_SIZE(imx95_clks),
1755
-
.clks_optional_cnt = 1,
1756
1802
.ltssm_off = IMX95_PE0_GEN_CTRL_3,
1757
1803
.ltssm_mask = IMX95_PCIE_LTSSM_EN,
1758
1804
.mode_off[0] = IMX95_PE0_GEN_CTRL_1,
···
1760
1816
IMX_PCIE_FLAG_HAS_PHY_RESET,
1761
1817
.mode = DW_PCIE_EP_TYPE,
1762
1818
.gpr = "fsl,imx8mq-iomuxc-gpr",
1763
-
.clk_names = imx8mq_clks,
1764
-
.clks_cnt = ARRAY_SIZE(imx8mq_clks),
1765
1819
.mode_off[0] = IOMUXC_GPR12,
1766
1820
.mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
1767
1821
.mode_off[1] = IOMUXC_GPR12,
···
1774
1832
IMX_PCIE_FLAG_HAS_PHYDRV,
1775
1833
.mode = DW_PCIE_EP_TYPE,
1776
1834
.gpr = "fsl,imx8mm-iomuxc-gpr",
1777
-
.clk_names = imx8mm_clks,
1778
-
.clks_cnt = ARRAY_SIZE(imx8mm_clks),
1779
1835
.mode_off[0] = IOMUXC_GPR12,
1780
1836
.mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
1781
1837
.epc_features = &imx8m_pcie_epc_features,
···
1785
1845
IMX_PCIE_FLAG_HAS_PHYDRV,
1786
1846
.mode = DW_PCIE_EP_TYPE,
1787
1847
.gpr = "fsl,imx8mp-iomuxc-gpr",
1788
-
.clk_names = imx8mm_clks,
1789
-
.clks_cnt = ARRAY_SIZE(imx8mm_clks),
1790
1848
.mode_off[0] = IOMUXC_GPR12,
1791
1849
.mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
1792
1850
.epc_features = &imx8m_pcie_epc_features,
···
1795
1857
.flags = IMX_PCIE_FLAG_HAS_PHYDRV,
1796
1858
.mode = DW_PCIE_EP_TYPE,
1797
1859
.epc_features = &imx8q_pcie_epc_features,
1798
-
.clk_names = imx8q_clks,
1799
-
.clks_cnt = ARRAY_SIZE(imx8q_clks),
1800
1860
},
1801
1861
[IMX95_EP] = {
1802
1862
.variant = IMX95_EP,
1803
1863
.flags = IMX_PCIE_FLAG_HAS_SERDES |
1804
1864
IMX_PCIE_FLAG_SUPPORT_64BIT,
1805
-
.clk_names = imx8mq_clks,
1806
-
.clks_cnt = ARRAY_SIZE(imx8mq_clks),
1807
1865
.ltssm_off = IMX95_PE0_GEN_CTRL_3,
1808
1866
.ltssm_mask = IMX95_PCIE_LTSSM_EN,
1809
1867
.mode_off[0] = IMX95_PE0_GEN_CTRL_1,
+3
-3
drivers/pci/controller/dwc/pci-keystone.c
+3
-3
drivers/pci/controller/dwc/pci-keystone.c
···
966
966
.msix_capable = true,
967
967
.bar[BAR_0] = { .type = BAR_RESERVED, },
968
968
.bar[BAR_1] = { .type = BAR_RESERVED, },
969
-
.bar[BAR_2] = { .type = BAR_FIXED, .fixed_size = SZ_1M, },
969
+
.bar[BAR_2] = { .type = BAR_RESIZABLE, },
970
970
.bar[BAR_3] = { .type = BAR_FIXED, .fixed_size = SZ_64K, },
971
971
.bar[BAR_4] = { .type = BAR_FIXED, .fixed_size = 256, },
972
-
.bar[BAR_5] = { .type = BAR_FIXED, .fixed_size = SZ_1M, },
973
-
.align = SZ_1M,
972
+
.bar[BAR_5] = { .type = BAR_RESIZABLE, },
973
+
.align = SZ_64K,
974
974
};
975
975
976
976
static const struct pci_epc_features*
+1
-1
drivers/pci/controller/dwc/pci-layerscape.c
+1
-1
drivers/pci/controller/dwc/pci-layerscape.c
+476
drivers/pci/controller/dwc/pcie-amd-mdb.c
+476
drivers/pci/controller/dwc/pcie-amd-mdb.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* PCIe host controller driver for AMD MDB PCIe Bridge
4
+
*
5
+
* Copyright (C) 2024-2025, Advanced Micro Devices, Inc.
6
+
*/
7
+
8
+
#include <linux/clk.h>
9
+
#include <linux/delay.h>
10
+
#include <linux/gpio.h>
11
+
#include <linux/interrupt.h>
12
+
#include <linux/irqdomain.h>
13
+
#include <linux/kernel.h>
14
+
#include <linux/init.h>
15
+
#include <linux/of_device.h>
16
+
#include <linux/pci.h>
17
+
#include <linux/platform_device.h>
18
+
#include <linux/resource.h>
19
+
#include <linux/types.h>
20
+
21
+
#include "pcie-designware.h"
22
+
23
+
#define AMD_MDB_TLP_IR_STATUS_MISC 0x4C0
24
+
#define AMD_MDB_TLP_IR_MASK_MISC 0x4C4
25
+
#define AMD_MDB_TLP_IR_ENABLE_MISC 0x4C8
26
+
#define AMD_MDB_TLP_IR_DISABLE_MISC 0x4CC
27
+
28
+
#define AMD_MDB_TLP_PCIE_INTX_MASK GENMASK(23, 16)
29
+
30
+
#define AMD_MDB_PCIE_INTR_INTX_ASSERT(x) BIT((x) * 2)
31
+
32
+
/* Interrupt registers definitions. */
33
+
#define AMD_MDB_PCIE_INTR_CMPL_TIMEOUT 15
34
+
#define AMD_MDB_PCIE_INTR_INTX 16
35
+
#define AMD_MDB_PCIE_INTR_PM_PME_RCVD 24
36
+
#define AMD_MDB_PCIE_INTR_PME_TO_ACK_RCVD 25
37
+
#define AMD_MDB_PCIE_INTR_MISC_CORRECTABLE 26
38
+
#define AMD_MDB_PCIE_INTR_NONFATAL 27
39
+
#define AMD_MDB_PCIE_INTR_FATAL 28
40
+
41
+
#define IMR(x) BIT(AMD_MDB_PCIE_INTR_ ##x)
42
+
#define AMD_MDB_PCIE_IMR_ALL_MASK \
43
+
( \
44
+
IMR(CMPL_TIMEOUT) | \
45
+
IMR(PM_PME_RCVD) | \
46
+
IMR(PME_TO_ACK_RCVD) | \
47
+
IMR(MISC_CORRECTABLE) | \
48
+
IMR(NONFATAL) | \
49
+
IMR(FATAL) | \
50
+
AMD_MDB_TLP_PCIE_INTX_MASK \
51
+
)
52
+
53
+
/**
54
+
* struct amd_mdb_pcie - PCIe port information
55
+
* @pci: DesignWare PCIe controller structure
56
+
* @slcr: MDB System Level Control and Status Register (SLCR) base
57
+
* @intx_domain: INTx IRQ domain pointer
58
+
* @mdb_domain: MDB IRQ domain pointer
59
+
* @intx_irq: INTx IRQ interrupt number
60
+
*/
61
+
struct amd_mdb_pcie {
62
+
struct dw_pcie pci;
63
+
void __iomem *slcr;
64
+
struct irq_domain *intx_domain;
65
+
struct irq_domain *mdb_domain;
66
+
int intx_irq;
67
+
};
68
+
69
+
static const struct dw_pcie_host_ops amd_mdb_pcie_host_ops = {
70
+
};
71
+
72
+
static void amd_mdb_intx_irq_mask(struct irq_data *data)
73
+
{
74
+
struct amd_mdb_pcie *pcie = irq_data_get_irq_chip_data(data);
75
+
struct dw_pcie *pci = &pcie->pci;
76
+
struct dw_pcie_rp *port = &pci->pp;
77
+
unsigned long flags;
78
+
u32 val;
79
+
80
+
raw_spin_lock_irqsave(&port->lock, flags);
81
+
val = FIELD_PREP(AMD_MDB_TLP_PCIE_INTX_MASK,
82
+
AMD_MDB_PCIE_INTR_INTX_ASSERT(data->hwirq));
83
+
84
+
/*
85
+
* Writing '1' to a bit in AMD_MDB_TLP_IR_DISABLE_MISC disables that
86
+
* interrupt, writing '0' has no effect.
87
+
*/
88
+
writel_relaxed(val, pcie->slcr + AMD_MDB_TLP_IR_DISABLE_MISC);
89
+
raw_spin_unlock_irqrestore(&port->lock, flags);
90
+
}
91
+
92
+
static void amd_mdb_intx_irq_unmask(struct irq_data *data)
93
+
{
94
+
struct amd_mdb_pcie *pcie = irq_data_get_irq_chip_data(data);
95
+
struct dw_pcie *pci = &pcie->pci;
96
+
struct dw_pcie_rp *port = &pci->pp;
97
+
unsigned long flags;
98
+
u32 val;
99
+
100
+
raw_spin_lock_irqsave(&port->lock, flags);
101
+
val = FIELD_PREP(AMD_MDB_TLP_PCIE_INTX_MASK,
102
+
AMD_MDB_PCIE_INTR_INTX_ASSERT(data->hwirq));
103
+
104
+
/*
105
+
* Writing '1' to a bit in AMD_MDB_TLP_IR_ENABLE_MISC enables that
106
+
* interrupt, writing '0' has no effect.
107
+
*/
108
+
writel_relaxed(val, pcie->slcr + AMD_MDB_TLP_IR_ENABLE_MISC);
109
+
raw_spin_unlock_irqrestore(&port->lock, flags);
110
+
}
111
+
112
+
static struct irq_chip amd_mdb_intx_irq_chip = {
113
+
.name = "AMD MDB INTx",
114
+
.irq_mask = amd_mdb_intx_irq_mask,
115
+
.irq_unmask = amd_mdb_intx_irq_unmask,
116
+
};
117
+
118
+
/**
119
+
* amd_mdb_pcie_intx_map - Set the handler for the INTx and mark IRQ as valid
120
+
* @domain: IRQ domain
121
+
* @irq: Virtual IRQ number
122
+
* @hwirq: Hardware interrupt number
123
+
*
124
+
* Return: Always returns '0'.
125
+
*/
126
+
static int amd_mdb_pcie_intx_map(struct irq_domain *domain,
127
+
unsigned int irq, irq_hw_number_t hwirq)
128
+
{
129
+
irq_set_chip_and_handler(irq, &amd_mdb_intx_irq_chip,
130
+
handle_level_irq);
131
+
irq_set_chip_data(irq, domain->host_data);
132
+
irq_set_status_flags(irq, IRQ_LEVEL);
133
+
134
+
return 0;
135
+
}
136
+
137
+
/* INTx IRQ domain operations. */
138
+
static const struct irq_domain_ops amd_intx_domain_ops = {
139
+
.map = amd_mdb_pcie_intx_map,
140
+
};
141
+
142
+
static irqreturn_t dw_pcie_rp_intx(int irq, void *args)
143
+
{
144
+
struct amd_mdb_pcie *pcie = args;
145
+
unsigned long val;
146
+
int i, int_status;
147
+
148
+
val = readl_relaxed(pcie->slcr + AMD_MDB_TLP_IR_STATUS_MISC);
149
+
int_status = FIELD_GET(AMD_MDB_TLP_PCIE_INTX_MASK, val);
150
+
151
+
for (i = 0; i < PCI_NUM_INTX; i++) {
152
+
if (int_status & AMD_MDB_PCIE_INTR_INTX_ASSERT(i))
153
+
generic_handle_domain_irq(pcie->intx_domain, i);
154
+
}
155
+
156
+
return IRQ_HANDLED;
157
+
}
158
+
159
+
#define _IC(x, s)[AMD_MDB_PCIE_INTR_ ## x] = { __stringify(x), s }
160
+
161
+
static const struct {
162
+
const char *sym;
163
+
const char *str;
164
+
} intr_cause[32] = {
165
+
_IC(CMPL_TIMEOUT, "Completion timeout"),
166
+
_IC(PM_PME_RCVD, "PM_PME message received"),
167
+
_IC(PME_TO_ACK_RCVD, "PME_TO_ACK message received"),
168
+
_IC(MISC_CORRECTABLE, "Correctable error message"),
169
+
_IC(NONFATAL, "Non fatal error message"),
170
+
_IC(FATAL, "Fatal error message"),
171
+
};
172
+
173
+
static void amd_mdb_event_irq_mask(struct irq_data *d)
174
+
{
175
+
struct amd_mdb_pcie *pcie = irq_data_get_irq_chip_data(d);
176
+
struct dw_pcie *pci = &pcie->pci;
177
+
struct dw_pcie_rp *port = &pci->pp;
178
+
unsigned long flags;
179
+
u32 val;
180
+
181
+
raw_spin_lock_irqsave(&port->lock, flags);
182
+
val = BIT(d->hwirq);
183
+
writel_relaxed(val, pcie->slcr + AMD_MDB_TLP_IR_DISABLE_MISC);
184
+
raw_spin_unlock_irqrestore(&port->lock, flags);
185
+
}
186
+
187
+
static void amd_mdb_event_irq_unmask(struct irq_data *d)
188
+
{
189
+
struct amd_mdb_pcie *pcie = irq_data_get_irq_chip_data(d);
190
+
struct dw_pcie *pci = &pcie->pci;
191
+
struct dw_pcie_rp *port = &pci->pp;
192
+
unsigned long flags;
193
+
u32 val;
194
+
195
+
raw_spin_lock_irqsave(&port->lock, flags);
196
+
val = BIT(d->hwirq);
197
+
writel_relaxed(val, pcie->slcr + AMD_MDB_TLP_IR_ENABLE_MISC);
198
+
raw_spin_unlock_irqrestore(&port->lock, flags);
199
+
}
200
+
201
+
static struct irq_chip amd_mdb_event_irq_chip = {
202
+
.name = "AMD MDB RC-Event",
203
+
.irq_mask = amd_mdb_event_irq_mask,
204
+
.irq_unmask = amd_mdb_event_irq_unmask,
205
+
};
206
+
207
+
static int amd_mdb_pcie_event_map(struct irq_domain *domain,
208
+
unsigned int irq, irq_hw_number_t hwirq)
209
+
{
210
+
irq_set_chip_and_handler(irq, &amd_mdb_event_irq_chip,
211
+
handle_level_irq);
212
+
irq_set_chip_data(irq, domain->host_data);
213
+
irq_set_status_flags(irq, IRQ_LEVEL);
214
+
215
+
return 0;
216
+
}
217
+
218
+
static const struct irq_domain_ops event_domain_ops = {
219
+
.map = amd_mdb_pcie_event_map,
220
+
};
221
+
222
+
static irqreturn_t amd_mdb_pcie_event(int irq, void *args)
223
+
{
224
+
struct amd_mdb_pcie *pcie = args;
225
+
unsigned long val;
226
+
int i;
227
+
228
+
val = readl_relaxed(pcie->slcr + AMD_MDB_TLP_IR_STATUS_MISC);
229
+
val &= ~readl_relaxed(pcie->slcr + AMD_MDB_TLP_IR_MASK_MISC);
230
+
for_each_set_bit(i, &val, 32)
231
+
generic_handle_domain_irq(pcie->mdb_domain, i);
232
+
writel_relaxed(val, pcie->slcr + AMD_MDB_TLP_IR_STATUS_MISC);
233
+
234
+
return IRQ_HANDLED;
235
+
}
236
+
237
+
static void amd_mdb_pcie_free_irq_domains(struct amd_mdb_pcie *pcie)
238
+
{
239
+
if (pcie->intx_domain) {
240
+
irq_domain_remove(pcie->intx_domain);
241
+
pcie->intx_domain = NULL;
242
+
}
243
+
244
+
if (pcie->mdb_domain) {
245
+
irq_domain_remove(pcie->mdb_domain);
246
+
pcie->mdb_domain = NULL;
247
+
}
248
+
}
249
+
250
+
static int amd_mdb_pcie_init_port(struct amd_mdb_pcie *pcie)
251
+
{
252
+
unsigned long val;
253
+
254
+
/* Disable all TLP interrupts. */
255
+
writel_relaxed(AMD_MDB_PCIE_IMR_ALL_MASK,
256
+
pcie->slcr + AMD_MDB_TLP_IR_DISABLE_MISC);
257
+
258
+
/* Clear pending TLP interrupts. */
259
+
val = readl_relaxed(pcie->slcr + AMD_MDB_TLP_IR_STATUS_MISC);
260
+
val &= AMD_MDB_PCIE_IMR_ALL_MASK;
261
+
writel_relaxed(val, pcie->slcr + AMD_MDB_TLP_IR_STATUS_MISC);
262
+
263
+
/* Enable all TLP interrupts. */
264
+
writel_relaxed(AMD_MDB_PCIE_IMR_ALL_MASK,
265
+
pcie->slcr + AMD_MDB_TLP_IR_ENABLE_MISC);
266
+
267
+
return 0;
268
+
}
269
+
270
+
/**
271
+
* amd_mdb_pcie_init_irq_domains - Initialize IRQ domain
272
+
* @pcie: PCIe port information
273
+
* @pdev: Platform device
274
+
*
275
+
* Return: Returns '0' on success and error value on failure.
276
+
*/
277
+
static int amd_mdb_pcie_init_irq_domains(struct amd_mdb_pcie *pcie,
278
+
struct platform_device *pdev)
279
+
{
280
+
struct dw_pcie *pci = &pcie->pci;
281
+
struct dw_pcie_rp *pp = &pci->pp;
282
+
struct device *dev = &pdev->dev;
283
+
struct device_node *node = dev->of_node;
284
+
struct device_node *pcie_intc_node;
285
+
int err;
286
+
287
+
pcie_intc_node = of_get_next_child(node, NULL);
288
+
if (!pcie_intc_node) {
289
+
dev_err(dev, "No PCIe Intc node found\n");
290
+
return -ENODEV;
291
+
}
292
+
293
+
pcie->mdb_domain = irq_domain_add_linear(pcie_intc_node, 32,
294
+
&event_domain_ops, pcie);
295
+
if (!pcie->mdb_domain) {
296
+
err = -ENOMEM;
297
+
dev_err(dev, "Failed to add MDB domain\n");
298
+
goto out;
299
+
}
300
+
301
+
irq_domain_update_bus_token(pcie->mdb_domain, DOMAIN_BUS_NEXUS);
302
+
303
+
pcie->intx_domain = irq_domain_add_linear(pcie_intc_node, PCI_NUM_INTX,
304
+
&amd_intx_domain_ops, pcie);
305
+
if (!pcie->intx_domain) {
306
+
err = -ENOMEM;
307
+
dev_err(dev, "Failed to add INTx domain\n");
308
+
goto mdb_out;
309
+
}
310
+
311
+
of_node_put(pcie_intc_node);
312
+
irq_domain_update_bus_token(pcie->intx_domain, DOMAIN_BUS_WIRED);
313
+
314
+
raw_spin_lock_init(&pp->lock);
315
+
316
+
return 0;
317
+
mdb_out:
318
+
amd_mdb_pcie_free_irq_domains(pcie);
319
+
out:
320
+
of_node_put(pcie_intc_node);
321
+
return err;
322
+
}
323
+
324
+
static irqreturn_t amd_mdb_pcie_intr_handler(int irq, void *args)
325
+
{
326
+
struct amd_mdb_pcie *pcie = args;
327
+
struct device *dev;
328
+
struct irq_data *d;
329
+
330
+
dev = pcie->pci.dev;
331
+
332
+
/*
333
+
* In the future, error reporting will be hooked to the AER subsystem.
334
+
* Currently, the driver prints a warning message to the user.
335
+
*/
336
+
d = irq_domain_get_irq_data(pcie->mdb_domain, irq);
337
+
if (intr_cause[d->hwirq].str)
338
+
dev_warn(dev, "%s\n", intr_cause[d->hwirq].str);
339
+
else
340
+
dev_warn_once(dev, "Unknown IRQ %ld\n", d->hwirq);
341
+
342
+
return IRQ_HANDLED;
343
+
}
344
+
345
+
static int amd_mdb_setup_irq(struct amd_mdb_pcie *pcie,
346
+
struct platform_device *pdev)
347
+
{
348
+
struct dw_pcie *pci = &pcie->pci;
349
+
struct dw_pcie_rp *pp = &pci->pp;
350
+
struct device *dev = &pdev->dev;
351
+
int i, irq, err;
352
+
353
+
amd_mdb_pcie_init_port(pcie);
354
+
355
+
pp->irq = platform_get_irq(pdev, 0);
356
+
if (pp->irq < 0)
357
+
return pp->irq;
358
+
359
+
for (i = 0; i < ARRAY_SIZE(intr_cause); i++) {
360
+
if (!intr_cause[i].str)
361
+
continue;
362
+
363
+
irq = irq_create_mapping(pcie->mdb_domain, i);
364
+
if (!irq) {
365
+
dev_err(dev, "Failed to map MDB domain interrupt\n");
366
+
return -ENOMEM;
367
+
}
368
+
369
+
err = devm_request_irq(dev, irq, amd_mdb_pcie_intr_handler,
370
+
IRQF_NO_THREAD, intr_cause[i].sym, pcie);
371
+
if (err) {
372
+
dev_err(dev, "Failed to request IRQ %d, err=%d\n",
373
+
irq, err);
374
+
return err;
375
+
}
376
+
}
377
+
378
+
pcie->intx_irq = irq_create_mapping(pcie->mdb_domain,
379
+
AMD_MDB_PCIE_INTR_INTX);
380
+
if (!pcie->intx_irq) {
381
+
dev_err(dev, "Failed to map INTx interrupt\n");
382
+
return -ENXIO;
383
+
}
384
+
385
+
err = devm_request_irq(dev, pcie->intx_irq, dw_pcie_rp_intx,
386
+
IRQF_NO_THREAD, NULL, pcie);
387
+
if (err) {
388
+
dev_err(dev, "Failed to request INTx IRQ %d, err=%d\n",
389
+
irq, err);
390
+
return err;
391
+
}
392
+
393
+
/* Plug the main event handler. */
394
+
err = devm_request_irq(dev, pp->irq, amd_mdb_pcie_event, IRQF_NO_THREAD,
395
+
"amd_mdb pcie_irq", pcie);
396
+
if (err) {
397
+
dev_err(dev, "Failed to request event IRQ %d, err=%d\n",
398
+
pp->irq, err);
399
+
return err;
400
+
}
401
+
402
+
return 0;
403
+
}
404
+
405
+
static int amd_mdb_add_pcie_port(struct amd_mdb_pcie *pcie,
406
+
struct platform_device *pdev)
407
+
{
408
+
struct dw_pcie *pci = &pcie->pci;
409
+
struct dw_pcie_rp *pp = &pci->pp;
410
+
struct device *dev = &pdev->dev;
411
+
int err;
412
+
413
+
pcie->slcr = devm_platform_ioremap_resource_byname(pdev, "slcr");
414
+
if (IS_ERR(pcie->slcr))
415
+
return PTR_ERR(pcie->slcr);
416
+
417
+
err = amd_mdb_pcie_init_irq_domains(pcie, pdev);
418
+
if (err)
419
+
return err;
420
+
421
+
err = amd_mdb_setup_irq(pcie, pdev);
422
+
if (err) {
423
+
dev_err(dev, "Failed to set up interrupts, err=%d\n", err);
424
+
goto out;
425
+
}
426
+
427
+
pp->ops = &amd_mdb_pcie_host_ops;
428
+
429
+
err = dw_pcie_host_init(pp);
430
+
if (err) {
431
+
dev_err(dev, "Failed to initialize host, err=%d\n", err);
432
+
goto out;
433
+
}
434
+
435
+
return 0;
436
+
437
+
out:
438
+
amd_mdb_pcie_free_irq_domains(pcie);
439
+
return err;
440
+
}
441
+
442
+
static int amd_mdb_pcie_probe(struct platform_device *pdev)
443
+
{
444
+
struct device *dev = &pdev->dev;
445
+
struct amd_mdb_pcie *pcie;
446
+
struct dw_pcie *pci;
447
+
448
+
pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
449
+
if (!pcie)
450
+
return -ENOMEM;
451
+
452
+
pci = &pcie->pci;
453
+
pci->dev = dev;
454
+
455
+
platform_set_drvdata(pdev, pcie);
456
+
457
+
return amd_mdb_add_pcie_port(pcie, pdev);
458
+
}
459
+
460
+
static const struct of_device_id amd_mdb_pcie_of_match[] = {
461
+
{
462
+
.compatible = "amd,versal2-mdb-host",
463
+
},
464
+
{},
465
+
};
466
+
467
+
static struct platform_driver amd_mdb_pcie_driver = {
468
+
.driver = {
469
+
.name = "amd-mdb-pcie",
470
+
.of_match_table = amd_mdb_pcie_of_match,
471
+
.suppress_bind_attrs = true,
472
+
},
473
+
.probe = amd_mdb_pcie_probe,
474
+
};
475
+
476
+
builtin_platform_driver(amd_mdb_pcie_driver);
+677
drivers/pci/controller/dwc/pcie-designware-debugfs.c
+677
drivers/pci/controller/dwc/pcie-designware-debugfs.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* Synopsys DesignWare PCIe controller debugfs driver
4
+
*
5
+
* Copyright (C) 2025 Samsung Electronics Co., Ltd.
6
+
* http://www.samsung.com
7
+
*
8
+
* Author: Shradha Todi <shradha.t@samsung.com>
9
+
*/
10
+
11
+
#include <linux/debugfs.h>
12
+
13
+
#include "pcie-designware.h"
14
+
15
+
#define SD_STATUS_L1LANE_REG 0xb0
16
+
#define PIPE_RXVALID BIT(18)
17
+
#define PIPE_DETECT_LANE BIT(17)
18
+
#define LANE_SELECT GENMASK(3, 0)
19
+
20
+
#define ERR_INJ0_OFF 0x34
21
+
#define EINJ_VAL_DIFF GENMASK(28, 16)
22
+
#define EINJ_VC_NUM GENMASK(14, 12)
23
+
#define EINJ_TYPE_SHIFT 8
24
+
#define EINJ0_TYPE GENMASK(11, 8)
25
+
#define EINJ1_TYPE BIT(8)
26
+
#define EINJ2_TYPE GENMASK(9, 8)
27
+
#define EINJ3_TYPE GENMASK(10, 8)
28
+
#define EINJ4_TYPE GENMASK(10, 8)
29
+
#define EINJ5_TYPE BIT(8)
30
+
#define EINJ_COUNT GENMASK(7, 0)
31
+
32
+
#define ERR_INJ_ENABLE_REG 0x30
33
+
34
+
#define RAS_DES_EVENT_COUNTER_DATA_REG 0xc
35
+
36
+
#define RAS_DES_EVENT_COUNTER_CTRL_REG 0x8
37
+
#define EVENT_COUNTER_GROUP_SELECT GENMASK(27, 24)
38
+
#define EVENT_COUNTER_EVENT_SELECT GENMASK(23, 16)
39
+
#define EVENT_COUNTER_LANE_SELECT GENMASK(11, 8)
40
+
#define EVENT_COUNTER_STATUS BIT(7)
41
+
#define EVENT_COUNTER_ENABLE GENMASK(4, 2)
42
+
#define PER_EVENT_ON 0x3
43
+
#define PER_EVENT_OFF 0x1
44
+
45
+
#define DWC_DEBUGFS_BUF_MAX 128
46
+
47
+
/**
48
+
* struct dwc_pcie_rasdes_info - Stores controller common information
49
+
* @ras_cap_offset: RAS DES vendor specific extended capability offset
50
+
* @reg_event_lock: Mutex used for RAS DES shadow event registers
51
+
*
52
+
* Any parameter constant to all files of the debugfs hierarchy for a single
53
+
* controller will be stored in this struct. It is allocated and assigned to
54
+
* controller specific struct dw_pcie during initialization.
55
+
*/
56
+
struct dwc_pcie_rasdes_info {
57
+
u32 ras_cap_offset;
58
+
struct mutex reg_event_lock;
59
+
};
60
+
61
+
/**
62
+
* struct dwc_pcie_rasdes_priv - Stores file specific private data information
63
+
* @pci: Reference to the dw_pcie structure
64
+
* @idx: Index of specific file related information in array of structs
65
+
*
66
+
* All debugfs files will have this struct as its private data.
67
+
*/
68
+
struct dwc_pcie_rasdes_priv {
69
+
struct dw_pcie *pci;
70
+
int idx;
71
+
};
72
+
73
+
/**
74
+
* struct dwc_pcie_err_inj - Store details about each error injection
75
+
* supported by DWC RAS DES
76
+
* @name: Name of the error that can be injected
77
+
* @err_inj_group: Group number to which the error belongs. The value
78
+
* can range from 0 to 5
79
+
* @err_inj_type: Each group can have multiple types of error
80
+
*/
81
+
struct dwc_pcie_err_inj {
82
+
const char *name;
83
+
u32 err_inj_group;
84
+
u32 err_inj_type;
85
+
};
86
+
87
+
static const struct dwc_pcie_err_inj err_inj_list[] = {
88
+
{"tx_lcrc", 0x0, 0x0},
89
+
{"b16_crc_dllp", 0x0, 0x1},
90
+
{"b16_crc_upd_fc", 0x0, 0x2},
91
+
{"tx_ecrc", 0x0, 0x3},
92
+
{"fcrc_tlp", 0x0, 0x4},
93
+
{"parity_tsos", 0x0, 0x5},
94
+
{"parity_skpos", 0x0, 0x6},
95
+
{"rx_lcrc", 0x0, 0x8},
96
+
{"rx_ecrc", 0x0, 0xb},
97
+
{"tlp_err_seq", 0x1, 0x0},
98
+
{"ack_nak_dllp_seq", 0x1, 0x1},
99
+
{"ack_nak_dllp", 0x2, 0x0},
100
+
{"upd_fc_dllp", 0x2, 0x1},
101
+
{"nak_dllp", 0x2, 0x2},
102
+
{"inv_sync_hdr_sym", 0x3, 0x0},
103
+
{"com_pad_ts1", 0x3, 0x1},
104
+
{"com_pad_ts2", 0x3, 0x2},
105
+
{"com_fts", 0x3, 0x3},
106
+
{"com_idl", 0x3, 0x4},
107
+
{"end_edb", 0x3, 0x5},
108
+
{"stp_sdp", 0x3, 0x6},
109
+
{"com_skp", 0x3, 0x7},
110
+
{"posted_tlp_hdr", 0x4, 0x0},
111
+
{"non_post_tlp_hdr", 0x4, 0x1},
112
+
{"cmpl_tlp_hdr", 0x4, 0x2},
113
+
{"posted_tlp_data", 0x4, 0x4},
114
+
{"non_post_tlp_data", 0x4, 0x5},
115
+
{"cmpl_tlp_data", 0x4, 0x6},
116
+
{"duplicate_tlp", 0x5, 0x0},
117
+
{"nullified_tlp", 0x5, 0x1},
118
+
};
119
+
120
+
static const u32 err_inj_type_mask[] = {
121
+
EINJ0_TYPE,
122
+
EINJ1_TYPE,
123
+
EINJ2_TYPE,
124
+
EINJ3_TYPE,
125
+
EINJ4_TYPE,
126
+
EINJ5_TYPE,
127
+
};
128
+
129
+
/**
130
+
* struct dwc_pcie_event_counter - Store details about each event counter
131
+
* supported in DWC RAS DES
132
+
* @name: Name of the error counter
133
+
* @group_no: Group number that the event belongs to. The value can range
134
+
* from 0 to 4
135
+
* @event_no: Event number of the particular event. The value ranges are:
136
+
* Group 0: 0 - 10
137
+
* Group 1: 5 - 13
138
+
* Group 2: 0 - 7
139
+
* Group 3: 0 - 5
140
+
* Group 4: 0 - 1
141
+
*/
142
+
struct dwc_pcie_event_counter {
143
+
const char *name;
144
+
u32 group_no;
145
+
u32 event_no;
146
+
};
147
+
148
+
static const struct dwc_pcie_event_counter event_list[] = {
149
+
{"ebuf_overflow", 0x0, 0x0},
150
+
{"ebuf_underrun", 0x0, 0x1},
151
+
{"decode_err", 0x0, 0x2},
152
+
{"running_disparity_err", 0x0, 0x3},
153
+
{"skp_os_parity_err", 0x0, 0x4},
154
+
{"sync_header_err", 0x0, 0x5},
155
+
{"rx_valid_deassertion", 0x0, 0x6},
156
+
{"ctl_skp_os_parity_err", 0x0, 0x7},
157
+
{"retimer_parity_err_1st", 0x0, 0x8},
158
+
{"retimer_parity_err_2nd", 0x0, 0x9},
159
+
{"margin_crc_parity_err", 0x0, 0xA},
160
+
{"detect_ei_infer", 0x1, 0x5},
161
+
{"receiver_err", 0x1, 0x6},
162
+
{"rx_recovery_req", 0x1, 0x7},
163
+
{"n_fts_timeout", 0x1, 0x8},
164
+
{"framing_err", 0x1, 0x9},
165
+
{"deskew_err", 0x1, 0xa},
166
+
{"framing_err_in_l0", 0x1, 0xc},
167
+
{"deskew_uncompleted_err", 0x1, 0xd},
168
+
{"bad_tlp", 0x2, 0x0},
169
+
{"lcrc_err", 0x2, 0x1},
170
+
{"bad_dllp", 0x2, 0x2},
171
+
{"replay_num_rollover", 0x2, 0x3},
172
+
{"replay_timeout", 0x2, 0x4},
173
+
{"rx_nak_dllp", 0x2, 0x5},
174
+
{"tx_nak_dllp", 0x2, 0x6},
175
+
{"retry_tlp", 0x2, 0x7},
176
+
{"fc_timeout", 0x3, 0x0},
177
+
{"poisoned_tlp", 0x3, 0x1},
178
+
{"ecrc_error", 0x3, 0x2},
179
+
{"unsupported_request", 0x3, 0x3},
180
+
{"completer_abort", 0x3, 0x4},
181
+
{"completion_timeout", 0x3, 0x5},
182
+
{"ebuf_skp_add", 0x4, 0x0},
183
+
{"ebuf_skp_del", 0x4, 0x1},
184
+
};
185
+
186
+
static ssize_t lane_detect_read(struct file *file, char __user *buf,
187
+
size_t count, loff_t *ppos)
188
+
{
189
+
struct dw_pcie *pci = file->private_data;
190
+
struct dwc_pcie_rasdes_info *rinfo = pci->debugfs->rasdes_info;
191
+
char debugfs_buf[DWC_DEBUGFS_BUF_MAX];
192
+
ssize_t pos;
193
+
u32 val;
194
+
195
+
val = dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset + SD_STATUS_L1LANE_REG);
196
+
val = FIELD_GET(PIPE_DETECT_LANE, val);
197
+
if (val)
198
+
pos = scnprintf(debugfs_buf, DWC_DEBUGFS_BUF_MAX, "Lane Detected\n");
199
+
else
200
+
pos = scnprintf(debugfs_buf, DWC_DEBUGFS_BUF_MAX, "Lane Undetected\n");
201
+
202
+
return simple_read_from_buffer(buf, count, ppos, debugfs_buf, pos);
203
+
}
204
+
205
+
static ssize_t lane_detect_write(struct file *file, const char __user *buf,
206
+
size_t count, loff_t *ppos)
207
+
{
208
+
struct dw_pcie *pci = file->private_data;
209
+
struct dwc_pcie_rasdes_info *rinfo = pci->debugfs->rasdes_info;
210
+
u32 lane, val;
211
+
212
+
val = kstrtou32_from_user(buf, count, 0, &lane);
213
+
if (val)
214
+
return val;
215
+
216
+
val = dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset + SD_STATUS_L1LANE_REG);
217
+
val &= ~(LANE_SELECT);
218
+
val |= FIELD_PREP(LANE_SELECT, lane);
219
+
dw_pcie_writel_dbi(pci, rinfo->ras_cap_offset + SD_STATUS_L1LANE_REG, val);
220
+
221
+
return count;
222
+
}
223
+
224
+
static ssize_t rx_valid_read(struct file *file, char __user *buf,
225
+
size_t count, loff_t *ppos)
226
+
{
227
+
struct dw_pcie *pci = file->private_data;
228
+
struct dwc_pcie_rasdes_info *rinfo = pci->debugfs->rasdes_info;
229
+
char debugfs_buf[DWC_DEBUGFS_BUF_MAX];
230
+
ssize_t pos;
231
+
u32 val;
232
+
233
+
val = dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset + SD_STATUS_L1LANE_REG);
234
+
val = FIELD_GET(PIPE_RXVALID, val);
235
+
if (val)
236
+
pos = scnprintf(debugfs_buf, DWC_DEBUGFS_BUF_MAX, "RX Valid\n");
237
+
else
238
+
pos = scnprintf(debugfs_buf, DWC_DEBUGFS_BUF_MAX, "RX Invalid\n");
239
+
240
+
return simple_read_from_buffer(buf, count, ppos, debugfs_buf, pos);
241
+
}
242
+
243
+
static ssize_t rx_valid_write(struct file *file, const char __user *buf,
244
+
size_t count, loff_t *ppos)
245
+
{
246
+
return lane_detect_write(file, buf, count, ppos);
247
+
}
248
+
249
+
static ssize_t err_inj_write(struct file *file, const char __user *buf,
250
+
size_t count, loff_t *ppos)
251
+
{
252
+
struct dwc_pcie_rasdes_priv *pdata = file->private_data;
253
+
struct dw_pcie *pci = pdata->pci;
254
+
struct dwc_pcie_rasdes_info *rinfo = pci->debugfs->rasdes_info;
255
+
u32 val, counter, vc_num, err_group, type_mask;
256
+
int val_diff = 0;
257
+
char *kern_buf;
258
+
259
+
err_group = err_inj_list[pdata->idx].err_inj_group;
260
+
type_mask = err_inj_type_mask[err_group];
261
+
262
+
kern_buf = memdup_user_nul(buf, count);
263
+
if (IS_ERR(kern_buf))
264
+
return PTR_ERR(kern_buf);
265
+
266
+
if (err_group == 4) {
267
+
val = sscanf(kern_buf, "%u %d %u", &counter, &val_diff, &vc_num);
268
+
if ((val != 3) || (val_diff < -4095 || val_diff > 4095)) {
269
+
kfree(kern_buf);
270
+
return -EINVAL;
271
+
}
272
+
} else if (err_group == 1) {
273
+
val = sscanf(kern_buf, "%u %d", &counter, &val_diff);
274
+
if ((val != 2) || (val_diff < -4095 || val_diff > 4095)) {
275
+
kfree(kern_buf);
276
+
return -EINVAL;
277
+
}
278
+
} else {
279
+
val = kstrtou32(kern_buf, 0, &counter);
280
+
if (val) {
281
+
kfree(kern_buf);
282
+
return val;
283
+
}
284
+
}
285
+
286
+
val = dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset + ERR_INJ0_OFF + (0x4 * err_group));
287
+
val &= ~(type_mask | EINJ_COUNT);
288
+
val |= ((err_inj_list[pdata->idx].err_inj_type << EINJ_TYPE_SHIFT) & type_mask);
289
+
val |= FIELD_PREP(EINJ_COUNT, counter);
290
+
291
+
if (err_group == 1 || err_group == 4) {
292
+
val &= ~(EINJ_VAL_DIFF);
293
+
val |= FIELD_PREP(EINJ_VAL_DIFF, val_diff);
294
+
}
295
+
if (err_group == 4) {
296
+
val &= ~(EINJ_VC_NUM);
297
+
val |= FIELD_PREP(EINJ_VC_NUM, vc_num);
298
+
}
299
+
300
+
dw_pcie_writel_dbi(pci, rinfo->ras_cap_offset + ERR_INJ0_OFF + (0x4 * err_group), val);
301
+
dw_pcie_writel_dbi(pci, rinfo->ras_cap_offset + ERR_INJ_ENABLE_REG, (0x1 << err_group));
302
+
303
+
kfree(kern_buf);
304
+
return count;
305
+
}
306
+
307
+
static void set_event_number(struct dwc_pcie_rasdes_priv *pdata,
308
+
struct dw_pcie *pci, struct dwc_pcie_rasdes_info *rinfo)
309
+
{
310
+
u32 val;
311
+
312
+
val = dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset + RAS_DES_EVENT_COUNTER_CTRL_REG);
313
+
val &= ~EVENT_COUNTER_ENABLE;
314
+
val &= ~(EVENT_COUNTER_GROUP_SELECT | EVENT_COUNTER_EVENT_SELECT);
315
+
val |= FIELD_PREP(EVENT_COUNTER_GROUP_SELECT, event_list[pdata->idx].group_no);
316
+
val |= FIELD_PREP(EVENT_COUNTER_EVENT_SELECT, event_list[pdata->idx].event_no);
317
+
dw_pcie_writel_dbi(pci, rinfo->ras_cap_offset + RAS_DES_EVENT_COUNTER_CTRL_REG, val);
318
+
}
319
+
320
+
static ssize_t counter_enable_read(struct file *file, char __user *buf,
321
+
size_t count, loff_t *ppos)
322
+
{
323
+
struct dwc_pcie_rasdes_priv *pdata = file->private_data;
324
+
struct dw_pcie *pci = pdata->pci;
325
+
struct dwc_pcie_rasdes_info *rinfo = pci->debugfs->rasdes_info;
326
+
char debugfs_buf[DWC_DEBUGFS_BUF_MAX];
327
+
ssize_t pos;
328
+
u32 val;
329
+
330
+
mutex_lock(&rinfo->reg_event_lock);
331
+
set_event_number(pdata, pci, rinfo);
332
+
val = dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset + RAS_DES_EVENT_COUNTER_CTRL_REG);
333
+
mutex_unlock(&rinfo->reg_event_lock);
334
+
val = FIELD_GET(EVENT_COUNTER_STATUS, val);
335
+
if (val)
336
+
pos = scnprintf(debugfs_buf, DWC_DEBUGFS_BUF_MAX, "Counter Enabled\n");
337
+
else
338
+
pos = scnprintf(debugfs_buf, DWC_DEBUGFS_BUF_MAX, "Counter Disabled\n");
339
+
340
+
return simple_read_from_buffer(buf, count, ppos, debugfs_buf, pos);
341
+
}
342
+
343
+
static ssize_t counter_enable_write(struct file *file, const char __user *buf,
344
+
size_t count, loff_t *ppos)
345
+
{
346
+
struct dwc_pcie_rasdes_priv *pdata = file->private_data;
347
+
struct dw_pcie *pci = pdata->pci;
348
+
struct dwc_pcie_rasdes_info *rinfo = pci->debugfs->rasdes_info;
349
+
u32 val, enable;
350
+
351
+
val = kstrtou32_from_user(buf, count, 0, &enable);
352
+
if (val)
353
+
return val;
354
+
355
+
mutex_lock(&rinfo->reg_event_lock);
356
+
set_event_number(pdata, pci, rinfo);
357
+
val = dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset + RAS_DES_EVENT_COUNTER_CTRL_REG);
358
+
if (enable)
359
+
val |= FIELD_PREP(EVENT_COUNTER_ENABLE, PER_EVENT_ON);
360
+
else
361
+
val |= FIELD_PREP(EVENT_COUNTER_ENABLE, PER_EVENT_OFF);
362
+
363
+
dw_pcie_writel_dbi(pci, rinfo->ras_cap_offset + RAS_DES_EVENT_COUNTER_CTRL_REG, val);
364
+
365
+
/*
366
+
* While enabling the counter, always read the status back to check if
367
+
* it is enabled or not. Return error if it is not enabled to let the
368
+
* users know that the counter is not supported on the platform.
369
+
*/
370
+
if (enable) {
371
+
val = dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset +
372
+
RAS_DES_EVENT_COUNTER_CTRL_REG);
373
+
if (!FIELD_GET(EVENT_COUNTER_STATUS, val)) {
374
+
mutex_unlock(&rinfo->reg_event_lock);
375
+
return -EOPNOTSUPP;
376
+
}
377
+
}
378
+
379
+
mutex_unlock(&rinfo->reg_event_lock);
380
+
381
+
return count;
382
+
}
383
+
384
+
static ssize_t counter_lane_read(struct file *file, char __user *buf,
385
+
size_t count, loff_t *ppos)
386
+
{
387
+
struct dwc_pcie_rasdes_priv *pdata = file->private_data;
388
+
struct dw_pcie *pci = pdata->pci;
389
+
struct dwc_pcie_rasdes_info *rinfo = pci->debugfs->rasdes_info;
390
+
char debugfs_buf[DWC_DEBUGFS_BUF_MAX];
391
+
ssize_t pos;
392
+
u32 val;
393
+
394
+
mutex_lock(&rinfo->reg_event_lock);
395
+
set_event_number(pdata, pci, rinfo);
396
+
val = dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset + RAS_DES_EVENT_COUNTER_CTRL_REG);
397
+
mutex_unlock(&rinfo->reg_event_lock);
398
+
val = FIELD_GET(EVENT_COUNTER_LANE_SELECT, val);
399
+
pos = scnprintf(debugfs_buf, DWC_DEBUGFS_BUF_MAX, "Lane: %d\n", val);
400
+
401
+
return simple_read_from_buffer(buf, count, ppos, debugfs_buf, pos);
402
+
}
403
+
404
+
static ssize_t counter_lane_write(struct file *file, const char __user *buf,
405
+
size_t count, loff_t *ppos)
406
+
{
407
+
struct dwc_pcie_rasdes_priv *pdata = file->private_data;
408
+
struct dw_pcie *pci = pdata->pci;
409
+
struct dwc_pcie_rasdes_info *rinfo = pci->debugfs->rasdes_info;
410
+
u32 val, lane;
411
+
412
+
val = kstrtou32_from_user(buf, count, 0, &lane);
413
+
if (val)
414
+
return val;
415
+
416
+
mutex_lock(&rinfo->reg_event_lock);
417
+
set_event_number(pdata, pci, rinfo);
418
+
val = dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset + RAS_DES_EVENT_COUNTER_CTRL_REG);
419
+
val &= ~(EVENT_COUNTER_LANE_SELECT);
420
+
val |= FIELD_PREP(EVENT_COUNTER_LANE_SELECT, lane);
421
+
dw_pcie_writel_dbi(pci, rinfo->ras_cap_offset + RAS_DES_EVENT_COUNTER_CTRL_REG, val);
422
+
mutex_unlock(&rinfo->reg_event_lock);
423
+
424
+
return count;
425
+
}
426
+
427
+
static ssize_t counter_value_read(struct file *file, char __user *buf,
428
+
size_t count, loff_t *ppos)
429
+
{
430
+
struct dwc_pcie_rasdes_priv *pdata = file->private_data;
431
+
struct dw_pcie *pci = pdata->pci;
432
+
struct dwc_pcie_rasdes_info *rinfo = pci->debugfs->rasdes_info;
433
+
char debugfs_buf[DWC_DEBUGFS_BUF_MAX];
434
+
ssize_t pos;
435
+
u32 val;
436
+
437
+
mutex_lock(&rinfo->reg_event_lock);
438
+
set_event_number(pdata, pci, rinfo);
439
+
val = dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset + RAS_DES_EVENT_COUNTER_DATA_REG);
440
+
mutex_unlock(&rinfo->reg_event_lock);
441
+
pos = scnprintf(debugfs_buf, DWC_DEBUGFS_BUF_MAX, "Counter value: %d\n", val);
442
+
443
+
return simple_read_from_buffer(buf, count, ppos, debugfs_buf, pos);
444
+
}
445
+
446
+
static const char *ltssm_status_string(enum dw_pcie_ltssm ltssm)
447
+
{
448
+
const char *str;
449
+
450
+
switch (ltssm) {
451
+
#define DW_PCIE_LTSSM_NAME(n) case n: str = #n; break
452
+
DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_DETECT_QUIET);
453
+
DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_DETECT_ACT);
454
+
DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_POLL_ACTIVE);
455
+
DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_POLL_COMPLIANCE);
456
+
DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_POLL_CONFIG);
457
+
DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_PRE_DETECT_QUIET);
458
+
DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_DETECT_WAIT);
459
+
DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_CFG_LINKWD_START);
460
+
DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_CFG_LINKWD_ACEPT);
461
+
DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_CFG_LANENUM_WAI);
462
+
DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_CFG_LANENUM_ACEPT);
463
+
DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_CFG_COMPLETE);
464
+
DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_CFG_IDLE);
465
+
DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_RCVRY_LOCK);
466
+
DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_RCVRY_SPEED);
467
+
DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_RCVRY_RCVRCFG);
468
+
DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_RCVRY_IDLE);
469
+
DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_L0);
470
+
DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_L0S);
471
+
DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_L123_SEND_EIDLE);
472
+
DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_L1_IDLE);
473
+
DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_L2_IDLE);
474
+
DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_L2_WAKE);
475
+
DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_DISABLED_ENTRY);
476
+
DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_DISABLED_IDLE);
477
+
DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_DISABLED);
478
+
DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_LPBK_ENTRY);
479
+
DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_LPBK_ACTIVE);
480
+
DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_LPBK_EXIT);
481
+
DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_LPBK_EXIT_TIMEOUT);
482
+
DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_HOT_RESET_ENTRY);
483
+
DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_HOT_RESET);
484
+
DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_RCVRY_EQ0);
485
+
DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_RCVRY_EQ1);
486
+
DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_RCVRY_EQ2);
487
+
DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_RCVRY_EQ3);
488
+
default:
489
+
str = "DW_PCIE_LTSSM_UNKNOWN";
490
+
break;
491
+
}
492
+
493
+
return str + strlen("DW_PCIE_LTSSM_");
494
+
}
495
+
496
+
static int ltssm_status_show(struct seq_file *s, void *v)
497
+
{
498
+
struct dw_pcie *pci = s->private;
499
+
enum dw_pcie_ltssm val;
500
+
501
+
val = dw_pcie_get_ltssm(pci);
502
+
seq_printf(s, "%s (0x%02x)\n", ltssm_status_string(val), val);
503
+
504
+
return 0;
505
+
}
506
+
507
+
static int ltssm_status_open(struct inode *inode, struct file *file)
508
+
{
509
+
return single_open(file, ltssm_status_show, inode->i_private);
510
+
}
511
+
512
+
#define dwc_debugfs_create(name) \
513
+
debugfs_create_file(#name, 0644, rasdes_debug, pci, \
514
+
&dbg_ ## name ## _fops)
515
+
516
+
#define DWC_DEBUGFS_FOPS(name) \
517
+
static const struct file_operations dbg_ ## name ## _fops = { \
518
+
.open = simple_open, \
519
+
.read = name ## _read, \
520
+
.write = name ## _write \
521
+
}
522
+
523
+
DWC_DEBUGFS_FOPS(lane_detect);
524
+
DWC_DEBUGFS_FOPS(rx_valid);
525
+
526
+
static const struct file_operations dwc_pcie_err_inj_ops = {
527
+
.open = simple_open,
528
+
.write = err_inj_write,
529
+
};
530
+
531
+
static const struct file_operations dwc_pcie_counter_enable_ops = {
532
+
.open = simple_open,
533
+
.read = counter_enable_read,
534
+
.write = counter_enable_write,
535
+
};
536
+
537
+
static const struct file_operations dwc_pcie_counter_lane_ops = {
538
+
.open = simple_open,
539
+
.read = counter_lane_read,
540
+
.write = counter_lane_write,
541
+
};
542
+
543
+
static const struct file_operations dwc_pcie_counter_value_ops = {
544
+
.open = simple_open,
545
+
.read = counter_value_read,
546
+
};
547
+
548
+
static const struct file_operations dwc_pcie_ltssm_status_ops = {
549
+
.open = ltssm_status_open,
550
+
.read = seq_read,
551
+
};
552
+
553
+
static void dwc_pcie_rasdes_debugfs_deinit(struct dw_pcie *pci)
554
+
{
555
+
struct dwc_pcie_rasdes_info *rinfo = pci->debugfs->rasdes_info;
556
+
557
+
mutex_destroy(&rinfo->reg_event_lock);
558
+
}
559
+
560
+
static int dwc_pcie_rasdes_debugfs_init(struct dw_pcie *pci, struct dentry *dir)
561
+
{
562
+
struct dentry *rasdes_debug, *rasdes_err_inj;
563
+
struct dentry *rasdes_event_counter, *rasdes_events;
564
+
struct dwc_pcie_rasdes_info *rasdes_info;
565
+
struct dwc_pcie_rasdes_priv *priv_tmp;
566
+
struct device *dev = pci->dev;
567
+
int ras_cap, i, ret;
568
+
569
+
/*
570
+
* If a given SoC has no RAS DES capability, the following call is
571
+
* bound to return an error, breaking some existing platforms. So,
572
+
* return 0 here, as this is not necessarily an error.
573
+
*/
574
+
ras_cap = dw_pcie_find_rasdes_capability(pci);
575
+
if (!ras_cap) {
576
+
dev_dbg(dev, "no RAS DES capability available\n");
577
+
return 0;
578
+
}
579
+
580
+
rasdes_info = devm_kzalloc(dev, sizeof(*rasdes_info), GFP_KERNEL);
581
+
if (!rasdes_info)
582
+
return -ENOMEM;
583
+
584
+
/* Create subdirectories for Debug, Error Injection, Statistics. */
585
+
rasdes_debug = debugfs_create_dir("rasdes_debug", dir);
586
+
rasdes_err_inj = debugfs_create_dir("rasdes_err_inj", dir);
587
+
rasdes_event_counter = debugfs_create_dir("rasdes_event_counter", dir);
588
+
589
+
mutex_init(&rasdes_info->reg_event_lock);
590
+
rasdes_info->ras_cap_offset = ras_cap;
591
+
pci->debugfs->rasdes_info = rasdes_info;
592
+
593
+
/* Create debugfs files for Debug subdirectory. */
594
+
dwc_debugfs_create(lane_detect);
595
+
dwc_debugfs_create(rx_valid);
596
+
597
+
/* Create debugfs files for Error Injection subdirectory. */
598
+
for (i = 0; i < ARRAY_SIZE(err_inj_list); i++) {
599
+
priv_tmp = devm_kzalloc(dev, sizeof(*priv_tmp), GFP_KERNEL);
600
+
if (!priv_tmp) {
601
+
ret = -ENOMEM;
602
+
goto err_deinit;
603
+
}
604
+
605
+
priv_tmp->idx = i;
606
+
priv_tmp->pci = pci;
607
+
debugfs_create_file(err_inj_list[i].name, 0200, rasdes_err_inj, priv_tmp,
608
+
&dwc_pcie_err_inj_ops);
609
+
}
610
+
611
+
/* Create debugfs files for Statistical Counter subdirectory. */
612
+
for (i = 0; i < ARRAY_SIZE(event_list); i++) {
613
+
priv_tmp = devm_kzalloc(dev, sizeof(*priv_tmp), GFP_KERNEL);
614
+
if (!priv_tmp) {
615
+
ret = -ENOMEM;
616
+
goto err_deinit;
617
+
}
618
+
619
+
priv_tmp->idx = i;
620
+
priv_tmp->pci = pci;
621
+
rasdes_events = debugfs_create_dir(event_list[i].name, rasdes_event_counter);
622
+
if (event_list[i].group_no == 0 || event_list[i].group_no == 4) {
623
+
debugfs_create_file("lane_select", 0644, rasdes_events,
624
+
priv_tmp, &dwc_pcie_counter_lane_ops);
625
+
}
626
+
debugfs_create_file("counter_value", 0444, rasdes_events, priv_tmp,
627
+
&dwc_pcie_counter_value_ops);
628
+
debugfs_create_file("counter_enable", 0644, rasdes_events, priv_tmp,
629
+
&dwc_pcie_counter_enable_ops);
630
+
}
631
+
632
+
return 0;
633
+
634
+
err_deinit:
635
+
dwc_pcie_rasdes_debugfs_deinit(pci);
636
+
return ret;
637
+
}
638
+
639
+
static void dwc_pcie_ltssm_debugfs_init(struct dw_pcie *pci, struct dentry *dir)
640
+
{
641
+
debugfs_create_file("ltssm_status", 0444, dir, pci,
642
+
&dwc_pcie_ltssm_status_ops);
643
+
}
644
+
645
+
void dwc_pcie_debugfs_deinit(struct dw_pcie *pci)
646
+
{
647
+
if (!pci->debugfs)
648
+
return;
649
+
650
+
dwc_pcie_rasdes_debugfs_deinit(pci);
651
+
debugfs_remove_recursive(pci->debugfs->debug_dir);
652
+
}
653
+
654
+
void dwc_pcie_debugfs_init(struct dw_pcie *pci)
655
+
{
656
+
char dirname[DWC_DEBUGFS_BUF_MAX];
657
+
struct device *dev = pci->dev;
658
+
struct debugfs_info *debugfs;
659
+
struct dentry *dir;
660
+
int err;
661
+
662
+
/* Create main directory for each platform driver. */
663
+
snprintf(dirname, DWC_DEBUGFS_BUF_MAX, "dwc_pcie_%s", dev_name(dev));
664
+
dir = debugfs_create_dir(dirname, NULL);
665
+
debugfs = devm_kzalloc(dev, sizeof(*debugfs), GFP_KERNEL);
666
+
if (!debugfs)
667
+
return;
668
+
669
+
debugfs->debug_dir = dir;
670
+
pci->debugfs = debugfs;
671
+
err = dwc_pcie_rasdes_debugfs_init(pci, dir);
672
+
if (err)
673
+
dev_err(dev, "failed to initialize RAS DES debugfs, err=%d\n",
674
+
err);
675
+
676
+
dwc_pcie_ltssm_debugfs_init(pci, dir);
677
+
}
+260
-61
drivers/pci/controller/dwc/pcie-designware-ep.c
+260
-61
drivers/pci/controller/dwc/pcie-designware-ep.c
···
102
102
return __dw_pcie_ep_find_next_cap(ep, func_no, next_cap_ptr, cap);
103
103
}
104
104
105
+
/**
106
+
* dw_pcie_ep_hide_ext_capability - Hide a capability from the linked list
107
+
* @pci: DWC PCI device
108
+
* @prev_cap: Capability preceding the capability that should be hidden
109
+
* @cap: Capability that should be hidden
110
+
*
111
+
* Return: 0 if success, errno otherwise.
112
+
*/
113
+
int dw_pcie_ep_hide_ext_capability(struct dw_pcie *pci, u8 prev_cap, u8 cap)
114
+
{
115
+
u16 prev_cap_offset, cap_offset;
116
+
u32 prev_cap_header, cap_header;
117
+
118
+
prev_cap_offset = dw_pcie_find_ext_capability(pci, prev_cap);
119
+
if (!prev_cap_offset)
120
+
return -EINVAL;
121
+
122
+
prev_cap_header = dw_pcie_readl_dbi(pci, prev_cap_offset);
123
+
cap_offset = PCI_EXT_CAP_NEXT(prev_cap_header);
124
+
cap_header = dw_pcie_readl_dbi(pci, cap_offset);
125
+
126
+
/* cap must immediately follow prev_cap. */
127
+
if (PCI_EXT_CAP_ID(cap_header) != cap)
128
+
return -EINVAL;
129
+
130
+
/* Clear next ptr. */
131
+
prev_cap_header &= ~GENMASK(31, 20);
132
+
133
+
/* Set next ptr to next ptr of cap. */
134
+
prev_cap_header |= cap_header & GENMASK(31, 20);
135
+
136
+
dw_pcie_dbi_ro_wr_en(pci);
137
+
dw_pcie_writel_dbi(pci, prev_cap_offset, prev_cap_header);
138
+
dw_pcie_dbi_ro_wr_dis(pci);
139
+
140
+
return 0;
141
+
}
142
+
EXPORT_SYMBOL_GPL(dw_pcie_ep_hide_ext_capability);
143
+
105
144
static int dw_pcie_ep_write_header(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
106
145
struct pci_epf_header *hdr)
107
146
{
···
167
128
}
168
129
169
130
static int dw_pcie_ep_inbound_atu(struct dw_pcie_ep *ep, u8 func_no, int type,
170
-
dma_addr_t cpu_addr, enum pci_barno bar,
131
+
dma_addr_t parent_bus_addr, enum pci_barno bar,
171
132
size_t size)
172
133
{
173
134
int ret;
···
185
146
}
186
147
187
148
ret = dw_pcie_prog_ep_inbound_atu(pci, func_no, free_win, type,
188
-
cpu_addr, bar, size);
149
+
parent_bus_addr, bar, size);
189
150
if (ret < 0) {
190
151
dev_err(pci->dev, "Failed to program IB window\n");
191
152
return ret;
···
220
181
return ret;
221
182
222
183
set_bit(free_win, ep->ob_window_map);
223
-
ep->outbound_addr[free_win] = atu->cpu_addr;
184
+
ep->outbound_addr[free_win] = atu->parent_bus_addr;
224
185
225
186
return 0;
226
187
}
···
244
205
ep->bar_to_atu[bar] = 0;
245
206
}
246
207
208
+
static unsigned int dw_pcie_ep_get_rebar_offset(struct dw_pcie *pci,
209
+
enum pci_barno bar)
210
+
{
211
+
u32 reg, bar_index;
212
+
unsigned int offset, nbars;
213
+
int i;
214
+
215
+
offset = dw_pcie_find_ext_capability(pci, PCI_EXT_CAP_ID_REBAR);
216
+
if (!offset)
217
+
return offset;
218
+
219
+
reg = dw_pcie_readl_dbi(pci, offset + PCI_REBAR_CTRL);
220
+
nbars = (reg & PCI_REBAR_CTRL_NBAR_MASK) >> PCI_REBAR_CTRL_NBAR_SHIFT;
221
+
222
+
for (i = 0; i < nbars; i++, offset += PCI_REBAR_CTRL) {
223
+
reg = dw_pcie_readl_dbi(pci, offset + PCI_REBAR_CTRL);
224
+
bar_index = reg & PCI_REBAR_CTRL_BAR_IDX;
225
+
if (bar_index == bar)
226
+
return offset;
227
+
}
228
+
229
+
return 0;
230
+
}
231
+
232
+
static int dw_pcie_ep_set_bar_resizable(struct dw_pcie_ep *ep, u8 func_no,
233
+
struct pci_epf_bar *epf_bar)
234
+
{
235
+
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
236
+
enum pci_barno bar = epf_bar->barno;
237
+
size_t size = epf_bar->size;
238
+
int flags = epf_bar->flags;
239
+
u32 reg = PCI_BASE_ADDRESS_0 + (4 * bar);
240
+
unsigned int rebar_offset;
241
+
u32 rebar_cap, rebar_ctrl;
242
+
int ret;
243
+
244
+
rebar_offset = dw_pcie_ep_get_rebar_offset(pci, bar);
245
+
if (!rebar_offset)
246
+
return -EINVAL;
247
+
248
+
ret = pci_epc_bar_size_to_rebar_cap(size, &rebar_cap);
249
+
if (ret)
250
+
return ret;
251
+
252
+
dw_pcie_dbi_ro_wr_en(pci);
253
+
254
+
/*
255
+
* A BAR mask should not be written for a resizable BAR. The BAR mask
256
+
* is automatically derived by the controller every time the "selected
257
+
* size" bits are updated, see "Figure 3-26 Resizable BAR Example for
258
+
* 32-bit Memory BAR0" in DWC EP databook 5.96a. We simply need to write
259
+
* BIT(0) to set the BAR enable bit.
260
+
*/
261
+
dw_pcie_ep_writel_dbi2(ep, func_no, reg, BIT(0));
262
+
dw_pcie_ep_writel_dbi(ep, func_no, reg, flags);
263
+
264
+
if (flags & PCI_BASE_ADDRESS_MEM_TYPE_64) {
265
+
dw_pcie_ep_writel_dbi2(ep, func_no, reg + 4, 0);
266
+
dw_pcie_ep_writel_dbi(ep, func_no, reg + 4, 0);
267
+
}
268
+
269
+
/*
270
+
* Bits 31:0 in PCI_REBAR_CAP define "supported sizes" bits for sizes
271
+
* 1 MB to 128 TB. Bits 31:16 in PCI_REBAR_CTRL define "supported sizes"
272
+
* bits for sizes 256 TB to 8 EB. Disallow sizes 256 TB to 8 EB.
273
+
*/
274
+
rebar_ctrl = dw_pcie_readl_dbi(pci, rebar_offset + PCI_REBAR_CTRL);
275
+
rebar_ctrl &= ~GENMASK(31, 16);
276
+
dw_pcie_writel_dbi(pci, rebar_offset + PCI_REBAR_CTRL, rebar_ctrl);
277
+
278
+
/*
279
+
* The "selected size" (bits 13:8) in PCI_REBAR_CTRL are automatically
280
+
* updated when writing PCI_REBAR_CAP, see "Figure 3-26 Resizable BAR
281
+
* Example for 32-bit Memory BAR0" in DWC EP databook 5.96a.
282
+
*/
283
+
dw_pcie_writel_dbi(pci, rebar_offset + PCI_REBAR_CAP, rebar_cap);
284
+
285
+
dw_pcie_dbi_ro_wr_dis(pci);
286
+
287
+
return 0;
288
+
}
289
+
290
+
static int dw_pcie_ep_set_bar_programmable(struct dw_pcie_ep *ep, u8 func_no,
291
+
struct pci_epf_bar *epf_bar)
292
+
{
293
+
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
294
+
enum pci_barno bar = epf_bar->barno;
295
+
size_t size = epf_bar->size;
296
+
int flags = epf_bar->flags;
297
+
u32 reg = PCI_BASE_ADDRESS_0 + (4 * bar);
298
+
299
+
dw_pcie_dbi_ro_wr_en(pci);
300
+
301
+
dw_pcie_ep_writel_dbi2(ep, func_no, reg, lower_32_bits(size - 1));
302
+
dw_pcie_ep_writel_dbi(ep, func_no, reg, flags);
303
+
304
+
if (flags & PCI_BASE_ADDRESS_MEM_TYPE_64) {
305
+
dw_pcie_ep_writel_dbi2(ep, func_no, reg + 4, upper_32_bits(size - 1));
306
+
dw_pcie_ep_writel_dbi(ep, func_no, reg + 4, 0);
307
+
}
308
+
309
+
dw_pcie_dbi_ro_wr_dis(pci);
310
+
311
+
return 0;
312
+
}
313
+
314
+
static enum pci_epc_bar_type dw_pcie_ep_get_bar_type(struct dw_pcie_ep *ep,
315
+
enum pci_barno bar)
316
+
{
317
+
const struct pci_epc_features *epc_features;
318
+
319
+
if (!ep->ops->get_features)
320
+
return BAR_PROGRAMMABLE;
321
+
322
+
epc_features = ep->ops->get_features(ep);
323
+
324
+
return epc_features->bar[bar].type;
325
+
}
326
+
247
327
static int dw_pcie_ep_set_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
248
328
struct pci_epf_bar *epf_bar)
249
329
{
···
370
212
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
371
213
enum pci_barno bar = epf_bar->barno;
372
214
size_t size = epf_bar->size;
215
+
enum pci_epc_bar_type bar_type;
373
216
int flags = epf_bar->flags;
374
217
int ret, type;
375
-
u32 reg;
376
218
377
219
/*
378
220
* DWC does not allow BAR pairs to overlap, e.g. you cannot combine BARs
···
404
246
goto config_atu;
405
247
}
406
248
407
-
reg = PCI_BASE_ADDRESS_0 + (4 * bar);
408
-
409
-
dw_pcie_dbi_ro_wr_en(pci);
410
-
411
-
dw_pcie_ep_writel_dbi2(ep, func_no, reg, lower_32_bits(size - 1));
412
-
dw_pcie_ep_writel_dbi(ep, func_no, reg, flags);
413
-
414
-
if (flags & PCI_BASE_ADDRESS_MEM_TYPE_64) {
415
-
dw_pcie_ep_writel_dbi2(ep, func_no, reg + 4, upper_32_bits(size - 1));
416
-
dw_pcie_ep_writel_dbi(ep, func_no, reg + 4, 0);
249
+
bar_type = dw_pcie_ep_get_bar_type(ep, bar);
250
+
switch (bar_type) {
251
+
case BAR_FIXED:
252
+
/*
253
+
* There is no need to write a BAR mask for a fixed BAR (except
254
+
* to write 1 to the LSB of the BAR mask register, to enable the
255
+
* BAR). Write the BAR mask regardless. (The fixed bits in the
256
+
* BAR mask register will be read-only anyway.)
257
+
*/
258
+
fallthrough;
259
+
case BAR_PROGRAMMABLE:
260
+
ret = dw_pcie_ep_set_bar_programmable(ep, func_no, epf_bar);
261
+
break;
262
+
case BAR_RESIZABLE:
263
+
ret = dw_pcie_ep_set_bar_resizable(ep, func_no, epf_bar);
264
+
break;
265
+
default:
266
+
ret = -EINVAL;
267
+
dev_err(pci->dev, "Invalid BAR type\n");
268
+
break;
417
269
}
418
270
419
-
dw_pcie_dbi_ro_wr_dis(pci);
271
+
if (ret)
272
+
return ret;
420
273
421
274
config_atu:
422
275
if (!(flags & PCI_BASE_ADDRESS_SPACE))
···
451
282
u32 index;
452
283
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
453
284
454
-
for (index = 0; index < pci->num_ob_windows; index++) {
285
+
for_each_set_bit(index, ep->ob_window_map, pci->num_ob_windows) {
455
286
if (ep->outbound_addr[index] != addr)
456
287
continue;
457
288
*atu_index = index;
···
483
314
struct dw_pcie_ep *ep = epc_get_drvdata(epc);
484
315
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
485
316
486
-
ret = dw_pcie_find_index(ep, addr, &atu_index);
317
+
ret = dw_pcie_find_index(ep, addr - pci->parent_bus_offset,
318
+
&atu_index);
487
319
if (ret < 0)
488
320
return;
489
321
···
503
333
504
334
atu.func_no = func_no;
505
335
atu.type = PCIE_ATU_TYPE_MEM;
506
-
atu.cpu_addr = addr;
336
+
atu.parent_bus_addr = addr - pci->parent_bus_offset;
507
337
atu.pci_addr = pci_addr;
508
338
atu.size = size;
509
339
ret = dw_pcie_ep_outbound_atu(ep, &atu);
···
836
666
{
837
667
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
838
668
669
+
dwc_pcie_debugfs_deinit(pci);
839
670
dw_pcie_edma_remove(pci);
840
671
}
841
672
EXPORT_SYMBOL_GPL(dw_pcie_ep_cleanup);
···
861
690
}
862
691
EXPORT_SYMBOL_GPL(dw_pcie_ep_deinit);
863
692
864
-
static unsigned int dw_pcie_ep_find_ext_capability(struct dw_pcie *pci, int cap)
865
-
{
866
-
u32 header;
867
-
int pos = PCI_CFG_SPACE_SIZE;
868
-
869
-
while (pos) {
870
-
header = dw_pcie_readl_dbi(pci, pos);
871
-
if (PCI_EXT_CAP_ID(header) == cap)
872
-
return pos;
873
-
874
-
pos = PCI_EXT_CAP_NEXT(header);
875
-
if (!pos)
876
-
break;
877
-
}
878
-
879
-
return 0;
880
-
}
881
-
882
693
static void dw_pcie_ep_init_non_sticky_registers(struct dw_pcie *pci)
883
694
{
695
+
struct dw_pcie_ep *ep = &pci->ep;
884
696
unsigned int offset;
885
697
unsigned int nbars;
886
-
u32 reg, i;
698
+
enum pci_barno bar;
699
+
u32 reg, i, val;
887
700
888
-
offset = dw_pcie_ep_find_ext_capability(pci, PCI_EXT_CAP_ID_REBAR);
701
+
offset = dw_pcie_find_ext_capability(pci, PCI_EXT_CAP_ID_REBAR);
889
702
890
703
dw_pcie_dbi_ro_wr_en(pci);
891
704
···
882
727
* PCIe r6.0, sec 7.8.6.2 require us to support at least one
883
728
* size in the range from 1 MB to 512 GB. Advertise support
884
729
* for 1 MB BAR size only.
730
+
*
731
+
* For a BAR that has been configured via dw_pcie_ep_set_bar(),
732
+
* advertise support for only that size instead.
885
733
*/
886
-
for (i = 0; i < nbars; i++, offset += PCI_REBAR_CTRL)
887
-
dw_pcie_writel_dbi(pci, offset + PCI_REBAR_CAP, BIT(4));
734
+
for (i = 0; i < nbars; i++, offset += PCI_REBAR_CTRL) {
735
+
/*
736
+
* While the RESBAR_CAP_REG_* fields are sticky, the
737
+
* RESBAR_CTRL_REG_BAR_SIZE field is non-sticky (it is
738
+
* sticky in certain versions of DWC PCIe, but not all).
739
+
*
740
+
* RESBAR_CTRL_REG_BAR_SIZE is updated automatically by
741
+
* the controller when RESBAR_CAP_REG is written, which
742
+
* is why RESBAR_CAP_REG is written here.
743
+
*/
744
+
val = dw_pcie_readl_dbi(pci, offset + PCI_REBAR_CTRL);
745
+
bar = val & PCI_REBAR_CTRL_BAR_IDX;
746
+
if (ep->epf_bar[bar])
747
+
pci_epc_bar_size_to_rebar_cap(ep->epf_bar[bar]->size, &val);
748
+
else
749
+
val = BIT(4);
750
+
751
+
dw_pcie_writel_dbi(pci, offset + PCI_REBAR_CAP, val);
752
+
}
888
753
}
889
754
890
755
dw_pcie_setup(pci);
···
948
773
if (ret)
949
774
return ret;
950
775
776
+
ret = -ENOMEM;
951
777
if (!ep->ib_window_map) {
952
778
ep->ib_window_map = devm_bitmap_zalloc(dev, pci->num_ib_windows,
953
779
GFP_KERNEL);
···
993
817
if (ep->ops->init)
994
818
ep->ops->init(ep);
995
819
996
-
ptm_cap_base = dw_pcie_ep_find_ext_capability(pci, PCI_EXT_CAP_ID_PTM);
820
+
ptm_cap_base = dw_pcie_find_ext_capability(pci, PCI_EXT_CAP_ID_PTM);
997
821
998
822
/*
999
823
* PTM responder capability can be disabled only after disabling
···
1012
836
}
1013
837
1014
838
dw_pcie_ep_init_non_sticky_registers(pci);
839
+
840
+
dwc_pcie_debugfs_init(pci);
1015
841
1016
842
return 0;
1017
843
···
1061
883
}
1062
884
EXPORT_SYMBOL_GPL(dw_pcie_ep_linkdown);
1063
885
1064
-
/**
1065
-
* dw_pcie_ep_init - Initialize the endpoint device
1066
-
* @ep: DWC EP device
1067
-
*
1068
-
* Initialize the endpoint device. Allocate resources and create the EPC
1069
-
* device with the endpoint framework.
1070
-
*
1071
-
* Return: 0 if success, errno otherwise.
1072
-
*/
1073
-
int dw_pcie_ep_init(struct dw_pcie_ep *ep)
886
+
static int dw_pcie_ep_get_resources(struct dw_pcie_ep *ep)
1074
887
{
1075
-
int ret;
1076
-
struct resource *res;
1077
-
struct pci_epc *epc;
1078
888
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
1079
889
struct device *dev = pci->dev;
1080
890
struct platform_device *pdev = to_platform_device(dev);
1081
891
struct device_node *np = dev->of_node;
1082
-
1083
-
INIT_LIST_HEAD(&ep->func_list);
892
+
struct pci_epc *epc = ep->epc;
893
+
struct resource *res;
894
+
int ret;
1084
895
1085
896
ret = dw_pcie_get_resources(pci);
1086
897
if (ret)
···
1082
915
ep->phys_base = res->start;
1083
916
ep->addr_size = resource_size(res);
1084
917
1085
-
if (ep->ops->pre_init)
1086
-
ep->ops->pre_init(ep);
918
+
/*
919
+
* artpec6_pcie_cpu_addr_fixup() uses ep->phys_base, so call
920
+
* dw_pcie_parent_bus_offset() after setting ep->phys_base.
921
+
*/
922
+
pci->parent_bus_offset = dw_pcie_parent_bus_offset(pci, "addr_space",
923
+
ep->phys_base);
924
+
925
+
ret = of_property_read_u8(np, "max-functions", &epc->max_functions);
926
+
if (ret < 0)
927
+
epc->max_functions = 1;
928
+
929
+
return 0;
930
+
}
931
+
932
+
/**
933
+
* dw_pcie_ep_init - Initialize the endpoint device
934
+
* @ep: DWC EP device
935
+
*
936
+
* Initialize the endpoint device. Allocate resources and create the EPC
937
+
* device with the endpoint framework.
938
+
*
939
+
* Return: 0 if success, errno otherwise.
940
+
*/
941
+
int dw_pcie_ep_init(struct dw_pcie_ep *ep)
942
+
{
943
+
int ret;
944
+
struct pci_epc *epc;
945
+
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
946
+
struct device *dev = pci->dev;
947
+
948
+
INIT_LIST_HEAD(&ep->func_list);
1087
949
1088
950
epc = devm_pci_epc_create(dev, &epc_ops);
1089
951
if (IS_ERR(epc)) {
···
1123
927
ep->epc = epc;
1124
928
epc_set_drvdata(epc, ep);
1125
929
1126
-
ret = of_property_read_u8(np, "max-functions", &epc->max_functions);
1127
-
if (ret < 0)
1128
-
epc->max_functions = 1;
930
+
ret = dw_pcie_ep_get_resources(ep);
931
+
if (ret)
932
+
return ret;
933
+
934
+
if (ep->ops->pre_init)
935
+
ep->ops->pre_init(ep);
1129
936
1130
937
ret = pci_epc_mem_init(epc, ep->phys_base, ep->addr_size,
1131
938
ep->page_size);
+42
-19
drivers/pci/controller/dwc/pcie-designware-host.c
+42
-19
drivers/pci/controller/dwc/pcie-designware-host.c
···
418
418
}
419
419
}
420
420
421
-
int dw_pcie_host_init(struct dw_pcie_rp *pp)
421
+
static int dw_pcie_host_get_resources(struct dw_pcie_rp *pp)
422
422
{
423
423
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
424
424
struct device *dev = pci->dev;
425
-
struct device_node *np = dev->of_node;
426
425
struct platform_device *pdev = to_platform_device(dev);
427
426
struct resource_entry *win;
428
-
struct pci_host_bridge *bridge;
429
427
struct resource *res;
430
428
int ret;
431
-
432
-
raw_spin_lock_init(&pp->lock);
433
429
434
430
ret = dw_pcie_get_resources(pci);
435
431
if (ret)
···
444
448
if (IS_ERR(pp->va_cfg0_base))
445
449
return PTR_ERR(pp->va_cfg0_base);
446
450
451
+
/* Get the I/O range from DT */
452
+
win = resource_list_first_type(&pp->bridge->windows, IORESOURCE_IO);
453
+
if (win) {
454
+
pp->io_size = resource_size(win->res);
455
+
pp->io_bus_addr = win->res->start - win->offset;
456
+
pp->io_base = pci_pio_to_address(win->res->start);
457
+
}
458
+
459
+
/*
460
+
* visconti_pcie_cpu_addr_fixup() uses pp->io_base, so we have to
461
+
* call dw_pcie_parent_bus_offset() after setting pp->io_base.
462
+
*/
463
+
pci->parent_bus_offset = dw_pcie_parent_bus_offset(pci, "config",
464
+
pp->cfg0_base);
465
+
return 0;
466
+
}
467
+
468
+
int dw_pcie_host_init(struct dw_pcie_rp *pp)
469
+
{
470
+
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
471
+
struct device *dev = pci->dev;
472
+
struct device_node *np = dev->of_node;
473
+
struct pci_host_bridge *bridge;
474
+
int ret;
475
+
476
+
raw_spin_lock_init(&pp->lock);
477
+
447
478
bridge = devm_pci_alloc_host_bridge(dev, 0);
448
479
if (!bridge)
449
480
return -ENOMEM;
450
481
451
482
pp->bridge = bridge;
452
483
453
-
/* Get the I/O range from DT */
454
-
win = resource_list_first_type(&bridge->windows, IORESOURCE_IO);
455
-
if (win) {
456
-
pp->io_size = resource_size(win->res);
457
-
pp->io_bus_addr = win->res->start - win->offset;
458
-
pp->io_base = pci_pio_to_address(win->res->start);
459
-
}
484
+
ret = dw_pcie_host_get_resources(pp);
485
+
if (ret)
486
+
return ret;
460
487
461
488
/* Set default bus ops */
462
489
bridge->ops = &dw_pcie_ops;
···
567
548
if (pp->ops->post_init)
568
549
pp->ops->post_init(pp);
569
550
551
+
dwc_pcie_debugfs_init(pci);
552
+
570
553
return 0;
571
554
572
555
err_stop_link:
···
592
571
void dw_pcie_host_deinit(struct dw_pcie_rp *pp)
593
572
{
594
573
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
574
+
575
+
dwc_pcie_debugfs_deinit(pci);
595
576
596
577
pci_stop_root_bus(pp->bridge->bus);
597
578
pci_remove_root_bus(pp->bridge->bus);
···
639
616
type = PCIE_ATU_TYPE_CFG1;
640
617
641
618
atu.type = type;
642
-
atu.cpu_addr = pp->cfg0_base;
619
+
atu.parent_bus_addr = pp->cfg0_base - pci->parent_bus_offset;
643
620
atu.pci_addr = busdev;
644
621
atu.size = pp->cfg0_size;
645
622
···
664
641
665
642
if (pp->cfg0_io_shared) {
666
643
atu.type = PCIE_ATU_TYPE_IO;
667
-
atu.cpu_addr = pp->io_base;
644
+
atu.parent_bus_addr = pp->io_base - pci->parent_bus_offset;
668
645
atu.pci_addr = pp->io_bus_addr;
669
646
atu.size = pp->io_size;
670
647
···
690
667
691
668
if (pp->cfg0_io_shared) {
692
669
atu.type = PCIE_ATU_TYPE_IO;
693
-
atu.cpu_addr = pp->io_base;
670
+
atu.parent_bus_addr = pp->io_base - pci->parent_bus_offset;
694
671
atu.pci_addr = pp->io_bus_addr;
695
672
atu.size = pp->io_size;
696
673
···
759
736
760
737
atu.index = i;
761
738
atu.type = PCIE_ATU_TYPE_MEM;
762
-
atu.cpu_addr = entry->res->start;
739
+
atu.parent_bus_addr = entry->res->start - pci->parent_bus_offset;
763
740
atu.pci_addr = entry->res->start - entry->offset;
764
741
765
742
/* Adjust iATU size if MSG TLP region was allocated before */
···
781
758
if (pci->num_ob_windows > ++i) {
782
759
atu.index = i;
783
760
atu.type = PCIE_ATU_TYPE_IO;
784
-
atu.cpu_addr = pp->io_base;
761
+
atu.parent_bus_addr = pp->io_base - pci->parent_bus_offset;
785
762
atu.pci_addr = pp->io_bus_addr;
786
763
atu.size = pp->io_size;
787
764
···
925
902
atu.size = resource_size(pci->pp.msg_res);
926
903
atu.index = pci->pp.msg_atu_index;
927
904
928
-
atu.cpu_addr = pci->pp.msg_res->start;
905
+
atu.parent_bus_addr = pci->pp.msg_res->start - pci->parent_bus_offset;
929
906
930
907
ret = dw_pcie_prog_outbound_atu(pci, &atu);
931
908
if (ret)
932
909
return ret;
933
910
934
-
mem = ioremap(atu.cpu_addr, pci->region_align);
911
+
mem = ioremap(pci->pp.msg_res->start, pci->region_align);
935
912
if (!mem)
936
913
return -ENOMEM;
937
914
+123
-19
drivers/pci/controller/dwc/pcie-designware.c
+123
-19
drivers/pci/controller/dwc/pcie-designware.c
···
16
16
#include <linux/gpio/consumer.h>
17
17
#include <linux/ioport.h>
18
18
#include <linux/of.h>
19
+
#include <linux/of_address.h>
20
+
#include <linux/pcie-dwc.h>
19
21
#include <linux/platform_device.h>
20
22
#include <linux/sizes.h>
21
23
#include <linux/types.h>
···
285
283
}
286
284
EXPORT_SYMBOL_GPL(dw_pcie_find_ext_capability);
287
285
286
+
static u16 __dw_pcie_find_vsec_capability(struct dw_pcie *pci, u16 vendor_id,
287
+
u16 vsec_id)
288
+
{
289
+
u16 vsec = 0;
290
+
u32 header;
291
+
292
+
if (vendor_id != dw_pcie_readw_dbi(pci, PCI_VENDOR_ID))
293
+
return 0;
294
+
295
+
while ((vsec = dw_pcie_find_next_ext_capability(pci, vsec,
296
+
PCI_EXT_CAP_ID_VNDR))) {
297
+
header = dw_pcie_readl_dbi(pci, vsec + PCI_VNDR_HEADER);
298
+
if (PCI_VNDR_HEADER_ID(header) == vsec_id)
299
+
return vsec;
300
+
}
301
+
302
+
return 0;
303
+
}
304
+
305
+
static u16 dw_pcie_find_vsec_capability(struct dw_pcie *pci,
306
+
const struct dwc_pcie_vsec_id *vsec_ids)
307
+
{
308
+
const struct dwc_pcie_vsec_id *vid;
309
+
u16 vsec;
310
+
u32 header;
311
+
312
+
for (vid = vsec_ids; vid->vendor_id; vid++) {
313
+
vsec = __dw_pcie_find_vsec_capability(pci, vid->vendor_id,
314
+
vid->vsec_id);
315
+
if (vsec) {
316
+
header = dw_pcie_readl_dbi(pci, vsec + PCI_VNDR_HEADER);
317
+
if (PCI_VNDR_HEADER_REV(header) == vid->vsec_rev)
318
+
return vsec;
319
+
}
320
+
}
321
+
322
+
return 0;
323
+
}
324
+
325
+
u16 dw_pcie_find_rasdes_capability(struct dw_pcie *pci)
326
+
{
327
+
return dw_pcie_find_vsec_capability(pci, dwc_pcie_rasdes_vsec_ids);
328
+
}
329
+
EXPORT_SYMBOL_GPL(dw_pcie_find_rasdes_capability);
330
+
288
331
int dw_pcie_read(void __iomem *addr, int size, u32 *val)
289
332
{
290
333
if (!IS_ALIGNED((uintptr_t)addr, size)) {
···
517
470
int dw_pcie_prog_outbound_atu(struct dw_pcie *pci,
518
471
const struct dw_pcie_ob_atu_cfg *atu)
519
472
{
520
-
u64 cpu_addr = atu->cpu_addr;
473
+
u64 parent_bus_addr = atu->parent_bus_addr;
521
474
u32 retries, val;
522
475
u64 limit_addr;
523
476
524
-
if (pci->ops && pci->ops->cpu_addr_fixup)
525
-
cpu_addr = pci->ops->cpu_addr_fixup(pci, cpu_addr);
477
+
limit_addr = parent_bus_addr + atu->size - 1;
526
478
527
-
limit_addr = cpu_addr + atu->size - 1;
528
-
529
-
if ((limit_addr & ~pci->region_limit) != (cpu_addr & ~pci->region_limit) ||
530
-
!IS_ALIGNED(cpu_addr, pci->region_align) ||
479
+
if ((limit_addr & ~pci->region_limit) != (parent_bus_addr & ~pci->region_limit) ||
480
+
!IS_ALIGNED(parent_bus_addr, pci->region_align) ||
531
481
!IS_ALIGNED(atu->pci_addr, pci->region_align) || !atu->size) {
532
482
return -EINVAL;
533
483
}
534
484
535
485
dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_LOWER_BASE,
536
-
lower_32_bits(cpu_addr));
486
+
lower_32_bits(parent_bus_addr));
537
487
dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_UPPER_BASE,
538
-
upper_32_bits(cpu_addr));
488
+
upper_32_bits(parent_bus_addr));
539
489
540
490
dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_LIMIT,
541
491
lower_32_bits(limit_addr));
···
546
502
upper_32_bits(atu->pci_addr));
547
503
548
504
val = atu->type | atu->routing | PCIE_ATU_FUNC_NUM(atu->func_no);
549
-
if (upper_32_bits(limit_addr) > upper_32_bits(cpu_addr) &&
505
+
if (upper_32_bits(limit_addr) > upper_32_bits(parent_bus_addr) &&
550
506
dw_pcie_ver_is_ge(pci, 460A))
551
507
val |= PCIE_ATU_INCREASE_REGION_SIZE;
552
508
if (dw_pcie_ver_is(pci, 490A))
···
589
545
}
590
546
591
547
int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, int index, int type,
592
-
u64 cpu_addr, u64 pci_addr, u64 size)
548
+
u64 parent_bus_addr, u64 pci_addr, u64 size)
593
549
{
594
550
u64 limit_addr = pci_addr + size - 1;
595
551
u32 retries, val;
596
552
597
553
if ((limit_addr & ~pci->region_limit) != (pci_addr & ~pci->region_limit) ||
598
-
!IS_ALIGNED(cpu_addr, pci->region_align) ||
554
+
!IS_ALIGNED(parent_bus_addr, pci->region_align) ||
599
555
!IS_ALIGNED(pci_addr, pci->region_align) || !size) {
600
556
return -EINVAL;
601
557
}
···
612
568
upper_32_bits(limit_addr));
613
569
614
570
dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_LOWER_TARGET,
615
-
lower_32_bits(cpu_addr));
571
+
lower_32_bits(parent_bus_addr));
616
572
dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_UPPER_TARGET,
617
-
upper_32_bits(cpu_addr));
573
+
upper_32_bits(parent_bus_addr));
618
574
619
575
val = type;
620
576
if (upper_32_bits(limit_addr) > upper_32_bits(pci_addr) &&
···
641
597
}
642
598
643
599
int dw_pcie_prog_ep_inbound_atu(struct dw_pcie *pci, u8 func_no, int index,
644
-
int type, u64 cpu_addr, u8 bar, size_t size)
600
+
int type, u64 parent_bus_addr, u8 bar, size_t size)
645
601
{
646
602
u32 retries, val;
647
603
648
-
if (!IS_ALIGNED(cpu_addr, pci->region_align) ||
649
-
!IS_ALIGNED(cpu_addr, size))
604
+
if (!IS_ALIGNED(parent_bus_addr, pci->region_align) ||
605
+
!IS_ALIGNED(parent_bus_addr, size))
650
606
return -EINVAL;
651
607
652
608
dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_LOWER_TARGET,
653
-
lower_32_bits(cpu_addr));
609
+
lower_32_bits(parent_bus_addr));
654
610
dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_UPPER_TARGET,
655
-
upper_32_bits(cpu_addr));
611
+
upper_32_bits(parent_bus_addr));
656
612
657
613
dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_REGION_CTRL1, type |
658
614
PCIE_ATU_FUNC_NUM(func_no));
···
1148
1104
dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val);
1149
1105
1150
1106
dw_pcie_link_set_max_link_width(pci, pci->num_lanes);
1107
+
}
1108
+
1109
+
resource_size_t dw_pcie_parent_bus_offset(struct dw_pcie *pci,
1110
+
const char *reg_name,
1111
+
resource_size_t cpu_phys_addr)
1112
+
{
1113
+
struct device *dev = pci->dev;
1114
+
struct device_node *np = dev->of_node;
1115
+
int index;
1116
+
u64 reg_addr, fixup_addr;
1117
+
u64 (*fixup)(struct dw_pcie *pcie, u64 cpu_addr);
1118
+
1119
+
/* Look up reg_name address on parent bus */
1120
+
index = of_property_match_string(np, "reg-names", reg_name);
1121
+
1122
+
if (index < 0) {
1123
+
dev_err(dev, "No %s in devicetree \"reg\" property\n", reg_name);
1124
+
return 0;
1125
+
}
1126
+
1127
+
of_property_read_reg(np, index, ®_addr, NULL);
1128
+
1129
+
fixup = pci->ops ? pci->ops->cpu_addr_fixup : NULL;
1130
+
if (fixup) {
1131
+
fixup_addr = fixup(pci, cpu_phys_addr);
1132
+
if (reg_addr == fixup_addr) {
1133
+
dev_info(dev, "%s reg[%d] %#010llx == %#010llx == fixup(cpu %#010llx); %ps is redundant with this devicetree\n",
1134
+
reg_name, index, reg_addr, fixup_addr,
1135
+
(unsigned long long) cpu_phys_addr, fixup);
1136
+
} else {
1137
+
dev_warn(dev, "%s reg[%d] %#010llx != %#010llx == fixup(cpu %#010llx); devicetree is broken\n",
1138
+
reg_name, index, reg_addr, fixup_addr,
1139
+
(unsigned long long) cpu_phys_addr);
1140
+
reg_addr = fixup_addr;
1141
+
}
1142
+
1143
+
return cpu_phys_addr - reg_addr;
1144
+
}
1145
+
1146
+
if (pci->use_parent_dt_ranges) {
1147
+
1148
+
/*
1149
+
* This platform once had a fixup, presumably because it
1150
+
* translates between CPU and PCI controller addresses.
1151
+
* Log a note if devicetree didn't describe a translation.
1152
+
*/
1153
+
if (reg_addr == cpu_phys_addr)
1154
+
dev_info(dev, "%s reg[%d] %#010llx == cpu %#010llx\n; no fixup was ever needed for this devicetree\n",
1155
+
reg_name, index, reg_addr,
1156
+
(unsigned long long) cpu_phys_addr);
1157
+
} else {
1158
+
if (reg_addr != cpu_phys_addr) {
1159
+
dev_warn(dev, "%s reg[%d] %#010llx != cpu %#010llx; no fixup and devicetree \"ranges\" is broken, assuming no translation\n",
1160
+
reg_name, index, reg_addr,
1161
+
(unsigned long long) cpu_phys_addr);
1162
+
return 0;
1163
+
}
1164
+
}
1165
+
1166
+
return cpu_phys_addr - reg_addr;
1151
1167
}
+79
-3
drivers/pci/controller/dwc/pcie-designware.h
+79
-3
drivers/pci/controller/dwc/pcie-designware.h
···
330
330
/* Need to align with PCIE_PORT_DEBUG0 bits 0:5 */
331
331
DW_PCIE_LTSSM_DETECT_QUIET = 0x0,
332
332
DW_PCIE_LTSSM_DETECT_ACT = 0x1,
333
+
DW_PCIE_LTSSM_POLL_ACTIVE = 0x2,
334
+
DW_PCIE_LTSSM_POLL_COMPLIANCE = 0x3,
335
+
DW_PCIE_LTSSM_POLL_CONFIG = 0x4,
336
+
DW_PCIE_LTSSM_PRE_DETECT_QUIET = 0x5,
333
337
DW_PCIE_LTSSM_DETECT_WAIT = 0x6,
338
+
DW_PCIE_LTSSM_CFG_LINKWD_START = 0x7,
339
+
DW_PCIE_LTSSM_CFG_LINKWD_ACEPT = 0x8,
340
+
DW_PCIE_LTSSM_CFG_LANENUM_WAI = 0x9,
341
+
DW_PCIE_LTSSM_CFG_LANENUM_ACEPT = 0xa,
342
+
DW_PCIE_LTSSM_CFG_COMPLETE = 0xb,
343
+
DW_PCIE_LTSSM_CFG_IDLE = 0xc,
344
+
DW_PCIE_LTSSM_RCVRY_LOCK = 0xd,
345
+
DW_PCIE_LTSSM_RCVRY_SPEED = 0xe,
346
+
DW_PCIE_LTSSM_RCVRY_RCVRCFG = 0xf,
347
+
DW_PCIE_LTSSM_RCVRY_IDLE = 0x10,
334
348
DW_PCIE_LTSSM_L0 = 0x11,
349
+
DW_PCIE_LTSSM_L0S = 0x12,
350
+
DW_PCIE_LTSSM_L123_SEND_EIDLE = 0x13,
351
+
DW_PCIE_LTSSM_L1_IDLE = 0x14,
335
352
DW_PCIE_LTSSM_L2_IDLE = 0x15,
353
+
DW_PCIE_LTSSM_L2_WAKE = 0x16,
354
+
DW_PCIE_LTSSM_DISABLED_ENTRY = 0x17,
355
+
DW_PCIE_LTSSM_DISABLED_IDLE = 0x18,
356
+
DW_PCIE_LTSSM_DISABLED = 0x19,
357
+
DW_PCIE_LTSSM_LPBK_ENTRY = 0x1a,
358
+
DW_PCIE_LTSSM_LPBK_ACTIVE = 0x1b,
359
+
DW_PCIE_LTSSM_LPBK_EXIT = 0x1c,
360
+
DW_PCIE_LTSSM_LPBK_EXIT_TIMEOUT = 0x1d,
361
+
DW_PCIE_LTSSM_HOT_RESET_ENTRY = 0x1e,
362
+
DW_PCIE_LTSSM_HOT_RESET = 0x1f,
363
+
DW_PCIE_LTSSM_RCVRY_EQ0 = 0x20,
364
+
DW_PCIE_LTSSM_RCVRY_EQ1 = 0x21,
365
+
DW_PCIE_LTSSM_RCVRY_EQ2 = 0x22,
366
+
DW_PCIE_LTSSM_RCVRY_EQ3 = 0x23,
336
367
337
368
DW_PCIE_LTSSM_UNKNOWN = 0xFFFFFFFF,
338
369
};
···
374
343
u8 func_no;
375
344
u8 code;
376
345
u8 routing;
377
-
u64 cpu_addr;
346
+
u64 parent_bus_addr;
378
347
u64 pci_addr;
379
348
u64 size;
380
349
};
···
468
437
void (*stop_link)(struct dw_pcie *pcie);
469
438
};
470
439
440
+
struct debugfs_info {
441
+
struct dentry *debug_dir;
442
+
void *rasdes_info;
443
+
};
444
+
471
445
struct dw_pcie {
472
446
struct device *dev;
473
447
void __iomem *dbi_base;
···
481
445
void __iomem *atu_base;
482
446
resource_size_t atu_phys_addr;
483
447
size_t atu_size;
448
+
resource_size_t parent_bus_offset;
484
449
u32 num_ib_windows;
485
450
u32 num_ob_windows;
486
451
u32 region_align;
···
502
465
struct reset_control_bulk_data core_rsts[DW_PCIE_NUM_CORE_RSTS];
503
466
struct gpio_desc *pe_rst;
504
467
bool suspended;
468
+
struct debugfs_info *debugfs;
469
+
470
+
/*
471
+
* If iATU input addresses are offset from CPU physical addresses,
472
+
* we previously required .cpu_addr_fixup() to convert them. We
473
+
* now rely on the devicetree instead. If .cpu_addr_fixup()
474
+
* exists, we compare its results with devicetree.
475
+
*
476
+
* If .cpu_addr_fixup() does not exist, we assume the offset is
477
+
* zero and warn if devicetree claims otherwise. If we know all
478
+
* devicetrees correctly describe the offset, set
479
+
* use_parent_dt_ranges to true to avoid this warning.
480
+
*/
481
+
bool use_parent_dt_ranges;
505
482
};
506
483
507
484
#define to_dw_pcie_from_pp(port) container_of((port), struct dw_pcie, pp)
···
529
478
530
479
u8 dw_pcie_find_capability(struct dw_pcie *pci, u8 cap);
531
480
u16 dw_pcie_find_ext_capability(struct dw_pcie *pci, u8 cap);
481
+
u16 dw_pcie_find_rasdes_capability(struct dw_pcie *pci);
532
482
533
483
int dw_pcie_read(void __iomem *addr, int size, u32 *val);
534
484
int dw_pcie_write(void __iomem *addr, int size, u32 val);
···
543
491
int dw_pcie_prog_outbound_atu(struct dw_pcie *pci,
544
492
const struct dw_pcie_ob_atu_cfg *atu);
545
493
int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, int index, int type,
546
-
u64 cpu_addr, u64 pci_addr, u64 size);
494
+
u64 parent_bus_addr, u64 pci_addr, u64 size);
547
495
int dw_pcie_prog_ep_inbound_atu(struct dw_pcie *pci, u8 func_no, int index,
548
-
int type, u64 cpu_addr, u8 bar, size_t size);
496
+
int type, u64 parent_bus_addr,
497
+
u8 bar, size_t size);
549
498
void dw_pcie_disable_atu(struct dw_pcie *pci, u32 dir, int index);
550
499
void dw_pcie_setup(struct dw_pcie *pci);
551
500
void dw_pcie_iatu_detect(struct dw_pcie *pci);
552
501
int dw_pcie_edma_detect(struct dw_pcie *pci);
553
502
void dw_pcie_edma_remove(struct dw_pcie *pci);
503
+
resource_size_t dw_pcie_parent_bus_offset(struct dw_pcie *pci,
504
+
const char *reg_name,
505
+
resource_size_t cpu_phy_addr);
554
506
555
507
static inline void dw_pcie_writel_dbi(struct dw_pcie *pci, u32 reg, u32 val)
556
508
{
···
799
743
int dw_pcie_ep_raise_msix_irq_doorbell(struct dw_pcie_ep *ep, u8 func_no,
800
744
u16 interrupt_num);
801
745
void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar);
746
+
int dw_pcie_ep_hide_ext_capability(struct dw_pcie *pci, u8 prev_cap, u8 cap);
802
747
struct dw_pcie_ep_func *
803
748
dw_pcie_ep_get_func_from_ep(struct dw_pcie_ep *ep, u8 func_no);
804
749
#else
···
857
800
{
858
801
}
859
802
803
+
static inline int dw_pcie_ep_hide_ext_capability(struct dw_pcie *pci,
804
+
u8 prev_cap, u8 cap)
805
+
{
806
+
return 0;
807
+
}
808
+
860
809
static inline struct dw_pcie_ep_func *
861
810
dw_pcie_ep_get_func_from_ep(struct dw_pcie_ep *ep, u8 func_no)
862
811
{
863
812
return NULL;
864
813
}
865
814
#endif
815
+
816
+
#ifdef CONFIG_PCIE_DW_DEBUGFS
817
+
void dwc_pcie_debugfs_init(struct dw_pcie *pci);
818
+
void dwc_pcie_debugfs_deinit(struct dw_pcie *pci);
819
+
#else
820
+
static inline void dwc_pcie_debugfs_init(struct dw_pcie *pci)
821
+
{
822
+
}
823
+
static inline void dwc_pcie_debugfs_deinit(struct dw_pcie *pci)
824
+
{
825
+
}
826
+
#endif
827
+
866
828
#endif /* _PCIE_DESIGNWARE_H */
+42
-11
drivers/pci/controller/dwc/pcie-dw-rockchip.c
+42
-11
drivers/pci/controller/dwc/pcie-dw-rockchip.c
···
240
240
.init = rockchip_pcie_host_init,
241
241
};
242
242
243
+
/*
244
+
* ATS does not work on RK3588 when running in EP mode.
245
+
*
246
+
* After the host has enabled ATS on the EP side, it will send an IOTLB
247
+
* invalidation request to the EP side. However, the RK3588 will never send
248
+
* a completion back and eventually the host will print an IOTLB_INV_TIMEOUT
249
+
* error, and the EP will not be operational. If we hide the ATS capability,
250
+
* things work as expected.
251
+
*/
252
+
static void rockchip_pcie_ep_hide_broken_ats_cap_rk3588(struct dw_pcie_ep *ep)
253
+
{
254
+
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
255
+
struct device *dev = pci->dev;
256
+
257
+
/* Only hide the ATS capability for RK3588 running in EP mode. */
258
+
if (!of_device_is_compatible(dev->of_node, "rockchip,rk3588-pcie-ep"))
259
+
return;
260
+
261
+
if (dw_pcie_ep_hide_ext_capability(pci, PCI_EXT_CAP_ID_SECPCI,
262
+
PCI_EXT_CAP_ID_ATS))
263
+
dev_err(dev, "failed to hide ATS capability\n");
264
+
}
265
+
266
+
static void rockchip_pcie_ep_pre_init(struct dw_pcie_ep *ep)
267
+
{
268
+
rockchip_pcie_ep_hide_broken_ats_cap_rk3588(ep);
269
+
}
270
+
243
271
static void rockchip_pcie_ep_init(struct dw_pcie_ep *ep)
244
272
{
245
273
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
···
300
272
.linkup_notifier = true,
301
273
.msi_capable = true,
302
274
.msix_capable = true,
275
+
.intx_capable = false,
303
276
.align = SZ_64K,
304
-
.bar[BAR_0] = { .type = BAR_FIXED, .fixed_size = SZ_1M, },
305
-
.bar[BAR_1] = { .type = BAR_FIXED, .fixed_size = SZ_1M, },
306
-
.bar[BAR_2] = { .type = BAR_FIXED, .fixed_size = SZ_1M, },
307
-
.bar[BAR_3] = { .type = BAR_FIXED, .fixed_size = SZ_1M, },
308
-
.bar[BAR_4] = { .type = BAR_FIXED, .fixed_size = SZ_1M, },
309
-
.bar[BAR_5] = { .type = BAR_FIXED, .fixed_size = SZ_1M, },
277
+
.bar[BAR_0] = { .type = BAR_RESIZABLE, },
278
+
.bar[BAR_1] = { .type = BAR_RESIZABLE, },
279
+
.bar[BAR_2] = { .type = BAR_RESIZABLE, },
280
+
.bar[BAR_3] = { .type = BAR_RESIZABLE, },
281
+
.bar[BAR_4] = { .type = BAR_RESIZABLE, },
282
+
.bar[BAR_5] = { .type = BAR_RESIZABLE, },
310
283
};
311
284
312
285
/*
···
321
292
.linkup_notifier = true,
322
293
.msi_capable = true,
323
294
.msix_capable = true,
295
+
.intx_capable = false,
324
296
.align = SZ_64K,
325
-
.bar[BAR_0] = { .type = BAR_FIXED, .fixed_size = SZ_1M, },
326
-
.bar[BAR_1] = { .type = BAR_FIXED, .fixed_size = SZ_1M, },
327
-
.bar[BAR_2] = { .type = BAR_FIXED, .fixed_size = SZ_1M, },
328
-
.bar[BAR_3] = { .type = BAR_FIXED, .fixed_size = SZ_1M, },
297
+
.bar[BAR_0] = { .type = BAR_RESIZABLE, },
298
+
.bar[BAR_1] = { .type = BAR_RESIZABLE, },
299
+
.bar[BAR_2] = { .type = BAR_RESIZABLE, },
300
+
.bar[BAR_3] = { .type = BAR_RESIZABLE, },
329
301
.bar[BAR_4] = { .type = BAR_RESERVED, },
330
-
.bar[BAR_5] = { .type = BAR_FIXED, .fixed_size = SZ_1M, },
302
+
.bar[BAR_5] = { .type = BAR_RESIZABLE, },
331
303
};
332
304
333
305
static const struct pci_epc_features *
···
342
312
343
313
static const struct dw_pcie_ep_ops rockchip_pcie_ep_ops = {
344
314
.init = rockchip_pcie_ep_init,
315
+
.pre_init = rockchip_pcie_ep_pre_init,
345
316
.raise_irq = rockchip_pcie_raise_irq,
346
317
.get_features = rockchip_pcie_get_features,
347
318
};
+8
-4
drivers/pci/controller/dwc/pcie-histb.c
+8
-4
drivers/pci/controller/dwc/pcie-histb.c
···
409
409
ret = histb_pcie_host_enable(pp);
410
410
if (ret) {
411
411
dev_err(dev, "failed to enable host\n");
412
-
return ret;
412
+
goto err_exit_phy;
413
413
}
414
414
415
415
ret = dw_pcie_host_init(pp);
416
416
if (ret) {
417
417
dev_err(dev, "failed to initialize host\n");
418
-
return ret;
418
+
goto err_exit_phy;
419
419
}
420
420
421
421
return 0;
422
+
423
+
err_exit_phy:
424
+
phy_exit(hipcie->phy);
425
+
426
+
return ret;
422
427
}
423
428
424
429
static void histb_pcie_remove(struct platform_device *pdev)
···
432
427
433
428
histb_pcie_host_disable(hipcie);
434
429
435
-
if (hipcie->phy)
436
-
phy_exit(hipcie->phy);
430
+
phy_exit(hipcie->phy);
437
431
}
438
432
439
433
static const struct of_device_id histb_pcie_of_match[] = {
+1
-7
drivers/pci/controller/dwc/pcie-intel-gw.c
+1
-7
drivers/pci/controller/dwc/pcie-intel-gw.c
···
57
57
PCIE_APP_IRN_INTA | PCIE_APP_IRN_INTB | \
58
58
PCIE_APP_IRN_INTC | PCIE_APP_IRN_INTD)
59
59
60
-
#define BUS_IATU_OFFSET SZ_256M
61
60
#define RESET_INTERVAL_MS 100
62
61
63
62
struct intel_pcie {
···
380
381
return intel_pcie_host_setup(pcie);
381
382
}
382
383
383
-
static u64 intel_pcie_cpu_addr(struct dw_pcie *pcie, u64 cpu_addr)
384
-
{
385
-
return cpu_addr + BUS_IATU_OFFSET;
386
-
}
387
-
388
384
static const struct dw_pcie_ops intel_pcie_ops = {
389
-
.cpu_addr_fixup = intel_pcie_cpu_addr,
390
385
};
391
386
392
387
static const struct dw_pcie_host_ops intel_pcie_dw_ops = {
···
402
409
platform_set_drvdata(pdev, pcie);
403
410
pci = &pcie->pci;
404
411
pci->dev = dev;
412
+
pci->use_parent_dt_ranges = true;
405
413
pp = &pci->pp;
406
414
407
415
ret = intel_pcie_get_resources(pdev);
+18
-32
drivers/pci/controller/dwc/pcie-kirin.c
+18
-32
drivers/pci/controller/dwc/pcie-kirin.c
···
216
216
217
217
usleep_range(PIPE_CLK_WAIT_MIN, PIPE_CLK_WAIT_MAX);
218
218
reg_val = kirin_apb_phy_readl(phy, PCIE_APB_PHY_STATUS0);
219
-
if (reg_val & PIPE_CLK_STABLE) {
220
-
dev_err(dev, "PIPE clk is not stable\n");
221
-
return -EINVAL;
222
-
}
219
+
if (reg_val & PIPE_CLK_STABLE)
220
+
return dev_err_probe(dev, -ETIMEDOUT,
221
+
"PIPE clk is not stable\n");
223
222
224
223
return 0;
225
224
}
···
370
371
if (ret < 0)
371
372
return 0;
372
373
373
-
if (ret > MAX_PCI_SLOTS) {
374
-
dev_err(dev, "Too many GPIO clock requests!\n");
375
-
return -EINVAL;
376
-
}
374
+
if (ret > MAX_PCI_SLOTS)
375
+
return dev_err_probe(dev, -EINVAL,
376
+
"Too many GPIO clock requests!\n");
377
377
378
378
pcie->n_gpio_clkreq = ret;
379
379
···
418
420
"unable to get a valid reset gpio\n");
419
421
}
420
422
421
-
if (pcie->num_slots + 1 >= MAX_PCI_SLOTS) {
422
-
dev_err(dev, "Too many PCI slots!\n");
423
-
return -EINVAL;
424
-
}
423
+
if (pcie->num_slots + 1 >= MAX_PCI_SLOTS)
424
+
return dev_err_probe(dev, -EINVAL,
425
+
"Too many PCI slots!\n");
426
+
425
427
pcie->num_slots++;
426
428
427
429
ret = of_pci_get_devfn(child);
428
-
if (ret < 0) {
429
-
dev_err(dev, "failed to parse devfn: %d\n", ret);
430
-
return ret;
431
-
}
430
+
if (ret < 0)
431
+
return dev_err_probe(dev, ret,
432
+
"failed to parse devfn\n");
432
433
433
434
slot = PCI_SLOT(ret);
434
435
···
449
452
struct platform_device *pdev)
450
453
{
451
454
struct device *dev = &pdev->dev;
452
-
struct device_node *child, *node = dev->of_node;
455
+
struct device_node *node = dev->of_node;
453
456
void __iomem *apb_base;
454
457
int ret;
455
458
···
474
477
return ret;
475
478
476
479
/* Parse OF children */
477
-
for_each_available_child_of_node(node, child) {
480
+
for_each_available_child_of_node_scoped(node, child) {
478
481
ret = kirin_pcie_parse_port(kirin_pcie, pdev, child);
479
482
if (ret)
480
-
goto put_node;
483
+
return ret;
481
484
}
482
485
483
486
return 0;
484
-
485
-
put_node:
486
-
of_node_put(child);
487
-
return ret;
488
487
}
489
488
490
489
static void kirin_pcie_sideband_dbi_w_mode(struct kirin_pcie *kirin_pcie,
···
722
729
struct dw_pcie *pci;
723
730
int ret;
724
731
725
-
if (!dev->of_node) {
726
-
dev_err(dev, "NULL node\n");
727
-
return -EINVAL;
728
-
}
729
-
730
732
data = of_device_get_match_data(dev);
731
-
if (!data) {
732
-
dev_err(dev, "OF data missing\n");
733
-
return -EINVAL;
734
-
}
733
+
if (!data)
734
+
return dev_err_probe(dev, -EINVAL, "OF data missing\n");
735
735
736
736
kirin_pcie = devm_kzalloc(dev, sizeof(struct kirin_pcie), GFP_KERNEL);
737
737
if (!kirin_pcie)
+11
-6
drivers/pci/controller/dwc/pcie-qcom-ep.c
+11
-6
drivers/pci/controller/dwc/pcie-qcom-ep.c
···
48
48
#define PARF_DBI_BASE_ADDR_HI 0x354
49
49
#define PARF_SLV_ADDR_SPACE_SIZE 0x358
50
50
#define PARF_SLV_ADDR_SPACE_SIZE_HI 0x35c
51
-
#define PARF_NO_SNOOP_OVERIDE 0x3d4
51
+
#define PARF_NO_SNOOP_OVERRIDE 0x3d4
52
52
#define PARF_ATU_BASE_ADDR 0x634
53
53
#define PARF_ATU_BASE_ADDR_HI 0x638
54
54
#define PARF_SRIS_MODE 0x644
···
89
89
#define PARF_DEBUG_INT_CFG_BUS_MASTER_EN BIT(2)
90
90
#define PARF_DEBUG_INT_RADM_PM_TURNOFF BIT(3)
91
91
92
-
/* PARF_NO_SNOOP_OVERIDE register fields */
93
-
#define WR_NO_SNOOP_OVERIDE_EN BIT(1)
94
-
#define RD_NO_SNOOP_OVERIDE_EN BIT(3)
92
+
/* PARF_NO_SNOOP_OVERRIDE register fields */
93
+
#define WR_NO_SNOOP_OVERRIDE_EN BIT(1)
94
+
#define RD_NO_SNOOP_OVERRIDE_EN BIT(3)
95
95
96
96
/* PARF_DEVICE_TYPE register fields */
97
97
#define PARF_DEVICE_TYPE_EP 0x0
···
529
529
writel_relaxed(val, pcie_ep->parf + PARF_LTSSM);
530
530
531
531
if (pcie_ep->cfg && pcie_ep->cfg->override_no_snoop)
532
-
writel_relaxed(WR_NO_SNOOP_OVERIDE_EN | RD_NO_SNOOP_OVERIDE_EN,
533
-
pcie_ep->parf + PARF_NO_SNOOP_OVERIDE);
532
+
writel_relaxed(WR_NO_SNOOP_OVERRIDE_EN | RD_NO_SNOOP_OVERRIDE_EN,
533
+
pcie_ep->parf + PARF_NO_SNOOP_OVERRIDE);
534
534
535
535
return 0;
536
536
···
825
825
.msi_capable = true,
826
826
.msix_capable = false,
827
827
.align = SZ_4K,
828
+
.bar[BAR_0] = { .only_64bit = true, },
829
+
.bar[BAR_1] = { .type = BAR_RESERVED, },
830
+
.bar[BAR_2] = { .only_64bit = true, },
831
+
.bar[BAR_3] = { .type = BAR_RESERVED, },
828
832
};
829
833
830
834
static const struct pci_epc_features *
···
937
933
{ .compatible = "qcom,sa8775p-pcie-ep", .data = &cfg_1_34_0},
938
934
{ .compatible = "qcom,sdx55-pcie-ep", },
939
935
{ .compatible = "qcom,sm8450-pcie-ep", },
936
+
{ .compatible = "qcom,sar2130p-pcie-ep", },
940
937
{ }
941
938
};
942
939
MODULE_DEVICE_TABLE(of, qcom_pcie_ep_match);
+6
-6
drivers/pci/controller/dwc/pcie-qcom.c
+6
-6
drivers/pci/controller/dwc/pcie-qcom.c
···
61
61
#define PARF_DBI_BASE_ADDR_V2_HI 0x354
62
62
#define PARF_SLV_ADDR_SPACE_SIZE_V2 0x358
63
63
#define PARF_SLV_ADDR_SPACE_SIZE_V2_HI 0x35c
64
-
#define PARF_NO_SNOOP_OVERIDE 0x3d4
64
+
#define PARF_NO_SNOOP_OVERRIDE 0x3d4
65
65
#define PARF_ATU_BASE_ADDR 0x634
66
66
#define PARF_ATU_BASE_ADDR_HI 0x638
67
67
#define PARF_DEVICE_TYPE 0x1000
···
135
135
#define PARF_INT_ALL_LINK_UP BIT(13)
136
136
#define PARF_INT_MSI_DEV_0_7 GENMASK(30, 23)
137
137
138
-
/* PARF_NO_SNOOP_OVERIDE register fields */
139
-
#define WR_NO_SNOOP_OVERIDE_EN BIT(1)
140
-
#define RD_NO_SNOOP_OVERIDE_EN BIT(3)
138
+
/* PARF_NO_SNOOP_OVERRIDE register fields */
139
+
#define WR_NO_SNOOP_OVERRIDE_EN BIT(1)
140
+
#define RD_NO_SNOOP_OVERRIDE_EN BIT(3)
141
141
142
142
/* PARF_DEVICE_TYPE register fields */
143
143
#define DEVICE_TYPE_RC 0x4
···
1007
1007
const struct qcom_pcie_cfg *pcie_cfg = pcie->cfg;
1008
1008
1009
1009
if (pcie_cfg->override_no_snoop)
1010
-
writel(WR_NO_SNOOP_OVERIDE_EN | RD_NO_SNOOP_OVERIDE_EN,
1011
-
pcie->parf + PARF_NO_SNOOP_OVERIDE);
1010
+
writel(WR_NO_SNOOP_OVERRIDE_EN | RD_NO_SNOOP_OVERRIDE_EN,
1011
+
pcie->parf + PARF_NO_SNOOP_OVERRIDE);
1012
1012
1013
1013
qcom_pcie_clear_aspm_l0s(pcie->pci);
1014
1014
qcom_pcie_clear_hpc(pcie->pci);
+1
-1
drivers/pci/controller/pci-hyperv.c
+1
-1
drivers/pci/controller/pci-hyperv.c
···
1356
1356
*
1357
1357
* If the PF driver wishes to initiate communication, it can "invalidate" one or
1358
1358
* more of the first 64 blocks. This invalidation is delivered via a callback
1359
-
* supplied by the VF driver by this driver.
1359
+
* supplied to the VF driver by this driver.
1360
1360
*
1361
1361
* No protocol is implied, except that supplied by the PF and VF drivers.
1362
1362
*/
+1
-1
drivers/pci/controller/pci-mvebu.c
+1
-1
drivers/pci/controller/pci-mvebu.c
···
1422
1422
}
1423
1423
1424
1424
/*
1425
-
* devm_of_pci_get_host_bridge_resources() only sets up translateable resources,
1425
+
* devm_of_pci_get_host_bridge_resources() only sets up translatable resources,
1426
1426
* so we need extra resource setup parsing our special DT properties encoding
1427
1427
* the MEM and IO apertures.
1428
1428
*/
+28
-52
drivers/pci/controller/pci-tegra.c
+28
-52
drivers/pci/controller/pci-tegra.c
···
2106
2106
static int tegra_pcie_parse_dt(struct tegra_pcie *pcie)
2107
2107
{
2108
2108
struct device *dev = pcie->dev;
2109
-
struct device_node *np = dev->of_node, *port;
2109
+
struct device_node *np = dev->of_node;
2110
2110
const struct tegra_pcie_soc *soc = pcie->soc;
2111
2111
u32 lanes = 0, mask = 0;
2112
2112
unsigned int lane = 0;
2113
2113
int err;
2114
2114
2115
2115
/* parse root ports */
2116
-
for_each_child_of_node(np, port) {
2116
+
for_each_child_of_node_scoped(np, port) {
2117
2117
struct tegra_pcie_port *rp;
2118
2118
unsigned int index;
2119
2119
u32 value;
2120
2120
char *label;
2121
2121
2122
2122
err = of_pci_get_devfn(port);
2123
-
if (err < 0) {
2124
-
dev_err(dev, "failed to parse address: %d\n", err);
2125
-
goto err_node_put;
2126
-
}
2123
+
if (err < 0)
2124
+
return dev_err_probe(dev, err, "failed to parse address\n");
2127
2125
2128
2126
index = PCI_SLOT(err);
2129
2127
2130
-
if (index < 1 || index > soc->num_ports) {
2131
-
dev_err(dev, "invalid port number: %d\n", index);
2132
-
err = -EINVAL;
2133
-
goto err_node_put;
2134
-
}
2128
+
if (index < 1 || index > soc->num_ports)
2129
+
return dev_err_probe(dev, -EINVAL,
2130
+
"invalid port number: %d\n", index);
2135
2131
2136
2132
index--;
2137
2133
2138
2134
err = of_property_read_u32(port, "nvidia,num-lanes", &value);
2139
-
if (err < 0) {
2140
-
dev_err(dev, "failed to parse # of lanes: %d\n",
2141
-
err);
2142
-
goto err_node_put;
2143
-
}
2135
+
if (err < 0)
2136
+
return dev_err_probe(dev, err,
2137
+
"failed to parse # of lanes\n");
2144
2138
2145
-
if (value > 16) {
2146
-
dev_err(dev, "invalid # of lanes: %u\n", value);
2147
-
err = -EINVAL;
2148
-
goto err_node_put;
2149
-
}
2139
+
if (value > 16)
2140
+
return dev_err_probe(dev, -EINVAL,
2141
+
"invalid # of lanes: %u\n", value);
2150
2142
2151
2143
lanes |= value << (index << 3);
2152
2144
···
2151
2159
lane += value;
2152
2160
2153
2161
rp = devm_kzalloc(dev, sizeof(*rp), GFP_KERNEL);
2154
-
if (!rp) {
2155
-
err = -ENOMEM;
2156
-
goto err_node_put;
2157
-
}
2162
+
if (!rp)
2163
+
return -ENOMEM;
2158
2164
2159
2165
err = of_address_to_resource(port, 0, &rp->regs);
2160
-
if (err < 0) {
2161
-
dev_err(dev, "failed to parse address: %d\n", err);
2162
-
goto err_node_put;
2163
-
}
2166
+
if (err < 0)
2167
+
return dev_err_probe(dev, err, "failed to parse address\n");
2164
2168
2165
2169
INIT_LIST_HEAD(&rp->list);
2166
2170
rp->index = index;
···
2165
2177
rp->np = port;
2166
2178
2167
2179
rp->base = devm_pci_remap_cfg_resource(dev, &rp->regs);
2168
-
if (IS_ERR(rp->base)) {
2169
-
err = PTR_ERR(rp->base);
2170
-
goto err_node_put;
2171
-
}
2180
+
if (IS_ERR(rp->base))
2181
+
return PTR_ERR(rp->base);
2172
2182
2173
2183
label = devm_kasprintf(dev, GFP_KERNEL, "pex-reset-%u", index);
2174
-
if (!label) {
2175
-
err = -ENOMEM;
2176
-
goto err_node_put;
2177
-
}
2184
+
if (!label)
2185
+
return -ENOMEM;
2178
2186
2179
2187
/*
2180
2188
* Returns -ENOENT if reset-gpios property is not populated
···
2183
2199
GPIOD_OUT_LOW,
2184
2200
label);
2185
2201
if (IS_ERR(rp->reset_gpio)) {
2186
-
if (PTR_ERR(rp->reset_gpio) == -ENOENT) {
2202
+
if (PTR_ERR(rp->reset_gpio) == -ENOENT)
2187
2203
rp->reset_gpio = NULL;
2188
-
} else {
2189
-
dev_err(dev, "failed to get reset GPIO: %ld\n",
2190
-
PTR_ERR(rp->reset_gpio));
2191
-
err = PTR_ERR(rp->reset_gpio);
2192
-
goto err_node_put;
2193
-
}
2204
+
else
2205
+
return dev_err_probe(dev, PTR_ERR(rp->reset_gpio),
2206
+
"failed to get reset GPIO\n");
2194
2207
}
2195
2208
2196
2209
list_add_tail(&rp->list, &pcie->ports);
2197
2210
}
2198
2211
2199
2212
err = tegra_pcie_get_xbar_config(pcie, lanes, &pcie->xbar_config);
2200
-
if (err < 0) {
2201
-
dev_err(dev, "invalid lane configuration\n");
2202
-
return err;
2203
-
}
2213
+
if (err < 0)
2214
+
return dev_err_probe(dev, err,
2215
+
"invalid lane configuration\n");
2204
2216
2205
2217
err = tegra_pcie_get_regulators(pcie, mask);
2206
2218
if (err < 0)
2207
2219
return err;
2208
2220
2209
2221
return 0;
2210
-
2211
-
err_node_put:
2212
-
of_node_put(port);
2213
-
return err;
2214
2222
}
2215
2223
2216
2224
/*
+1
-1
drivers/pci/controller/pci-thunder-ecam.c
+1
-1
drivers/pci/controller/pci-thunder-ecam.c
+1
-1
drivers/pci/controller/pci-xgene-msi.c
+1
-1
drivers/pci/controller/pci-xgene-msi.c
···
154
154
* X-Gene v1 only has 16 MSI GIC IRQs for 2048 MSI vectors. To maintain
155
155
* the expected behaviour of .set_affinity for each MSI interrupt, the 16
156
156
* MSI GIC IRQs are statically allocated to 8 X-Gene v1 cores (2 GIC IRQs
157
-
* for each core). The MSI vector is moved fom 1 MSI GIC IRQ to another
157
+
* for each core). The MSI vector is moved from 1 MSI GIC IRQ to another
158
158
* MSI GIC IRQ to steer its MSI interrupt to correct X-Gene v1 core. As a
159
159
* consequence, the total MSI vectors that X-Gene v1 supports will be
160
160
* reduced to 256 (2048/8) vectors.
+247
-10
drivers/pci/controller/pcie-altera.c
+247
-10
drivers/pci/controller/pcie-altera.c
···
6
6
* Description: Altera PCIe host controller driver
7
7
*/
8
8
9
+
#include <linux/bitfield.h>
9
10
#include <linux/delay.h>
10
11
#include <linux/interrupt.h>
11
12
#include <linux/irqchip/chained_irq.h>
···
78
77
#define S10_TLP_FMTTYPE_CFGWR0 0x45
79
78
#define S10_TLP_FMTTYPE_CFGWR1 0x44
80
79
80
+
#define AGLX_RP_CFG_ADDR(pcie, reg) (((pcie)->hip_base) + (reg))
81
+
#define AGLX_RP_SECONDARY(pcie) \
82
+
readb(AGLX_RP_CFG_ADDR(pcie, PCI_SECONDARY_BUS))
83
+
84
+
#define AGLX_BDF_REG 0x00002004
85
+
#define AGLX_ROOT_PORT_IRQ_STATUS 0x14c
86
+
#define AGLX_ROOT_PORT_IRQ_ENABLE 0x150
87
+
#define CFG_AER BIT(4)
88
+
89
+
#define AGLX_CFG_TARGET GENMASK(13, 12)
90
+
#define AGLX_CFG_TARGET_TYPE0 0
91
+
#define AGLX_CFG_TARGET_TYPE1 1
92
+
#define AGLX_CFG_TARGET_LOCAL_2000 2
93
+
#define AGLX_CFG_TARGET_LOCAL_3000 3
94
+
81
95
enum altera_pcie_version {
82
96
ALTERA_PCIE_V1 = 0,
83
97
ALTERA_PCIE_V2,
98
+
ALTERA_PCIE_V3,
84
99
};
85
100
86
101
struct altera_pcie {
···
119
102
int size, u32 *value);
120
103
int (*rp_write_cfg)(struct altera_pcie *pcie, u8 busno,
121
104
int where, int size, u32 value);
105
+
int (*ep_read_cfg)(struct altera_pcie *pcie, u8 busno,
106
+
unsigned int devfn, int where, int size, u32 *value);
107
+
int (*ep_write_cfg)(struct altera_pcie *pcie, u8 busno,
108
+
unsigned int devfn, int where, int size, u32 value);
109
+
void (*rp_isr)(struct irq_desc *desc);
122
110
};
123
111
124
112
struct altera_pcie_data {
···
134
112
u32 cfgrd1;
135
113
u32 cfgwr0;
136
114
u32 cfgwr1;
115
+
u32 port_conf_offset;
116
+
u32 port_irq_status_offset;
117
+
u32 port_irq_enable_offset;
137
118
};
138
119
139
120
struct tlp_rp_regpair_t {
···
156
131
return readl_relaxed(pcie->cra_base + reg);
157
132
}
158
133
134
+
static inline void cra_writew(struct altera_pcie *pcie, const u32 value,
135
+
const u32 reg)
136
+
{
137
+
writew_relaxed(value, pcie->cra_base + reg);
138
+
}
139
+
140
+
static inline u32 cra_readw(struct altera_pcie *pcie, const u32 reg)
141
+
{
142
+
return readw_relaxed(pcie->cra_base + reg);
143
+
}
144
+
145
+
static inline void cra_writeb(struct altera_pcie *pcie, const u32 value,
146
+
const u32 reg)
147
+
{
148
+
writeb_relaxed(value, pcie->cra_base + reg);
149
+
}
150
+
151
+
static inline u32 cra_readb(struct altera_pcie *pcie, const u32 reg)
152
+
{
153
+
return readb_relaxed(pcie->cra_base + reg);
154
+
}
155
+
159
156
static bool altera_pcie_link_up(struct altera_pcie *pcie)
160
157
{
161
158
return !!((cra_readl(pcie, RP_LTSSM) & RP_LTSSM_MASK) == LTSSM_L0);
···
192
145
return !!(readw(addr) & PCI_EXP_LNKSTA_DLLLA);
193
146
}
194
147
148
+
static bool aglx_altera_pcie_link_up(struct altera_pcie *pcie)
149
+
{
150
+
void __iomem *addr = AGLX_RP_CFG_ADDR(pcie,
151
+
pcie->pcie_data->cap_offset +
152
+
PCI_EXP_LNKSTA);
153
+
154
+
return (readw_relaxed(addr) & PCI_EXP_LNKSTA_DLLLA);
155
+
}
156
+
195
157
/*
196
158
* Altera PCIe port uses BAR0 of RC's configuration space as the translation
197
159
* from PCI bus to native BUS. Entire DDR region is mapped into PCIe space
198
160
* using these registers, so it can be reached by DMA from EP devices.
199
-
* This BAR0 will also access to MSI vector when receiving MSI/MSIX interrupt
161
+
* This BAR0 will also access to MSI vector when receiving MSI/MSI-X interrupt
200
162
* from EP devices, eventually trigger interrupt to GIC. The BAR0 of bridge
201
163
* should be hidden during enumeration to avoid the sizing and resource
202
164
* allocation by PCIe core.
···
481
425
return PCIBIOS_SUCCESSFUL;
482
426
}
483
427
428
+
static int aglx_rp_read_cfg(struct altera_pcie *pcie, int where,
429
+
int size, u32 *value)
430
+
{
431
+
void __iomem *addr = AGLX_RP_CFG_ADDR(pcie, where);
432
+
433
+
switch (size) {
434
+
case 1:
435
+
*value = readb_relaxed(addr);
436
+
break;
437
+
case 2:
438
+
*value = readw_relaxed(addr);
439
+
break;
440
+
default:
441
+
*value = readl_relaxed(addr);
442
+
break;
443
+
}
444
+
445
+
/* Interrupt PIN not programmed in hardware, set to INTA. */
446
+
if (where == PCI_INTERRUPT_PIN && size == 1 && !(*value))
447
+
*value = 0x01;
448
+
else if (where == PCI_INTERRUPT_LINE && !(*value & 0xff00))
449
+
*value |= 0x0100;
450
+
451
+
return PCIBIOS_SUCCESSFUL;
452
+
}
453
+
454
+
static int aglx_rp_write_cfg(struct altera_pcie *pcie, u8 busno,
455
+
int where, int size, u32 value)
456
+
{
457
+
void __iomem *addr = AGLX_RP_CFG_ADDR(pcie, where);
458
+
459
+
switch (size) {
460
+
case 1:
461
+
writeb_relaxed(value, addr);
462
+
break;
463
+
case 2:
464
+
writew_relaxed(value, addr);
465
+
break;
466
+
default:
467
+
writel_relaxed(value, addr);
468
+
break;
469
+
}
470
+
471
+
/*
472
+
* Monitor changes to PCI_PRIMARY_BUS register on Root Port
473
+
* and update local copy of root bus number accordingly.
474
+
*/
475
+
if (busno == pcie->root_bus_nr && where == PCI_PRIMARY_BUS)
476
+
pcie->root_bus_nr = value & 0xff;
477
+
478
+
return PCIBIOS_SUCCESSFUL;
479
+
}
480
+
481
+
static int aglx_ep_write_cfg(struct altera_pcie *pcie, u8 busno,
482
+
unsigned int devfn, int where, int size, u32 value)
483
+
{
484
+
cra_writel(pcie, ((busno << 8) | devfn), AGLX_BDF_REG);
485
+
if (busno > AGLX_RP_SECONDARY(pcie))
486
+
where |= FIELD_PREP(AGLX_CFG_TARGET, AGLX_CFG_TARGET_TYPE1);
487
+
488
+
switch (size) {
489
+
case 1:
490
+
cra_writeb(pcie, value, where);
491
+
break;
492
+
case 2:
493
+
cra_writew(pcie, value, where);
494
+
break;
495
+
default:
496
+
cra_writel(pcie, value, where);
497
+
break;
498
+
}
499
+
500
+
return PCIBIOS_SUCCESSFUL;
501
+
}
502
+
503
+
static int aglx_ep_read_cfg(struct altera_pcie *pcie, u8 busno,
504
+
unsigned int devfn, int where, int size, u32 *value)
505
+
{
506
+
cra_writel(pcie, ((busno << 8) | devfn), AGLX_BDF_REG);
507
+
if (busno > AGLX_RP_SECONDARY(pcie))
508
+
where |= FIELD_PREP(AGLX_CFG_TARGET, AGLX_CFG_TARGET_TYPE1);
509
+
510
+
switch (size) {
511
+
case 1:
512
+
*value = cra_readb(pcie, where);
513
+
break;
514
+
case 2:
515
+
*value = cra_readw(pcie, where);
516
+
break;
517
+
default:
518
+
*value = cra_readl(pcie, where);
519
+
break;
520
+
}
521
+
522
+
return PCIBIOS_SUCCESSFUL;
523
+
}
524
+
484
525
static int _altera_pcie_cfg_read(struct altera_pcie *pcie, u8 busno,
485
526
unsigned int devfn, int where, int size,
486
527
u32 *value)
···
589
436
if (busno == pcie->root_bus_nr && pcie->pcie_data->ops->rp_read_cfg)
590
437
return pcie->pcie_data->ops->rp_read_cfg(pcie, where,
591
438
size, value);
439
+
440
+
if (pcie->pcie_data->ops->ep_read_cfg)
441
+
return pcie->pcie_data->ops->ep_read_cfg(pcie, busno, devfn,
442
+
where, size, value);
592
443
593
444
switch (size) {
594
445
case 1:
···
636
479
637
480
if (busno == pcie->root_bus_nr && pcie->pcie_data->ops->rp_write_cfg)
638
481
return pcie->pcie_data->ops->rp_write_cfg(pcie, busno,
482
+
where, size, value);
483
+
484
+
if (pcie->pcie_data->ops->ep_write_cfg)
485
+
return pcie->pcie_data->ops->ep_write_cfg(pcie, busno, devfn,
639
486
where, size, value);
640
487
641
488
switch (size) {
···
820
659
dev_err_ratelimited(dev, "unexpected IRQ, INT%d\n", bit);
821
660
}
822
661
}
662
+
chained_irq_exit(chip, desc);
663
+
}
823
664
665
+
static void aglx_isr(struct irq_desc *desc)
666
+
{
667
+
struct irq_chip *chip = irq_desc_get_chip(desc);
668
+
struct altera_pcie *pcie;
669
+
struct device *dev;
670
+
u32 status;
671
+
int ret;
672
+
673
+
chained_irq_enter(chip, desc);
674
+
pcie = irq_desc_get_handler_data(desc);
675
+
dev = &pcie->pdev->dev;
676
+
677
+
status = readl(pcie->hip_base + pcie->pcie_data->port_conf_offset +
678
+
pcie->pcie_data->port_irq_status_offset);
679
+
680
+
if (status & CFG_AER) {
681
+
writel(CFG_AER, (pcie->hip_base + pcie->pcie_data->port_conf_offset +
682
+
pcie->pcie_data->port_irq_status_offset));
683
+
684
+
ret = generic_handle_domain_irq(pcie->irq_domain, 0);
685
+
if (ret)
686
+
dev_err_ratelimited(dev, "unexpected IRQ %d\n", pcie->irq);
687
+
}
824
688
chained_irq_exit(chip, desc);
825
689
}
826
690
···
880
694
if (IS_ERR(pcie->cra_base))
881
695
return PTR_ERR(pcie->cra_base);
882
696
883
-
if (pcie->pcie_data->version == ALTERA_PCIE_V2) {
884
-
pcie->hip_base =
885
-
devm_platform_ioremap_resource_byname(pdev, "Hip");
697
+
if (pcie->pcie_data->version == ALTERA_PCIE_V2 ||
698
+
pcie->pcie_data->version == ALTERA_PCIE_V3) {
699
+
pcie->hip_base = devm_platform_ioremap_resource_byname(pdev, "Hip");
886
700
if (IS_ERR(pcie->hip_base))
887
701
return PTR_ERR(pcie->hip_base);
888
702
}
···
892
706
if (pcie->irq < 0)
893
707
return pcie->irq;
894
708
895
-
irq_set_chained_handler_and_data(pcie->irq, altera_pcie_isr, pcie);
709
+
irq_set_chained_handler_and_data(pcie->irq, pcie->pcie_data->ops->rp_isr, pcie);
896
710
return 0;
897
711
}
898
712
···
905
719
.tlp_read_pkt = tlp_read_packet,
906
720
.tlp_write_pkt = tlp_write_packet,
907
721
.get_link_status = altera_pcie_link_up,
722
+
.rp_isr = altera_pcie_isr,
908
723
};
909
724
910
725
static const struct altera_pcie_ops altera_pcie_ops_2_0 = {
···
914
727
.get_link_status = s10_altera_pcie_link_up,
915
728
.rp_read_cfg = s10_rp_read_cfg,
916
729
.rp_write_cfg = s10_rp_write_cfg,
730
+
.rp_isr = altera_pcie_isr,
731
+
};
732
+
733
+
static const struct altera_pcie_ops altera_pcie_ops_3_0 = {
734
+
.rp_read_cfg = aglx_rp_read_cfg,
735
+
.rp_write_cfg = aglx_rp_write_cfg,
736
+
.get_link_status = aglx_altera_pcie_link_up,
737
+
.ep_read_cfg = aglx_ep_read_cfg,
738
+
.ep_write_cfg = aglx_ep_write_cfg,
739
+
.rp_isr = aglx_isr,
917
740
};
918
741
919
742
static const struct altera_pcie_data altera_pcie_1_0_data = {
···
946
749
.cfgwr1 = S10_TLP_FMTTYPE_CFGWR1,
947
750
};
948
751
752
+
static const struct altera_pcie_data altera_pcie_3_0_f_tile_data = {
753
+
.ops = &altera_pcie_ops_3_0,
754
+
.version = ALTERA_PCIE_V3,
755
+
.cap_offset = 0x70,
756
+
.port_conf_offset = 0x14000,
757
+
.port_irq_status_offset = AGLX_ROOT_PORT_IRQ_STATUS,
758
+
.port_irq_enable_offset = AGLX_ROOT_PORT_IRQ_ENABLE,
759
+
};
760
+
761
+
static const struct altera_pcie_data altera_pcie_3_0_p_tile_data = {
762
+
.ops = &altera_pcie_ops_3_0,
763
+
.version = ALTERA_PCIE_V3,
764
+
.cap_offset = 0x70,
765
+
.port_conf_offset = 0x104000,
766
+
.port_irq_status_offset = AGLX_ROOT_PORT_IRQ_STATUS,
767
+
.port_irq_enable_offset = AGLX_ROOT_PORT_IRQ_ENABLE,
768
+
};
769
+
770
+
static const struct altera_pcie_data altera_pcie_3_0_r_tile_data = {
771
+
.ops = &altera_pcie_ops_3_0,
772
+
.version = ALTERA_PCIE_V3,
773
+
.cap_offset = 0x70,
774
+
.port_conf_offset = 0x1300,
775
+
.port_irq_status_offset = 0x0,
776
+
.port_irq_enable_offset = 0x4,
777
+
};
778
+
949
779
static const struct of_device_id altera_pcie_of_match[] = {
950
780
{.compatible = "altr,pcie-root-port-1.0",
951
781
.data = &altera_pcie_1_0_data },
952
782
{.compatible = "altr,pcie-root-port-2.0",
953
783
.data = &altera_pcie_2_0_data },
784
+
{.compatible = "altr,pcie-root-port-3.0-f-tile",
785
+
.data = &altera_pcie_3_0_f_tile_data },
786
+
{.compatible = "altr,pcie-root-port-3.0-p-tile",
787
+
.data = &altera_pcie_3_0_p_tile_data },
788
+
{.compatible = "altr,pcie-root-port-3.0-r-tile",
789
+
.data = &altera_pcie_3_0_r_tile_data },
954
790
{},
955
791
};
956
792
···
1021
791
return ret;
1022
792
}
1023
793
1024
-
/* clear all interrupts */
1025
-
cra_writel(pcie, P2A_INT_STS_ALL, P2A_INT_STATUS);
1026
-
/* enable all interrupts */
1027
-
cra_writel(pcie, P2A_INT_ENA_ALL, P2A_INT_ENABLE);
1028
-
altera_pcie_host_init(pcie);
794
+
if (pcie->pcie_data->version == ALTERA_PCIE_V1 ||
795
+
pcie->pcie_data->version == ALTERA_PCIE_V2) {
796
+
/* clear all interrupts */
797
+
cra_writel(pcie, P2A_INT_STS_ALL, P2A_INT_STATUS);
798
+
/* enable all interrupts */
799
+
cra_writel(pcie, P2A_INT_ENA_ALL, P2A_INT_ENABLE);
800
+
altera_pcie_host_init(pcie);
801
+
} else if (pcie->pcie_data->version == ALTERA_PCIE_V3) {
802
+
writel(CFG_AER,
803
+
pcie->hip_base + pcie->pcie_data->port_conf_offset +
804
+
pcie->pcie_data->port_irq_enable_offset);
805
+
}
1029
806
1030
807
bridge->sysdata = pcie;
1031
808
bridge->busnr = pcie->root_bus_nr;
+1
-3
drivers/pci/controller/pcie-apple.c
+1
-3
drivers/pci/controller/pcie-apple.c
···
732
732
{
733
733
struct device *dev = cfg->parent;
734
734
struct platform_device *platform = to_platform_device(dev);
735
-
struct device_node *of_port;
736
735
struct apple_pcie *pcie;
737
736
int ret;
738
737
···
754
755
if (ret)
755
756
return ret;
756
757
757
-
for_each_child_of_node(dev->of_node, of_port) {
758
+
for_each_child_of_node_scoped(dev->of_node, of_port) {
758
759
ret = apple_pcie_setup_port(pcie, of_port);
759
760
if (ret) {
760
761
dev_err(pcie->dev, "Port %pOF setup fail: %d\n", of_port, ret);
761
-
of_node_put(of_port);
762
762
return ret;
763
763
}
764
764
}
+134
-68
drivers/pci/controller/pcie-brcmstb.c
+134
-68
drivers/pci/controller/pcie-brcmstb.c
···
40
40
/* Broadcom STB PCIe Register Offsets */
41
41
#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1 0x0188
42
42
#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK 0xc
43
-
#define PCIE_RC_CFG_VENDOR_SPCIFIC_REG1_LITTLE_ENDIAN 0x0
43
+
#define PCIE_RC_CFG_VENDOR_SPECIFIC_REG1_LITTLE_ENDIAN 0x0
44
44
45
45
#define PCIE_RC_CFG_PRIV1_ID_VAL3 0x043c
46
46
#define PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK 0xffffff
···
54
54
#define PCIE_RC_DL_MDIO_ADDR 0x1100
55
55
#define PCIE_RC_DL_MDIO_WR_DATA 0x1104
56
56
#define PCIE_RC_DL_MDIO_RD_DATA 0x1108
57
+
58
+
#define PCIE_RC_PL_PHY_CTL_15 0x184c
59
+
#define PCIE_RC_PL_PHY_CTL_15_DIS_PLL_PD_MASK 0x400000
60
+
#define PCIE_RC_PL_PHY_CTL_15_PM_CLK_PERIOD_MASK 0xff
57
61
58
62
#define PCIE_MISC_MISC_CTRL 0x4008
59
63
#define PCIE_MISC_MISC_CTRL_PCIE_RCB_64B_MODE_MASK 0x80
···
150
146
#define MSI_INT_MASK_SET 0x10
151
147
#define MSI_INT_MASK_CLR 0x14
152
148
153
-
#define PCIE_EXT_CFG_DATA 0x8000
154
-
#define PCIE_EXT_CFG_INDEX 0x9000
155
-
156
149
#define PCIE_RGR1_SW_INIT_1_PERST_MASK 0x1
157
150
#define PCIE_RGR1_SW_INIT_1_PERST_SHIFT 0x0
158
151
···
175
174
#define MDIO_PORT0 0x0
176
175
#define MDIO_DATA_MASK 0x7fffffff
177
176
#define MDIO_PORT_MASK 0xf0000
177
+
#define MDIO_PORT_EXT_MASK 0x200000
178
178
#define MDIO_REGAD_MASK 0xffff
179
-
#define MDIO_CMD_MASK 0xfff00000
179
+
#define MDIO_CMD_MASK 0x00100000
180
180
#define MDIO_CMD_READ 0x1
181
181
#define MDIO_CMD_WRITE 0x0
182
182
#define MDIO_DATA_DONE_MASK 0x80000000
···
193
191
#define SSC_STATUS_PLL_LOCK_MASK 0x800
194
192
#define PCIE_BRCM_MAX_MEMC 3
195
193
196
-
#define IDX_ADDR(pcie) ((pcie)->reg_offsets[EXT_CFG_INDEX])
197
-
#define DATA_ADDR(pcie) ((pcie)->reg_offsets[EXT_CFG_DATA])
198
-
#define PCIE_RGR1_SW_INIT_1(pcie) ((pcie)->reg_offsets[RGR1_SW_INIT_1])
199
-
#define HARD_DEBUG(pcie) ((pcie)->reg_offsets[PCIE_HARD_DEBUG])
200
-
#define INTR2_CPU_BASE(pcie) ((pcie)->reg_offsets[PCIE_INTR2_CPU_BASE])
194
+
#define IDX_ADDR(pcie) ((pcie)->cfg->offsets[EXT_CFG_INDEX])
195
+
#define DATA_ADDR(pcie) ((pcie)->cfg->offsets[EXT_CFG_DATA])
196
+
#define PCIE_RGR1_SW_INIT_1(pcie) ((pcie)->cfg->offsets[RGR1_SW_INIT_1])
197
+
#define HARD_DEBUG(pcie) ((pcie)->cfg->offsets[PCIE_HARD_DEBUG])
198
+
#define INTR2_CPU_BASE(pcie) ((pcie)->cfg->offsets[PCIE_INTR2_CPU_BASE])
201
199
202
200
/* Rescal registers */
203
201
#define PCIE_DVT_PMU_PCIE_PHY_CTRL 0xc700
···
236
234
u64 cpu_addr;
237
235
};
238
236
237
+
/*
238
+
* The RESCAL block is tied to PCIe controller #1, regardless of the number of
239
+
* controllers, and turning off PCIe controller #1 prevents access to the RESCAL
240
+
* register blocks, therefore no other controller can access this register
241
+
* space, and depending upon the bus fabric we may get a timeout (UBUS/GISB),
242
+
* or a hang (AXI).
243
+
*/
244
+
#define CFG_QUIRK_AVOID_BRIDGE_SHUTDOWN BIT(0)
245
+
239
246
struct pcie_cfg_data {
240
247
const int *offsets;
241
248
const enum pcie_soc_base soc_base;
242
249
const bool has_phy;
250
+
const u32 quirks;
243
251
u8 num_inbound_wins;
244
252
int (*perst_set)(struct brcm_pcie *pcie, u32 val);
245
253
int (*bridge_sw_init_set)(struct brcm_pcie *pcie, u32 val);
254
+
int (*post_setup)(struct brcm_pcie *pcie);
246
255
};
247
256
248
257
struct subdev_regulators {
···
289
276
int gen;
290
277
u64 msi_target_addr;
291
278
struct brcm_msi *msi;
292
-
const int *reg_offsets;
293
-
enum pcie_soc_base soc_base;
294
279
struct reset_control *rescal;
295
280
struct reset_control *perst_reset;
296
281
struct reset_control *bridge_reset;
···
296
285
int num_memc;
297
286
u64 memc_size[PCIE_BRCM_MAX_MEMC];
298
287
u32 hw_rev;
299
-
int (*perst_set)(struct brcm_pcie *pcie, u32 val);
300
-
int (*bridge_sw_init_set)(struct brcm_pcie *pcie, u32 val);
301
288
struct subdev_regulators *sr;
302
289
bool ep_wakeup_capable;
303
-
bool has_phy;
304
-
u8 num_inbound_wins;
290
+
const struct pcie_cfg_data *cfg;
305
291
};
306
292
307
293
static inline bool is_bmips(const struct brcm_pcie *pcie)
308
294
{
309
-
return pcie->soc_base == BCM7435 || pcie->soc_base == BCM7425;
295
+
return pcie->cfg->soc_base == BCM7435 || pcie->cfg->soc_base == BCM7425;
310
296
}
311
297
312
298
/*
···
317
309
if (log2_in >= 12 && log2_in <= 15)
318
310
/* Covers 4KB to 32KB (inclusive) */
319
311
return (log2_in - 12) + 0x1c;
320
-
else if (log2_in >= 16 && log2_in <= 35)
321
-
/* Covers 64KB to 32GB, (inclusive) */
312
+
else if (log2_in >= 16 && log2_in <= 36)
313
+
/* Covers 64KB to 64GB, (inclusive) */
322
314
return log2_in - 15;
323
315
/* Something is awry so disable */
324
316
return 0;
···
328
320
{
329
321
u32 pkt = 0;
330
322
323
+
pkt |= FIELD_PREP(MDIO_PORT_EXT_MASK, port >> 4);
331
324
pkt |= FIELD_PREP(MDIO_PORT_MASK, port);
332
325
pkt |= FIELD_PREP(MDIO_REGAD_MASK, regad);
333
326
pkt |= FIELD_PREP(MDIO_CMD_MASK, cmd);
···
412
403
static void brcm_pcie_set_gen(struct brcm_pcie *pcie, int gen)
413
404
{
414
405
u16 lnkctl2 = readw(pcie->base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCTL2);
415
-
u32 lnkcap = readl(pcie->base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCAP);
406
+
u32 lnkcap = readl(pcie->base + PCIE_RC_CFG_PRIV1_LINK_CAPABILITY);
416
407
417
-
lnkcap = (lnkcap & ~PCI_EXP_LNKCAP_SLS) | gen;
418
-
writel(lnkcap, pcie->base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCAP);
408
+
u32p_replace_bits(&lnkcap, gen, PCI_EXP_LNKCAP_SLS);
409
+
writel(lnkcap, pcie->base + PCIE_RC_CFG_PRIV1_LINK_CAPABILITY);
419
410
420
-
lnkctl2 = (lnkctl2 & ~0xf) | gen;
411
+
u16p_replace_bits(&lnkctl2, gen, PCI_EXP_LNKCTL2_TLS);
421
412
writew(lnkctl2, pcie->base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCTL2);
422
413
}
423
414
···
559
550
return hwirq;
560
551
561
552
for (i = 0; i < nr_irqs; i++)
562
-
irq_domain_set_info(domain, virq + i, hwirq + i,
553
+
irq_domain_set_info(domain, virq + i, (irq_hw_number_t)hwirq + i,
563
554
&brcm_msi_bottom_irq_chip, domain->host_data,
564
555
handle_edge_irq, NULL, NULL);
565
556
return 0;
···
726
717
727
718
/* For devices, write to the config space index register */
728
719
idx = PCIE_ECAM_OFFSET(bus->number, devfn, 0);
729
-
writel(idx, pcie->base + PCIE_EXT_CFG_INDEX);
730
-
return base + PCIE_EXT_CFG_DATA + PCIE_ECAM_REG(where);
720
+
writel(idx, base + IDX_ADDR(pcie));
721
+
return base + DATA_ADDR(pcie) + PCIE_ECAM_REG(where);
731
722
}
732
723
733
724
static void __iomem *brcm7425_pcie_map_bus(struct pci_bus *bus,
···
830
821
return 0;
831
822
}
832
823
824
+
static int brcm_pcie_post_setup_bcm2712(struct brcm_pcie *pcie)
825
+
{
826
+
static const u16 data[] = { 0x50b9, 0xbda1, 0x0094, 0x97b4, 0x5030,
827
+
0x5030, 0x0007 };
828
+
static const u8 regs[] = { 0x16, 0x17, 0x18, 0x19, 0x1b, 0x1c, 0x1e };
829
+
int ret, i;
830
+
u32 tmp;
831
+
832
+
/* Allow a 54MHz (xosc) refclk source */
833
+
ret = brcm_pcie_mdio_write(pcie->base, MDIO_PORT0, SET_ADDR_OFFSET, 0x1600);
834
+
if (ret < 0)
835
+
return ret;
836
+
837
+
for (i = 0; i < ARRAY_SIZE(regs); i++) {
838
+
ret = brcm_pcie_mdio_write(pcie->base, MDIO_PORT0, regs[i], data[i]);
839
+
if (ret < 0)
840
+
return ret;
841
+
}
842
+
843
+
usleep_range(100, 200);
844
+
845
+
/*
846
+
* Set L1SS sub-state timers to avoid lengthy state transitions,
847
+
* PM clock period is 18.52ns (1/54MHz, round down).
848
+
*/
849
+
tmp = readl(pcie->base + PCIE_RC_PL_PHY_CTL_15);
850
+
tmp &= ~PCIE_RC_PL_PHY_CTL_15_PM_CLK_PERIOD_MASK;
851
+
tmp |= 0x12;
852
+
writel(tmp, pcie->base + PCIE_RC_PL_PHY_CTL_15);
853
+
854
+
return 0;
855
+
}
856
+
833
857
static void add_inbound_win(struct inbound_win *b, u8 *count, u64 size,
834
858
u64 cpu_addr, u64 pci_offset)
835
859
{
···
897
855
* security considerations, and is not implemented in our modern
898
856
* SoCs.
899
857
*/
900
-
if (pcie->soc_base != BCM7712)
858
+
if (pcie->cfg->soc_base != BCM7712)
901
859
add_inbound_win(b++, &n, 0, 0, 0);
902
860
903
861
resource_list_for_each_entry(entry, &bridge->dma_ranges) {
···
914
872
* That being said, each BARs size must still be a power of
915
873
* two.
916
874
*/
917
-
if (pcie->soc_base == BCM7712)
875
+
if (pcie->cfg->soc_base == BCM7712)
918
876
add_inbound_win(b++, &n, size, cpu_start, pcie_start);
919
877
920
-
if (n > pcie->num_inbound_wins)
878
+
if (n > pcie->cfg->num_inbound_wins)
921
879
break;
922
880
}
923
881
···
931
889
* that enables multiple memory controllers. As such, it can return
932
890
* now w/o doing special configuration.
933
891
*/
934
-
if (pcie->soc_base == BCM7712)
892
+
if (pcie->cfg->soc_base == BCM7712)
935
893
return n;
936
894
937
895
ret = of_property_read_variable_u64_array(pcie->np, "brcm,scb-sizes", pcie->memc_size, 1,
···
1054
1012
* 7712:
1055
1013
* All of their BARs need to be set.
1056
1014
*/
1057
-
if (pcie->soc_base == BCM7712) {
1015
+
if (pcie->cfg->soc_base == BCM7712) {
1058
1016
/* BUS remap register settings */
1059
1017
reg_offset = brcm_ubus_reg_offset(i);
1060
1018
tmp = lower_32_bits(cpu_addr) & ~0xfff;
···
1078
1036
int memc, ret;
1079
1037
1080
1038
/* Reset the bridge */
1081
-
ret = pcie->bridge_sw_init_set(pcie, 1);
1039
+
ret = pcie->cfg->bridge_sw_init_set(pcie, 1);
1082
1040
if (ret)
1083
1041
return ret;
1084
1042
1085
1043
/* Ensure that PERST# is asserted; some bootloaders may deassert it. */
1086
-
if (pcie->soc_base == BCM2711) {
1087
-
ret = pcie->perst_set(pcie, 1);
1044
+
if (pcie->cfg->soc_base == BCM2711) {
1045
+
ret = pcie->cfg->perst_set(pcie, 1);
1088
1046
if (ret) {
1089
-
pcie->bridge_sw_init_set(pcie, 0);
1047
+
pcie->cfg->bridge_sw_init_set(pcie, 0);
1090
1048
return ret;
1091
1049
}
1092
1050
}
···
1094
1052
usleep_range(100, 200);
1095
1053
1096
1054
/* Take the bridge out of reset */
1097
-
ret = pcie->bridge_sw_init_set(pcie, 0);
1055
+
ret = pcie->cfg->bridge_sw_init_set(pcie, 0);
1098
1056
if (ret)
1099
1057
return ret;
1100
1058
···
1114
1072
*/
1115
1073
if (is_bmips(pcie))
1116
1074
burst = 0x1; /* 256 bytes */
1117
-
else if (pcie->soc_base == BCM2711)
1075
+
else if (pcie->cfg->soc_base == BCM2711)
1118
1076
burst = 0x0; /* 128 bytes */
1119
-
else if (pcie->soc_base == BCM7278)
1077
+
else if (pcie->cfg->soc_base == BCM7278)
1120
1078
burst = 0x3; /* 512 bytes */
1121
1079
else
1122
1080
burst = 0x2; /* 512 bytes */
···
1222
1180
1223
1181
/* PCIe->SCB endian mode for inbound window */
1224
1182
tmp = readl(base + PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1);
1225
-
u32p_replace_bits(&tmp, PCIE_RC_CFG_VENDOR_SPCIFIC_REG1_LITTLE_ENDIAN,
1183
+
u32p_replace_bits(&tmp, PCIE_RC_CFG_VENDOR_SPECIFIC_REG1_LITTLE_ENDIAN,
1226
1184
PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK);
1227
1185
writel(tmp, base + PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1);
1186
+
1187
+
if (pcie->cfg->post_setup) {
1188
+
ret = pcie->cfg->post_setup(pcie);
1189
+
if (ret < 0)
1190
+
return ret;
1191
+
}
1228
1192
1229
1193
return 0;
1230
1194
}
···
1247
1199
u32 timeout_us = 4000000; /* 4 seconds, our setting for L1SS */
1248
1200
1249
1201
/* 7712 does not have this (RGR1) timer */
1250
-
if (pcie->soc_base == BCM7712)
1202
+
if (pcie->cfg->soc_base == BCM7712)
1251
1203
return;
1252
1204
1253
1205
/* Each unit in timeout register is 1/216,000,000 seconds */
···
1324
1276
bool ssc_good = false;
1325
1277
int ret, i;
1326
1278
1279
+
/* Limit the generation if specified */
1280
+
if (pcie->gen)
1281
+
brcm_pcie_set_gen(pcie, pcie->gen);
1282
+
1327
1283
/* Unassert the fundamental reset */
1328
-
ret = pcie->perst_set(pcie, 0);
1284
+
ret = pcie->cfg->perst_set(pcie, 0);
1329
1285
if (ret)
1330
1286
return ret;
1331
1287
···
1353
1301
}
1354
1302
1355
1303
brcm_config_clkreq(pcie);
1356
-
1357
-
if (pcie->gen)
1358
-
brcm_pcie_set_gen(pcie, pcie->gen);
1359
1304
1360
1305
if (pcie->ssc) {
1361
1306
ret = brcm_pcie_set_ssc(pcie);
···
1416
1367
1417
1368
ret = regulator_bulk_get(dev, sr->num_supplies, sr->supplies);
1418
1369
if (ret) {
1419
-
dev_info(dev, "No regulators for downstream device\n");
1370
+
dev_info(dev, "Did not get regulators, err=%d\n", ret);
1371
+
pcie->sr = NULL;
1420
1372
goto no_regulators;
1421
1373
}
1422
1374
···
1440
1390
struct subdev_regulators *sr = pcie->sr;
1441
1391
struct device *dev = &bus->dev;
1442
1392
1443
-
if (!sr)
1393
+
if (!sr || !bus->parent || !pci_is_root_bus(bus->parent))
1444
1394
return;
1445
1395
1446
1396
if (regulator_bulk_disable(sr->num_supplies, sr->supplies))
···
1513
1463
1514
1464
static inline int brcm_phy_start(struct brcm_pcie *pcie)
1515
1465
{
1516
-
return pcie->has_phy ? brcm_phy_cntl(pcie, 1) : 0;
1466
+
return pcie->cfg->has_phy ? brcm_phy_cntl(pcie, 1) : 0;
1517
1467
}
1518
1468
1519
1469
static inline int brcm_phy_stop(struct brcm_pcie *pcie)
1520
1470
{
1521
-
return pcie->has_phy ? brcm_phy_cntl(pcie, 0) : 0;
1471
+
return pcie->cfg->has_phy ? brcm_phy_cntl(pcie, 0) : 0;
1522
1472
}
1523
1473
1524
1474
static int brcm_pcie_turn_off(struct brcm_pcie *pcie)
···
1529
1479
if (brcm_pcie_link_up(pcie))
1530
1480
brcm_pcie_enter_l23(pcie);
1531
1481
/* Assert fundamental reset */
1532
-
ret = pcie->perst_set(pcie, 1);
1482
+
ret = pcie->cfg->perst_set(pcie, 1);
1533
1483
if (ret)
1534
1484
return ret;
1535
1485
···
1543
1493
u32p_replace_bits(&tmp, 1, PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK);
1544
1494
writel(tmp, base + HARD_DEBUG(pcie));
1545
1495
1546
-
/* Shutdown PCIe bridge */
1547
-
ret = pcie->bridge_sw_init_set(pcie, 1);
1496
+
if (!(pcie->cfg->quirks & CFG_QUIRK_AVOID_BRIDGE_SHUTDOWN))
1497
+
/* Shutdown PCIe bridge */
1498
+
ret = pcie->cfg->bridge_sw_init_set(pcie, 1);
1548
1499
1549
1500
return ret;
1550
1501
}
···
1633
1582
goto err_reset;
1634
1583
1635
1584
/* Take bridge out of reset so we can access the SERDES reg */
1636
-
pcie->bridge_sw_init_set(pcie, 0);
1585
+
pcie->cfg->bridge_sw_init_set(pcie, 0);
1637
1586
1638
1587
/* SERDES_IDDQ = 0 */
1639
1588
tmp = readl(base + HARD_DEBUG(pcie));
···
1711
1660
static const int pcie_offsets[] = {
1712
1661
[RGR1_SW_INIT_1] = 0x9210,
1713
1662
[EXT_CFG_INDEX] = 0x9000,
1714
-
[EXT_CFG_DATA] = 0x9004,
1663
+
[EXT_CFG_DATA] = 0x8000,
1715
1664
[PCIE_HARD_DEBUG] = 0x4204,
1716
1665
[PCIE_INTR2_CPU_BASE] = 0x4300,
1717
1666
};
···
1719
1668
static const int pcie_offsets_bcm7278[] = {
1720
1669
[RGR1_SW_INIT_1] = 0xc010,
1721
1670
[EXT_CFG_INDEX] = 0x9000,
1722
-
[EXT_CFG_DATA] = 0x9004,
1671
+
[EXT_CFG_DATA] = 0x8000,
1723
1672
[PCIE_HARD_DEBUG] = 0x4204,
1724
1673
[PCIE_INTR2_CPU_BASE] = 0x4300,
1725
1674
};
···
1733
1682
};
1734
1683
1735
1684
static const int pcie_offsets_bcm7712[] = {
1685
+
[RGR1_SW_INIT_1] = 0x9210,
1736
1686
[EXT_CFG_INDEX] = 0x9000,
1737
-
[EXT_CFG_DATA] = 0x9004,
1687
+
[EXT_CFG_DATA] = 0x8000,
1738
1688
[PCIE_HARD_DEBUG] = 0x4304,
1739
1689
[PCIE_INTR2_CPU_BASE] = 0x4400,
1740
1690
};
···
1754
1702
.perst_set = brcm_pcie_perst_set_generic,
1755
1703
.bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic,
1756
1704
.num_inbound_wins = 3,
1705
+
};
1706
+
1707
+
static const struct pcie_cfg_data bcm2712_cfg = {
1708
+
.offsets = pcie_offsets_bcm7712,
1709
+
.soc_base = BCM7712,
1710
+
.perst_set = brcm_pcie_perst_set_7278,
1711
+
.bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic,
1712
+
.post_setup = brcm_pcie_post_setup_bcm2712,
1713
+
.quirks = CFG_QUIRK_AVOID_BRIDGE_SHUTDOWN,
1714
+
.num_inbound_wins = 10,
1757
1715
};
1758
1716
1759
1717
static const struct pcie_cfg_data bcm4908_cfg = {
···
1817
1755
1818
1756
static const struct of_device_id brcm_pcie_match[] = {
1819
1757
{ .compatible = "brcm,bcm2711-pcie", .data = &bcm2711_cfg },
1758
+
{ .compatible = "brcm,bcm2712-pcie", .data = &bcm2712_cfg },
1820
1759
{ .compatible = "brcm,bcm4908-pcie", .data = &bcm4908_cfg },
1821
1760
{ .compatible = "brcm,bcm7211-pcie", .data = &generic_cfg },
1822
1761
{ .compatible = "brcm,bcm7216-pcie", .data = &bcm7216_cfg },
···
1847
1784
1848
1785
static int brcm_pcie_probe(struct platform_device *pdev)
1849
1786
{
1850
-
struct device_node *np = pdev->dev.of_node, *msi_np;
1787
+
struct device_node *np = pdev->dev.of_node;
1851
1788
struct pci_host_bridge *bridge;
1852
1789
const struct pcie_cfg_data *data;
1853
1790
struct brcm_pcie *pcie;
···
1866
1803
pcie = pci_host_bridge_priv(bridge);
1867
1804
pcie->dev = &pdev->dev;
1868
1805
pcie->np = np;
1869
-
pcie->reg_offsets = data->offsets;
1870
-
pcie->soc_base = data->soc_base;
1871
-
pcie->perst_set = data->perst_set;
1872
-
pcie->bridge_sw_init_set = data->bridge_sw_init_set;
1873
-
pcie->has_phy = data->has_phy;
1874
-
pcie->num_inbound_wins = data->num_inbound_wins;
1806
+
pcie->cfg = data;
1875
1807
1876
1808
pcie->base = devm_platform_ioremap_resource(pdev, 0);
1877
1809
if (IS_ERR(pcie->base))
···
1901
1843
if (ret)
1902
1844
return dev_err_probe(&pdev->dev, ret, "could not enable clock\n");
1903
1845
1904
-
pcie->bridge_sw_init_set(pcie, 0);
1846
+
pcie->cfg->bridge_sw_init_set(pcie, 0);
1905
1847
1906
1848
if (pcie->swinit_reset) {
1907
1849
ret = reset_control_assert(pcie->swinit_reset);
···
1940
1882
goto fail;
1941
1883
1942
1884
pcie->hw_rev = readl(pcie->base + PCIE_MISC_REVISION);
1943
-
if (pcie->soc_base == BCM4908 && pcie->hw_rev >= BRCM_PCIE_HW_REV_3_20) {
1885
+
if (pcie->cfg->soc_base == BCM4908 &&
1886
+
pcie->hw_rev >= BRCM_PCIE_HW_REV_3_20) {
1944
1887
dev_err(pcie->dev, "hardware revision with unsupported PERST# setup\n");
1945
1888
ret = -ENODEV;
1946
1889
goto fail;
1947
1890
}
1948
1891
1949
-
msi_np = of_parse_phandle(pcie->np, "msi-parent", 0);
1950
-
if (pci_msi_enabled() && msi_np == pcie->np) {
1951
-
ret = brcm_pcie_enable_msi(pcie);
1892
+
if (pci_msi_enabled()) {
1893
+
struct device_node *msi_np = of_parse_phandle(pcie->np, "msi-parent", 0);
1894
+
1895
+
if (msi_np == pcie->np)
1896
+
ret = brcm_pcie_enable_msi(pcie);
1897
+
1898
+
of_node_put(msi_np);
1899
+
1952
1900
if (ret) {
1953
1901
dev_err(pcie->dev, "probe of internal MSI failed");
1954
1902
goto fail;
1955
1903
}
1956
1904
}
1957
1905
1958
-
bridge->ops = pcie->soc_base == BCM7425 ? &brcm7425_pcie_ops : &brcm_pcie_ops;
1906
+
bridge->ops = pcie->cfg->soc_base == BCM7425 ?
1907
+
&brcm7425_pcie_ops : &brcm_pcie_ops;
1959
1908
bridge->sysdata = pcie;
1960
1909
1961
1910
platform_set_drvdata(pdev, pcie);
···
2005
1940
MODULE_LICENSE("GPL");
2006
1941
MODULE_DESCRIPTION("Broadcom STB PCIe RC driver");
2007
1942
MODULE_AUTHOR("Broadcom");
1943
+
MODULE_SOFTDEP("pre: irq_bcm2712_mip");
+49
-15
drivers/pci/controller/pcie-mediatek-gen3.c
+49
-15
drivers/pci/controller/pcie-mediatek-gen3.c
···
15
15
#include <linux/irqchip/chained_irq.h>
16
16
#include <linux/irqdomain.h>
17
17
#include <linux/kernel.h>
18
+
#include <linux/mfd/syscon.h>
18
19
#include <linux/module.h>
19
20
#include <linux/msi.h>
20
21
#include <linux/of_device.h>
···
25
24
#include <linux/platform_device.h>
26
25
#include <linux/pm_domain.h>
27
26
#include <linux/pm_runtime.h>
27
+
#include <linux/regmap.h>
28
28
#include <linux/reset.h>
29
29
30
30
#include "../pci.h"
···
354
352
355
353
dev_dbg(pcie->dev, "set %s trans window[%d]: cpu_addr = %#llx, pci_addr = %#llx, size = %#llx\n",
356
354
range_type, *num, (unsigned long long)cpu_addr,
357
-
(unsigned long long)pci_addr, (unsigned long long)table_size);
355
+
(unsigned long long)pci_addr,
356
+
(unsigned long long)table_size);
358
357
359
358
cpu_addr += table_size;
360
359
pci_addr += table_size;
···
890
887
for (i = 0; i < num_resets; i++)
891
888
pcie->phy_resets[i].id = pcie->soc->phy_resets.id[i];
892
889
893
-
ret = devm_reset_control_bulk_get_optional_shared(dev, num_resets, pcie->phy_resets);
890
+
ret = devm_reset_control_bulk_get_optional_shared(dev, num_resets,
891
+
pcie->phy_resets);
894
892
if (ret) {
895
893
dev_err(dev, "failed to get PHY bulk reset\n");
896
894
return ret;
···
921
917
return pcie->num_clks;
922
918
}
923
919
924
-
ret = of_property_read_u32(dev->of_node, "num-lanes", &num_lanes);
925
-
if (ret == 0) {
926
-
if (num_lanes == 0 || num_lanes > 16 || (num_lanes != 1 && num_lanes % 2))
920
+
ret = of_property_read_u32(dev->of_node, "num-lanes", &num_lanes);
921
+
if (ret == 0) {
922
+
if (num_lanes == 0 || num_lanes > 16 ||
923
+
(num_lanes != 1 && num_lanes % 2))
927
924
dev_warn(dev, "invalid num-lanes, using controller defaults\n");
928
-
else
925
+
else
929
926
pcie->num_lanes = num_lanes;
930
-
}
927
+
}
931
928
932
929
return 0;
933
930
}
934
931
935
932
static int mtk_pcie_en7581_power_up(struct mtk_gen3_pcie *pcie)
936
933
{
934
+
struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie);
937
935
struct device *dev = pcie->dev;
936
+
struct resource_entry *entry;
937
+
struct regmap *pbus_regmap;
938
+
u32 val, args[2], size;
939
+
resource_size_t addr;
938
940
int err;
939
-
u32 val;
940
941
941
942
/*
942
943
* The controller may have been left out of reset by the bootloader
···
949
940
*/
950
941
reset_control_bulk_assert(pcie->soc->phy_resets.num_resets,
951
942
pcie->phy_resets);
952
-
reset_control_assert(pcie->mac_reset);
953
943
954
944
/* Wait for the time needed to complete the reset lines assert. */
955
945
msleep(PCIE_EN7581_RESET_TIME_MS);
946
+
947
+
/*
948
+
* Configure PBus base address and base address mask to allow the
949
+
* hw to detect if a given address is accessible on PCIe controller.
950
+
*/
951
+
pbus_regmap = syscon_regmap_lookup_by_phandle_args(dev->of_node,
952
+
"mediatek,pbus-csr",
953
+
ARRAY_SIZE(args),
954
+
args);
955
+
if (IS_ERR(pbus_regmap))
956
+
return PTR_ERR(pbus_regmap);
957
+
958
+
entry = resource_list_first_type(&host->windows, IORESOURCE_MEM);
959
+
if (!entry)
960
+
return -ENODEV;
961
+
962
+
addr = entry->res->start - entry->offset;
963
+
regmap_write(pbus_regmap, args[0], lower_32_bits(addr));
964
+
size = lower_32_bits(resource_size(entry->res));
965
+
regmap_write(pbus_regmap, args[1], GENMASK(31, __fls(size)));
956
966
957
967
/*
958
968
* Unlike the other MediaTek Gen3 controllers, the Airoha EN7581
···
989
961
goto err_phy_on;
990
962
}
991
963
992
-
err = reset_control_bulk_deassert(pcie->soc->phy_resets.num_resets, pcie->phy_resets);
964
+
err = reset_control_bulk_deassert(pcie->soc->phy_resets.num_resets,
965
+
pcie->phy_resets);
993
966
if (err) {
994
967
dev_err(dev, "failed to deassert PHYs\n");
995
968
goto err_phy_deassert;
···
1035
1006
err_clk_prepare_enable:
1036
1007
pm_runtime_put_sync(dev);
1037
1008
pm_runtime_disable(dev);
1038
-
reset_control_bulk_assert(pcie->soc->phy_resets.num_resets, pcie->phy_resets);
1009
+
reset_control_bulk_assert(pcie->soc->phy_resets.num_resets,
1010
+
pcie->phy_resets);
1039
1011
err_phy_deassert:
1040
1012
phy_power_off(pcie->phy);
1041
1013
err_phy_on:
···
1060
1030
usleep_range(PCIE_MTK_RESET_TIME_US, 2 * PCIE_MTK_RESET_TIME_US);
1061
1031
1062
1032
/* PHY power on and enable pipe clock */
1063
-
err = reset_control_bulk_deassert(pcie->soc->phy_resets.num_resets, pcie->phy_resets);
1033
+
err = reset_control_bulk_deassert(pcie->soc->phy_resets.num_resets,
1034
+
pcie->phy_resets);
1064
1035
if (err) {
1065
1036
dev_err(dev, "failed to deassert PHYs\n");
1066
1037
return err;
···
1101
1070
err_phy_on:
1102
1071
phy_exit(pcie->phy);
1103
1072
err_phy_init:
1104
-
reset_control_bulk_assert(pcie->soc->phy_resets.num_resets, pcie->phy_resets);
1073
+
reset_control_bulk_assert(pcie->soc->phy_resets.num_resets,
1074
+
pcie->phy_resets);
1105
1075
1106
1076
return err;
1107
1077
}
···
1117
1085
1118
1086
phy_power_off(pcie->phy);
1119
1087
phy_exit(pcie->phy);
1120
-
reset_control_bulk_assert(pcie->soc->phy_resets.num_resets, pcie->phy_resets);
1088
+
reset_control_bulk_assert(pcie->soc->phy_resets.num_resets,
1089
+
pcie->phy_resets);
1121
1090
}
1122
1091
1123
1092
static int mtk_pcie_get_controller_max_link_speed(struct mtk_gen3_pcie *pcie)
···
1145
1112
* Deassert the line in order to avoid unbalance in deassert_count
1146
1113
* counter since the bulk is shared.
1147
1114
*/
1148
-
reset_control_bulk_deassert(pcie->soc->phy_resets.num_resets, pcie->phy_resets);
1115
+
reset_control_bulk_deassert(pcie->soc->phy_resets.num_resets,
1116
+
pcie->phy_resets);
1149
1117
1150
1118
/* Don't touch the hardware registers before power up */
1151
1119
err = pcie->soc->power_up(pcie);
+5
-10
drivers/pci/controller/pcie-mediatek.c
+5
-10
drivers/pci/controller/pcie-mediatek.c
···
1041
1041
static int mtk_pcie_setup(struct mtk_pcie *pcie)
1042
1042
{
1043
1043
struct device *dev = pcie->dev;
1044
-
struct device_node *node = dev->of_node, *child;
1044
+
struct device_node *node = dev->of_node;
1045
1045
struct mtk_pcie_port *port, *tmp;
1046
1046
int err, slot;
1047
1047
1048
1048
slot = of_get_pci_domain_nr(dev->of_node);
1049
1049
if (slot < 0) {
1050
-
for_each_available_child_of_node(node, child) {
1050
+
for_each_available_child_of_node_scoped(node, child) {
1051
1051
err = of_pci_get_devfn(child);
1052
-
if (err < 0) {
1053
-
dev_err(dev, "failed to get devfn: %d\n", err);
1054
-
goto error_put_node;
1055
-
}
1052
+
if (err < 0)
1053
+
return dev_err_probe(dev, err, "failed to get devfn\n");
1056
1054
1057
1055
slot = PCI_SLOT(err);
1058
1056
1059
1057
err = mtk_pcie_parse_port(pcie, child, slot);
1060
1058
if (err)
1061
-
goto error_put_node;
1059
+
return err;
1062
1060
}
1063
1061
} else {
1064
1062
err = mtk_pcie_parse_port(pcie, node, slot);
···
1077
1079
mtk_pcie_subsys_powerdown(pcie);
1078
1080
1079
1081
return 0;
1080
-
error_put_node:
1081
-
of_node_put(child);
1082
-
return err;
1083
1082
}
1084
1083
1085
1084
static int mtk_pcie_probe(struct platform_device *pdev)
+5
-10
drivers/pci/controller/pcie-mt7621.c
+5
-10
drivers/pci/controller/pcie-mt7621.c
···
258
258
{
259
259
struct device *dev = pcie->dev;
260
260
struct platform_device *pdev = to_platform_device(dev);
261
-
struct device_node *node = dev->of_node, *child;
261
+
struct device_node *node = dev->of_node;
262
262
int err;
263
263
264
264
pcie->base = devm_platform_ioremap_resource(pdev, 0);
265
265
if (IS_ERR(pcie->base))
266
266
return PTR_ERR(pcie->base);
267
267
268
-
for_each_available_child_of_node(node, child) {
268
+
for_each_available_child_of_node_scoped(node, child) {
269
269
int slot;
270
270
271
271
err = of_pci_get_devfn(child);
272
-
if (err < 0) {
273
-
of_node_put(child);
274
-
dev_err(dev, "failed to parse devfn: %d\n", err);
275
-
return err;
276
-
}
272
+
if (err < 0)
273
+
return dev_err_probe(dev, err, "failed to parse devfn\n");
277
274
278
275
slot = PCI_SLOT(err);
279
276
280
277
err = mt7621_pcie_parse_port(pcie, child, slot);
281
-
if (err) {
282
-
of_node_put(child);
278
+
if (err)
283
279
return err;
284
-
}
285
280
}
286
281
287
282
return 0;
+6
-4
drivers/pci/controller/pcie-rcar-host.c
+6
-4
drivers/pci/controller/pcie-rcar-host.c
···
178
178
* space, it's generally only accessible when in endpoint mode.
179
179
* When in root complex mode, the controller is unable to target
180
180
* itself with either type 0 or type 1 accesses, and indeed, any
181
-
* controller initiated target transfer to its own config space
182
-
* result in a completer abort.
181
+
* controller-initiated target transfer to its own config space
182
+
* results in a completer abort.
183
183
*
184
184
* Each channel effectively only supports a single device, but as
185
185
* the same channel <-> device access works for any PCI_SLOT()
···
775
775
if (err)
776
776
return err;
777
777
778
-
/* Two irqs are for MSI, but they are also used for non-MSI irqs */
778
+
/* Two IRQs are for MSI, but they are also used for non-MSI IRQs */
779
779
err = devm_request_irq(dev, msi->irq1, rcar_pcie_msi_irq,
780
780
IRQF_SHARED | IRQF_NO_THREAD,
781
781
rcar_msi_bottom_chip.name, host);
···
792
792
goto err;
793
793
}
794
794
795
-
/* disable all MSIs */
795
+
/* Disable all MSIs */
796
796
rcar_pci_write_reg(pcie, 0, PCIEMSIIER);
797
797
798
798
/*
···
892
892
dev_err(pcie->dev, "Failed to map inbound regions!\n");
893
893
return -EINVAL;
894
894
}
895
+
895
896
/*
896
897
* If the size of the range is larger than the alignment of
897
898
* the start address, we have to use multiple entries to
···
904
903
905
904
size = min(size, alignment);
906
905
}
906
+
907
907
/* Hardware supports max 4GiB inbound region */
908
908
size = min(size, 1ULL << 32);
909
909
+1
-1
drivers/pci/controller/pcie-rockchip-host.c
+1
-1
drivers/pci/controller/pcie-rockchip-host.c
-1
drivers/pci/controller/pcie-rockchip.h
-1
drivers/pci/controller/pcie-rockchip.h
+37
-16
drivers/pci/controller/pcie-xilinx-cpm.c
+37
-16
drivers/pci/controller/pcie-xilinx-cpm.c
···
84
84
CPM,
85
85
CPM5,
86
86
CPM5_HOST1,
87
+
CPM5NC_HOST,
87
88
};
88
89
89
90
/**
···
479
478
{
480
479
const struct xilinx_cpm_variant *variant = port->variant;
481
480
481
+
if (variant->version == CPM5NC_HOST)
482
+
return;
483
+
482
484
if (cpm_pcie_link_up(port))
483
485
dev_info(port->dev, "PCIe Link is UP\n");
484
486
else
···
542
538
if (IS_ERR(port->cfg))
543
539
return PTR_ERR(port->cfg);
544
540
545
-
if (port->variant->version == CPM5) {
541
+
if (port->variant->version == CPM5 ||
542
+
port->variant->version == CPM5_HOST1) {
546
543
port->reg_base = devm_platform_ioremap_resource_byname(pdev,
547
544
"cpm_csr");
548
545
if (IS_ERR(port->reg_base))
···
583
578
584
579
port->dev = dev;
585
580
586
-
err = xilinx_cpm_pcie_init_irq_domain(port);
587
-
if (err)
588
-
return err;
581
+
port->variant = of_device_get_match_data(dev);
582
+
583
+
if (port->variant->version != CPM5NC_HOST) {
584
+
err = xilinx_cpm_pcie_init_irq_domain(port);
585
+
if (err)
586
+
return err;
587
+
}
589
588
590
589
bus = resource_list_first_type(&bridge->windows, IORESOURCE_BUS);
591
-
if (!bus)
592
-
return -ENODEV;
593
-
594
-
port->variant = of_device_get_match_data(dev);
590
+
if (!bus) {
591
+
err = -ENODEV;
592
+
goto err_free_irq_domains;
593
+
}
595
594
596
595
err = xilinx_cpm_pcie_parse_dt(port, bus->res);
597
596
if (err) {
598
597
dev_err(dev, "Parsing DT failed\n");
599
-
goto err_parse_dt;
598
+
goto err_free_irq_domains;
600
599
}
601
600
602
601
xilinx_cpm_pcie_init_port(port);
603
602
604
-
err = xilinx_cpm_setup_irq(port);
605
-
if (err) {
606
-
dev_err(dev, "Failed to set up interrupts\n");
607
-
goto err_setup_irq;
603
+
if (port->variant->version != CPM5NC_HOST) {
604
+
err = xilinx_cpm_setup_irq(port);
605
+
if (err) {
606
+
dev_err(dev, "Failed to set up interrupts\n");
607
+
goto err_setup_irq;
608
+
}
608
609
}
609
610
610
611
bridge->sysdata = port->cfg;
···
623
612
return 0;
624
613
625
614
err_host_bridge:
626
-
xilinx_cpm_free_interrupts(port);
615
+
if (port->variant->version != CPM5NC_HOST)
616
+
xilinx_cpm_free_interrupts(port);
627
617
err_setup_irq:
628
618
pci_ecam_free(port->cfg);
629
-
err_parse_dt:
630
-
xilinx_cpm_free_irq_domains(port);
619
+
err_free_irq_domains:
620
+
if (port->variant->version != CPM5NC_HOST)
621
+
xilinx_cpm_free_irq_domains(port);
631
622
return err;
632
623
}
633
624
···
652
639
.ir_enable = XILINX_CPM_PCIE1_IR_ENABLE,
653
640
};
654
641
642
+
static const struct xilinx_cpm_variant cpm5n_host = {
643
+
.version = CPM5NC_HOST,
644
+
};
645
+
655
646
static const struct of_device_id xilinx_cpm_pcie_of_match[] = {
656
647
{
657
648
.compatible = "xlnx,versal-cpm-host-1.00",
···
668
651
{
669
652
.compatible = "xlnx,versal-cpm5-host1",
670
653
.data = &cpm5_host1,
654
+
},
655
+
{
656
+
.compatible = "xlnx,versal-cpm5nc-host",
657
+
.data = &cpm5n_host,
671
658
},
672
659
{}
673
660
};
+6
-6
drivers/pci/controller/vmd.c
+6
-6
drivers/pci/controller/vmd.c
···
127
127
struct vmd_dev {
128
128
struct pci_dev *dev;
129
129
130
-
spinlock_t cfg_lock;
130
+
raw_spinlock_t cfg_lock;
131
131
void __iomem *cfgbar;
132
132
133
133
int msix_count;
···
393
393
if (!addr)
394
394
return -EFAULT;
395
395
396
-
spin_lock_irqsave(&vmd->cfg_lock, flags);
396
+
raw_spin_lock_irqsave(&vmd->cfg_lock, flags);
397
397
switch (len) {
398
398
case 1:
399
399
*value = readb(addr);
···
408
408
ret = -EINVAL;
409
409
break;
410
410
}
411
-
spin_unlock_irqrestore(&vmd->cfg_lock, flags);
411
+
raw_spin_unlock_irqrestore(&vmd->cfg_lock, flags);
412
412
return ret;
413
413
}
414
414
···
428
428
if (!addr)
429
429
return -EFAULT;
430
430
431
-
spin_lock_irqsave(&vmd->cfg_lock, flags);
431
+
raw_spin_lock_irqsave(&vmd->cfg_lock, flags);
432
432
switch (len) {
433
433
case 1:
434
434
writeb(value, addr);
···
446
446
ret = -EINVAL;
447
447
break;
448
448
}
449
-
spin_unlock_irqrestore(&vmd->cfg_lock, flags);
449
+
raw_spin_unlock_irqrestore(&vmd->cfg_lock, flags);
450
450
return ret;
451
451
}
452
452
···
1029
1029
if (features & VMD_FEAT_OFFSET_FIRST_VECTOR)
1030
1030
vmd->first_vec = 1;
1031
1031
1032
-
spin_lock_init(&vmd->cfg_lock);
1032
+
raw_spin_lock_init(&vmd->cfg_lock);
1033
1033
pci_set_drvdata(dev, vmd);
1034
1034
err = vmd_enable_domain(vmd, features);
1035
1035
if (err)
+15
-3
drivers/pci/devres.c
+15
-3
drivers/pci/devres.c
···
40
40
* Legacy struct storing addresses to whole mapped BARs.
41
41
*/
42
42
struct pcim_iomap_devres {
43
-
void __iomem *table[PCI_STD_NUM_BARS];
43
+
void __iomem *table[PCI_NUM_RESOURCES];
44
44
};
45
45
46
46
/* Used to restore the old INTx state on driver detach. */
···
577
577
{
578
578
void __iomem **legacy_iomap_table;
579
579
580
-
if (bar >= PCI_STD_NUM_BARS)
580
+
if (!pci_bar_index_is_valid(bar))
581
581
return -EINVAL;
582
582
583
583
legacy_iomap_table = (void __iomem **)pcim_iomap_table(pdev);
···
622
622
{
623
623
void __iomem **legacy_iomap_table;
624
624
625
-
if (bar >= PCI_STD_NUM_BARS)
625
+
if (!pci_bar_index_is_valid(bar))
626
626
return;
627
627
628
628
legacy_iomap_table = (void __iomem **)pcim_iomap_table(pdev);
···
654
654
{
655
655
void __iomem *mapping;
656
656
struct pcim_addr_devres *res;
657
+
658
+
if (!pci_bar_index_is_valid(bar))
659
+
return NULL;
657
660
658
661
res = pcim_addr_devres_alloc(pdev);
659
662
if (!res)
···
724
721
{
725
722
int ret;
726
723
struct pcim_addr_devres *res;
724
+
725
+
if (!pci_bar_index_is_valid(bar))
726
+
return IOMEM_ERR_PTR(-EINVAL);
727
727
728
728
res = pcim_addr_devres_alloc(pdev);
729
729
if (!res)
···
828
822
{
829
823
int ret;
830
824
struct pcim_addr_devres *res;
825
+
826
+
if (!pci_bar_index_is_valid(bar))
827
+
return -EINVAL;
831
828
832
829
res = pcim_addr_devres_alloc(pdev);
833
830
if (!res)
···
999
990
{
1000
991
void __iomem *mapping;
1001
992
struct pcim_addr_devres *res;
993
+
994
+
if (!pci_bar_index_is_valid(bar))
995
+
return IOMEM_ERR_PTR(-EINVAL);
1002
996
1003
997
res = pcim_addr_devres_alloc(pdev);
1004
998
if (!res)
+200
-47
drivers/pci/doe.c
+200
-47
drivers/pci/doe.c
···
14
14
15
15
#include <linux/bitfield.h>
16
16
#include <linux/delay.h>
17
+
#include <linux/device.h>
17
18
#include <linux/jiffies.h>
18
19
#include <linux/mutex.h>
19
20
#include <linux/pci.h>
20
21
#include <linux/pci-doe.h>
22
+
#include <linux/sysfs.h>
21
23
#include <linux/workqueue.h>
22
24
23
25
#include "pci.h"
24
26
25
-
#define PCI_DOE_PROTOCOL_DISCOVERY 0
27
+
#define PCI_DOE_FEATURE_DISCOVERY 0
26
28
27
29
/* Timeout of 1 second from 6.30.2 Operation, PCI Spec r6.0 */
28
30
#define PCI_DOE_TIMEOUT HZ
···
45
43
*
46
44
* @pdev: PCI device this mailbox belongs to
47
45
* @cap_offset: Capability offset
48
-
* @prots: Array of protocols supported (encoded as long values)
46
+
* @feats: Array of features supported (encoded as long values)
49
47
* @wq: Wait queue for work item
50
48
* @work_queue: Queue of pci_doe_work items
51
49
* @flags: Bit array of PCI_DOE_FLAG_* flags
50
+
* @sysfs_attrs: Array of sysfs device attributes
52
51
*/
53
52
struct pci_doe_mb {
54
53
struct pci_dev *pdev;
55
54
u16 cap_offset;
56
-
struct xarray prots;
55
+
struct xarray feats;
57
56
58
57
wait_queue_head_t wq;
59
58
struct workqueue_struct *work_queue;
60
59
unsigned long flags;
60
+
61
+
#ifdef CONFIG_SYSFS
62
+
struct device_attribute *sysfs_attrs;
63
+
#endif
61
64
};
62
65
63
-
struct pci_doe_protocol {
66
+
struct pci_doe_feature {
64
67
u16 vid;
65
68
u8 type;
66
69
};
···
73
66
/**
74
67
* struct pci_doe_task - represents a single query/response
75
68
*
76
-
* @prot: DOE Protocol
69
+
* @feat: DOE Feature
77
70
* @request_pl: The request payload
78
71
* @request_pl_sz: Size of the request payload (bytes)
79
72
* @response_pl: The response payload
···
85
78
* @doe_mb: Used internally by the mailbox
86
79
*/
87
80
struct pci_doe_task {
88
-
struct pci_doe_protocol prot;
81
+
struct pci_doe_feature feat;
89
82
const __le32 *request_pl;
90
83
size_t request_pl_sz;
91
84
__le32 *response_pl;
···
98
91
struct work_struct work;
99
92
struct pci_doe_mb *doe_mb;
100
93
};
94
+
95
+
#ifdef CONFIG_SYSFS
96
+
static ssize_t doe_discovery_show(struct device *dev,
97
+
struct device_attribute *attr,
98
+
char *buf)
99
+
{
100
+
return sysfs_emit(buf, "0001:00\n");
101
+
}
102
+
static DEVICE_ATTR_RO(doe_discovery);
103
+
104
+
static struct attribute *pci_doe_sysfs_feature_attrs[] = {
105
+
&dev_attr_doe_discovery.attr,
106
+
NULL
107
+
};
108
+
109
+
static bool pci_doe_features_sysfs_group_visible(struct kobject *kobj)
110
+
{
111
+
struct pci_dev *pdev = to_pci_dev(kobj_to_dev(kobj));
112
+
113
+
return !xa_empty(&pdev->doe_mbs);
114
+
}
115
+
DEFINE_SIMPLE_SYSFS_GROUP_VISIBLE(pci_doe_features_sysfs)
116
+
117
+
const struct attribute_group pci_doe_sysfs_group = {
118
+
.name = "doe_features",
119
+
.attrs = pci_doe_sysfs_feature_attrs,
120
+
.is_visible = SYSFS_GROUP_VISIBLE(pci_doe_features_sysfs),
121
+
};
122
+
123
+
static ssize_t pci_doe_sysfs_feature_show(struct device *dev,
124
+
struct device_attribute *attr,
125
+
char *buf)
126
+
{
127
+
return sysfs_emit(buf, "%s\n", attr->attr.name);
128
+
}
129
+
130
+
static void pci_doe_sysfs_feature_remove(struct pci_dev *pdev,
131
+
struct pci_doe_mb *doe_mb)
132
+
{
133
+
struct device_attribute *attrs = doe_mb->sysfs_attrs;
134
+
struct device *dev = &pdev->dev;
135
+
unsigned long i;
136
+
void *entry;
137
+
138
+
if (!attrs)
139
+
return;
140
+
141
+
doe_mb->sysfs_attrs = NULL;
142
+
xa_for_each(&doe_mb->feats, i, entry) {
143
+
if (attrs[i].show)
144
+
sysfs_remove_file_from_group(&dev->kobj, &attrs[i].attr,
145
+
pci_doe_sysfs_group.name);
146
+
kfree(attrs[i].attr.name);
147
+
}
148
+
kfree(attrs);
149
+
}
150
+
151
+
static int pci_doe_sysfs_feature_populate(struct pci_dev *pdev,
152
+
struct pci_doe_mb *doe_mb)
153
+
{
154
+
struct device *dev = &pdev->dev;
155
+
struct device_attribute *attrs;
156
+
unsigned long num_features = 0;
157
+
unsigned long vid, type;
158
+
unsigned long i;
159
+
void *entry;
160
+
int ret;
161
+
162
+
xa_for_each(&doe_mb->feats, i, entry)
163
+
num_features++;
164
+
165
+
attrs = kcalloc(num_features, sizeof(*attrs), GFP_KERNEL);
166
+
if (!attrs) {
167
+
pci_warn(pdev, "Failed allocating the device_attribute array\n");
168
+
return -ENOMEM;
169
+
}
170
+
171
+
doe_mb->sysfs_attrs = attrs;
172
+
xa_for_each(&doe_mb->feats, i, entry) {
173
+
sysfs_attr_init(&attrs[i].attr);
174
+
vid = xa_to_value(entry) >> 8;
175
+
type = xa_to_value(entry) & 0xFF;
176
+
177
+
if (vid == PCI_VENDOR_ID_PCI_SIG &&
178
+
type == PCI_DOE_FEATURE_DISCOVERY) {
179
+
180
+
/*
181
+
* DOE Discovery, manually displayed by
182
+
* `dev_attr_doe_discovery`
183
+
*/
184
+
continue;
185
+
}
186
+
187
+
attrs[i].attr.name = kasprintf(GFP_KERNEL,
188
+
"%04lx:%02lx", vid, type);
189
+
if (!attrs[i].attr.name) {
190
+
ret = -ENOMEM;
191
+
pci_warn(pdev, "Failed allocating the attribute name\n");
192
+
goto fail;
193
+
}
194
+
195
+
attrs[i].attr.mode = 0444;
196
+
attrs[i].show = pci_doe_sysfs_feature_show;
197
+
198
+
ret = sysfs_add_file_to_group(&dev->kobj, &attrs[i].attr,
199
+
pci_doe_sysfs_group.name);
200
+
if (ret) {
201
+
attrs[i].show = NULL;
202
+
if (ret != -EEXIST) {
203
+
pci_warn(pdev, "Failed adding %s to sysfs group\n",
204
+
attrs[i].attr.name);
205
+
goto fail;
206
+
} else
207
+
kfree(attrs[i].attr.name);
208
+
}
209
+
}
210
+
211
+
return 0;
212
+
213
+
fail:
214
+
pci_doe_sysfs_feature_remove(pdev, doe_mb);
215
+
return ret;
216
+
}
217
+
218
+
void pci_doe_sysfs_teardown(struct pci_dev *pdev)
219
+
{
220
+
struct pci_doe_mb *doe_mb;
221
+
unsigned long index;
222
+
223
+
xa_for_each(&pdev->doe_mbs, index, doe_mb)
224
+
pci_doe_sysfs_feature_remove(pdev, doe_mb);
225
+
}
226
+
227
+
void pci_doe_sysfs_init(struct pci_dev *pdev)
228
+
{
229
+
struct pci_doe_mb *doe_mb;
230
+
unsigned long index;
231
+
int ret;
232
+
233
+
xa_for_each(&pdev->doe_mbs, index, doe_mb) {
234
+
ret = pci_doe_sysfs_feature_populate(pdev, doe_mb);
235
+
if (ret)
236
+
return;
237
+
}
238
+
}
239
+
#endif
101
240
102
241
static int pci_doe_wait(struct pci_doe_mb *doe_mb, unsigned long timeout)
103
242
{
···
336
183
length = 0;
337
184
338
185
/* Write DOE Header */
339
-
val = FIELD_PREP(PCI_DOE_DATA_OBJECT_HEADER_1_VID, task->prot.vid) |
340
-
FIELD_PREP(PCI_DOE_DATA_OBJECT_HEADER_1_TYPE, task->prot.type);
186
+
val = FIELD_PREP(PCI_DOE_DATA_OBJECT_HEADER_1_VID, task->feat.vid) |
187
+
FIELD_PREP(PCI_DOE_DATA_OBJECT_HEADER_1_TYPE, task->feat.type);
341
188
pci_write_config_dword(pdev, offset + PCI_DOE_WRITE, val);
342
189
pci_write_config_dword(pdev, offset + PCI_DOE_WRITE,
343
190
FIELD_PREP(PCI_DOE_DATA_OBJECT_HEADER_2_LENGTH,
···
382
229
int i = 0;
383
230
u32 val;
384
231
385
-
/* Read the first dword to get the protocol */
232
+
/* Read the first dword to get the feature */
386
233
pci_read_config_dword(pdev, offset + PCI_DOE_READ, &val);
387
-
if ((FIELD_GET(PCI_DOE_DATA_OBJECT_HEADER_1_VID, val) != task->prot.vid) ||
388
-
(FIELD_GET(PCI_DOE_DATA_OBJECT_HEADER_1_TYPE, val) != task->prot.type)) {
389
-
dev_err_ratelimited(&pdev->dev, "[%x] expected [VID, Protocol] = [%04x, %02x], got [%04x, %02x]\n",
390
-
doe_mb->cap_offset, task->prot.vid, task->prot.type,
234
+
if ((FIELD_GET(PCI_DOE_DATA_OBJECT_HEADER_1_VID, val) != task->feat.vid) ||
235
+
(FIELD_GET(PCI_DOE_DATA_OBJECT_HEADER_1_TYPE, val) != task->feat.type)) {
236
+
dev_err_ratelimited(&pdev->dev, "[%x] expected [VID, Feature] = [%04x, %02x], got [%04x, %02x]\n",
237
+
doe_mb->cap_offset, task->feat.vid, task->feat.type,
391
238
FIELD_GET(PCI_DOE_DATA_OBJECT_HEADER_1_VID, val),
392
239
FIELD_GET(PCI_DOE_DATA_OBJECT_HEADER_1_TYPE, val));
393
240
return -EIO;
···
549
396
}
550
397
551
398
static int pci_doe_discovery(struct pci_doe_mb *doe_mb, u8 capver, u8 *index, u16 *vid,
552
-
u8 *protocol)
399
+
u8 *feature)
553
400
{
554
401
u32 request_pl = FIELD_PREP(PCI_DOE_DATA_OBJECT_DISC_REQ_3_INDEX,
555
402
*index) |
···
560
407
u32 response_pl;
561
408
int rc;
562
409
563
-
rc = pci_doe(doe_mb, PCI_VENDOR_ID_PCI_SIG, PCI_DOE_PROTOCOL_DISCOVERY,
410
+
rc = pci_doe(doe_mb, PCI_VENDOR_ID_PCI_SIG, PCI_DOE_FEATURE_DISCOVERY,
564
411
&request_pl_le, sizeof(request_pl_le),
565
412
&response_pl_le, sizeof(response_pl_le));
566
413
if (rc < 0)
···
571
418
572
419
response_pl = le32_to_cpu(response_pl_le);
573
420
*vid = FIELD_GET(PCI_DOE_DATA_OBJECT_DISC_RSP_3_VID, response_pl);
574
-
*protocol = FIELD_GET(PCI_DOE_DATA_OBJECT_DISC_RSP_3_PROTOCOL,
421
+
*feature = FIELD_GET(PCI_DOE_DATA_OBJECT_DISC_RSP_3_TYPE,
575
422
response_pl);
576
423
*index = FIELD_GET(PCI_DOE_DATA_OBJECT_DISC_RSP_3_NEXT_INDEX,
577
424
response_pl);
···
579
426
return 0;
580
427
}
581
428
582
-
static void *pci_doe_xa_prot_entry(u16 vid, u8 prot)
429
+
static void *pci_doe_xa_feat_entry(u16 vid, u8 type)
583
430
{
584
-
return xa_mk_value((vid << 8) | prot);
431
+
return xa_mk_value((vid << 8) | type);
585
432
}
586
433
587
-
static int pci_doe_cache_protocols(struct pci_doe_mb *doe_mb)
434
+
static int pci_doe_cache_features(struct pci_doe_mb *doe_mb)
588
435
{
589
436
u8 index = 0;
590
437
u8 xa_idx = 0;
···
595
442
do {
596
443
int rc;
597
444
u16 vid;
598
-
u8 prot;
445
+
u8 type;
599
446
600
447
rc = pci_doe_discovery(doe_mb, PCI_EXT_CAP_VER(hdr), &index,
601
-
&vid, &prot);
448
+
&vid, &type);
602
449
if (rc)
603
450
return rc;
604
451
605
452
pci_dbg(doe_mb->pdev,
606
-
"[%x] Found protocol %d vid: %x prot: %x\n",
607
-
doe_mb->cap_offset, xa_idx, vid, prot);
453
+
"[%x] Found feature %d vid: %x type: %x\n",
454
+
doe_mb->cap_offset, xa_idx, vid, type);
608
455
609
-
rc = xa_insert(&doe_mb->prots, xa_idx++,
610
-
pci_doe_xa_prot_entry(vid, prot), GFP_KERNEL);
456
+
rc = xa_insert(&doe_mb->feats, xa_idx++,
457
+
pci_doe_xa_feat_entry(vid, type), GFP_KERNEL);
611
458
if (rc)
612
459
return rc;
613
460
} while (index);
···
631
478
* @pdev: PCI device to create the DOE mailbox for
632
479
* @cap_offset: Offset of the DOE mailbox
633
480
*
634
-
* Create a single mailbox object to manage the mailbox protocol at the
481
+
* Create a single mailbox object to manage the mailbox feature at the
635
482
* cap_offset specified.
636
483
*
637
484
* RETURNS: created mailbox object on success
···
650
497
doe_mb->pdev = pdev;
651
498
doe_mb->cap_offset = cap_offset;
652
499
init_waitqueue_head(&doe_mb->wq);
653
-
xa_init(&doe_mb->prots);
500
+
xa_init(&doe_mb->feats);
654
501
655
502
doe_mb->work_queue = alloc_ordered_workqueue("%s %s DOE [%x]", 0,
656
503
dev_bus_name(&pdev->dev),
···
673
520
674
521
/*
675
522
* The state machine and the mailbox should be in sync now;
676
-
* Use the mailbox to query protocols.
523
+
* Use the mailbox to query features.
677
524
*/
678
-
rc = pci_doe_cache_protocols(doe_mb);
525
+
rc = pci_doe_cache_features(doe_mb);
679
526
if (rc) {
680
-
pci_err(pdev, "[%x] failed to cache protocols : %d\n",
527
+
pci_err(pdev, "[%x] failed to cache features : %d\n",
681
528
doe_mb->cap_offset, rc);
682
529
goto err_cancel;
683
530
}
···
686
533
687
534
err_cancel:
688
535
pci_doe_cancel_tasks(doe_mb);
689
-
xa_destroy(&doe_mb->prots);
536
+
xa_destroy(&doe_mb->feats);
690
537
err_destroy_wq:
691
538
destroy_workqueue(doe_mb->work_queue);
692
539
err_free:
···
704
551
static void pci_doe_destroy_mb(struct pci_doe_mb *doe_mb)
705
552
{
706
553
pci_doe_cancel_tasks(doe_mb);
707
-
xa_destroy(&doe_mb->prots);
554
+
xa_destroy(&doe_mb->feats);
708
555
destroy_workqueue(doe_mb->work_queue);
709
556
kfree(doe_mb);
710
557
}
711
558
712
559
/**
713
-
* pci_doe_supports_prot() - Return if the DOE instance supports the given
714
-
* protocol
560
+
* pci_doe_supports_feat() - Return if the DOE instance supports the given
561
+
* feature
715
562
* @doe_mb: DOE mailbox capability to query
716
-
* @vid: Protocol Vendor ID
717
-
* @type: Protocol type
563
+
* @vid: Feature Vendor ID
564
+
* @type: Feature type
718
565
*
719
-
* RETURNS: True if the DOE mailbox supports the protocol specified
566
+
* RETURNS: True if the DOE mailbox supports the feature specified
720
567
*/
721
-
static bool pci_doe_supports_prot(struct pci_doe_mb *doe_mb, u16 vid, u8 type)
568
+
static bool pci_doe_supports_feat(struct pci_doe_mb *doe_mb, u16 vid, u8 type)
722
569
{
723
570
unsigned long index;
724
571
void *entry;
725
572
726
-
/* The discovery protocol must always be supported */
727
-
if (vid == PCI_VENDOR_ID_PCI_SIG && type == PCI_DOE_PROTOCOL_DISCOVERY)
573
+
/* The discovery feature must always be supported */
574
+
if (vid == PCI_VENDOR_ID_PCI_SIG && type == PCI_DOE_FEATURE_DISCOVERY)
728
575
return true;
729
576
730
-
xa_for_each(&doe_mb->prots, index, entry)
731
-
if (entry == pci_doe_xa_prot_entry(vid, type))
577
+
xa_for_each(&doe_mb->feats, index, entry)
578
+
if (entry == pci_doe_xa_feat_entry(vid, type))
732
579
return true;
733
580
734
581
return false;
···
756
603
static int pci_doe_submit_task(struct pci_doe_mb *doe_mb,
757
604
struct pci_doe_task *task)
758
605
{
759
-
if (!pci_doe_supports_prot(doe_mb, task->prot.vid, task->prot.type))
606
+
if (!pci_doe_supports_feat(doe_mb, task->feat.vid, task->feat.type))
760
607
return -EINVAL;
761
608
762
609
if (test_bit(PCI_DOE_FLAG_DEAD, &doe_mb->flags))
···
802
649
{
803
650
DECLARE_COMPLETION_ONSTACK(c);
804
651
struct pci_doe_task task = {
805
-
.prot.vid = vendor,
806
-
.prot.type = type,
652
+
.feat.vid = vendor,
653
+
.feat.type = type,
807
654
.request_pl = request,
808
655
.request_pl_sz = request_sz,
809
656
.response_pl = response,
···
830
677
* @vendor: Vendor ID
831
678
* @type: Data Object Type
832
679
*
833
-
* Find first DOE mailbox of a PCI device which supports the given protocol.
680
+
* Find first DOE mailbox of a PCI device which supports the given feature.
834
681
*
835
682
* RETURNS: Pointer to the DOE mailbox or NULL if none was found.
836
683
*/
···
841
688
unsigned long index;
842
689
843
690
xa_for_each(&pdev->doe_mbs, index, doe_mb)
844
-
if (pci_doe_supports_prot(doe_mb, vendor, type))
691
+
if (pci_doe_supports_feat(doe_mb, vendor, type))
845
692
return doe_mb;
846
693
847
694
return NULL;
+1
-1
drivers/pci/endpoint/Kconfig
+1
-1
drivers/pci/endpoint/Kconfig
+1
-1
drivers/pci/endpoint/functions/pci-epf-mhi.c
+1
-1
drivers/pci/endpoint/functions/pci-epf-mhi.c
···
125
125
126
126
static struct pci_epf_header sa8775p_header = {
127
127
.vendorid = PCI_VENDOR_ID_QCOM,
128
-
.deviceid = 0x0306, /* FIXME: Update deviceid for sa8775p EP */
128
+
.deviceid = 0x0116,
129
129
.baseclass_code = PCI_CLASS_OTHERS,
130
130
.interrupt_pin = PCI_INTERRUPT_INTA,
131
131
};
+88
-54
drivers/pci/endpoint/functions/pci-epf-test.c
+88
-54
drivers/pci/endpoint/functions/pci-epf-test.c
···
45
45
#define TIMER_RESOLUTION 1
46
46
47
47
#define CAP_UNALIGNED_ACCESS BIT(0)
48
+
#define CAP_MSI BIT(1)
49
+
#define CAP_MSIX BIT(2)
50
+
#define CAP_INTX BIT(3)
48
51
49
52
static struct workqueue_struct *kpcitest_workqueue;
50
53
···
69
66
};
70
67
71
68
struct pci_epf_test_reg {
72
-
u32 magic;
73
-
u32 command;
74
-
u32 status;
75
-
u64 src_addr;
76
-
u64 dst_addr;
77
-
u32 size;
78
-
u32 checksum;
79
-
u32 irq_type;
80
-
u32 irq_number;
81
-
u32 flags;
82
-
u32 caps;
69
+
__le32 magic;
70
+
__le32 command;
71
+
__le32 status;
72
+
__le64 src_addr;
73
+
__le64 dst_addr;
74
+
__le32 size;
75
+
__le32 checksum;
76
+
__le32 irq_type;
77
+
__le32 irq_number;
78
+
__le32 flags;
79
+
__le32 caps;
83
80
} __packed;
84
81
85
82
static struct pci_epf_header test_header = {
···
327
324
struct pci_epc *epc = epf->epc;
328
325
struct device *dev = &epf->dev;
329
326
struct pci_epc_map src_map, dst_map;
330
-
u64 src_addr = reg->src_addr;
331
-
u64 dst_addr = reg->dst_addr;
332
-
size_t copy_size = reg->size;
327
+
u64 src_addr = le64_to_cpu(reg->src_addr);
328
+
u64 dst_addr = le64_to_cpu(reg->dst_addr);
329
+
size_t orig_size, copy_size;
333
330
ssize_t map_size = 0;
331
+
u32 flags = le32_to_cpu(reg->flags);
332
+
u32 status = 0;
334
333
void *copy_buf = NULL, *buf;
335
334
336
-
if (reg->flags & FLAG_USE_DMA) {
335
+
orig_size = copy_size = le32_to_cpu(reg->size);
336
+
337
+
if (flags & FLAG_USE_DMA) {
337
338
if (!dma_has_cap(DMA_MEMCPY, epf_test->dma_chan_tx->device->cap_mask)) {
338
339
dev_err(dev, "DMA controller doesn't support MEMCPY\n");
339
340
ret = -EINVAL;
···
357
350
src_addr, copy_size, &src_map);
358
351
if (ret) {
359
352
dev_err(dev, "Failed to map source address\n");
360
-
reg->status = STATUS_SRC_ADDR_INVALID;
353
+
status = STATUS_SRC_ADDR_INVALID;
361
354
goto free_buf;
362
355
}
363
356
···
365
358
dst_addr, copy_size, &dst_map);
366
359
if (ret) {
367
360
dev_err(dev, "Failed to map destination address\n");
368
-
reg->status = STATUS_DST_ADDR_INVALID;
361
+
status = STATUS_DST_ADDR_INVALID;
369
362
pci_epc_mem_unmap(epc, epf->func_no, epf->vfunc_no,
370
363
&src_map);
371
364
goto free_buf;
···
374
367
map_size = min_t(size_t, dst_map.pci_size, src_map.pci_size);
375
368
376
369
ktime_get_ts64(&start);
377
-
if (reg->flags & FLAG_USE_DMA) {
370
+
if (flags & FLAG_USE_DMA) {
378
371
ret = pci_epf_test_data_transfer(epf_test,
379
372
dst_map.phys_addr, src_map.phys_addr,
380
373
map_size, 0, DMA_MEM_TO_MEM);
···
398
391
map_size = 0;
399
392
}
400
393
401
-
pci_epf_test_print_rate(epf_test, "COPY", reg->size, &start,
402
-
&end, reg->flags & FLAG_USE_DMA);
394
+
pci_epf_test_print_rate(epf_test, "COPY", orig_size, &start, &end,
395
+
flags & FLAG_USE_DMA);
403
396
404
397
unmap:
405
398
if (map_size) {
···
412
405
413
406
set_status:
414
407
if (!ret)
415
-
reg->status |= STATUS_COPY_SUCCESS;
408
+
status |= STATUS_COPY_SUCCESS;
416
409
else
417
-
reg->status |= STATUS_COPY_FAIL;
410
+
status |= STATUS_COPY_FAIL;
411
+
reg->status = cpu_to_le32(status);
418
412
}
419
413
420
414
static void pci_epf_test_read(struct pci_epf_test *epf_test,
···
431
423
struct pci_epc *epc = epf->epc;
432
424
struct device *dev = &epf->dev;
433
425
struct device *dma_dev = epf->epc->dev.parent;
434
-
u64 src_addr = reg->src_addr;
435
-
size_t src_size = reg->size;
426
+
u64 src_addr = le64_to_cpu(reg->src_addr);
427
+
size_t orig_size, src_size;
436
428
ssize_t map_size = 0;
429
+
u32 flags = le32_to_cpu(reg->flags);
430
+
u32 checksum = le32_to_cpu(reg->checksum);
431
+
u32 status = 0;
432
+
433
+
orig_size = src_size = le32_to_cpu(reg->size);
437
434
438
435
src_buf = kzalloc(src_size, GFP_KERNEL);
439
436
if (!src_buf) {
···
452
439
src_addr, src_size, &map);
453
440
if (ret) {
454
441
dev_err(dev, "Failed to map address\n");
455
-
reg->status = STATUS_SRC_ADDR_INVALID;
442
+
status = STATUS_SRC_ADDR_INVALID;
456
443
goto free_buf;
457
444
}
458
445
459
446
map_size = map.pci_size;
460
-
if (reg->flags & FLAG_USE_DMA) {
447
+
if (flags & FLAG_USE_DMA) {
461
448
dst_phys_addr = dma_map_single(dma_dev, buf, map_size,
462
449
DMA_FROM_DEVICE);
463
450
if (dma_mapping_error(dma_dev, dst_phys_addr)) {
···
494
481
map_size = 0;
495
482
}
496
483
497
-
pci_epf_test_print_rate(epf_test, "READ", reg->size, &start,
498
-
&end, reg->flags & FLAG_USE_DMA);
484
+
pci_epf_test_print_rate(epf_test, "READ", orig_size, &start, &end,
485
+
flags & FLAG_USE_DMA);
499
486
500
-
crc32 = crc32_le(~0, src_buf, reg->size);
501
-
if (crc32 != reg->checksum)
487
+
crc32 = crc32_le(~0, src_buf, orig_size);
488
+
if (crc32 != checksum)
502
489
ret = -EIO;
503
490
504
491
unmap:
···
510
497
511
498
set_status:
512
499
if (!ret)
513
-
reg->status |= STATUS_READ_SUCCESS;
500
+
status |= STATUS_READ_SUCCESS;
514
501
else
515
-
reg->status |= STATUS_READ_FAIL;
502
+
status |= STATUS_READ_FAIL;
503
+
reg->status = cpu_to_le32(status);
516
504
}
517
505
518
506
static void pci_epf_test_write(struct pci_epf_test *epf_test,
···
528
514
struct pci_epc *epc = epf->epc;
529
515
struct device *dev = &epf->dev;
530
516
struct device *dma_dev = epf->epc->dev.parent;
531
-
u64 dst_addr = reg->dst_addr;
532
-
size_t dst_size = reg->size;
517
+
u64 dst_addr = le64_to_cpu(reg->dst_addr);
518
+
size_t orig_size, dst_size;
533
519
ssize_t map_size = 0;
520
+
u32 flags = le32_to_cpu(reg->flags);
521
+
u32 status = 0;
522
+
523
+
orig_size = dst_size = le32_to_cpu(reg->size);
534
524
535
525
dst_buf = kzalloc(dst_size, GFP_KERNEL);
536
526
if (!dst_buf) {
···
542
524
goto set_status;
543
525
}
544
526
get_random_bytes(dst_buf, dst_size);
545
-
reg->checksum = crc32_le(~0, dst_buf, dst_size);
527
+
reg->checksum = cpu_to_le32(crc32_le(~0, dst_buf, dst_size));
546
528
buf = dst_buf;
547
529
548
530
while (dst_size) {
···
550
532
dst_addr, dst_size, &map);
551
533
if (ret) {
552
534
dev_err(dev, "Failed to map address\n");
553
-
reg->status = STATUS_DST_ADDR_INVALID;
535
+
status = STATUS_DST_ADDR_INVALID;
554
536
goto free_buf;
555
537
}
556
538
557
539
map_size = map.pci_size;
558
-
if (reg->flags & FLAG_USE_DMA) {
540
+
if (flags & FLAG_USE_DMA) {
559
541
src_phys_addr = dma_map_single(dma_dev, buf, map_size,
560
542
DMA_TO_DEVICE);
561
543
if (dma_mapping_error(dma_dev, src_phys_addr)) {
···
594
576
map_size = 0;
595
577
}
596
578
597
-
pci_epf_test_print_rate(epf_test, "WRITE", reg->size, &start,
598
-
&end, reg->flags & FLAG_USE_DMA);
579
+
pci_epf_test_print_rate(epf_test, "WRITE", orig_size, &start, &end,
580
+
flags & FLAG_USE_DMA);
599
581
600
582
/*
601
583
* wait 1ms inorder for the write to complete. Without this delay L3
···
612
594
613
595
set_status:
614
596
if (!ret)
615
-
reg->status |= STATUS_WRITE_SUCCESS;
597
+
status |= STATUS_WRITE_SUCCESS;
616
598
else
617
-
reg->status |= STATUS_WRITE_FAIL;
599
+
status |= STATUS_WRITE_FAIL;
600
+
reg->status = cpu_to_le32(status);
618
601
}
619
602
620
603
static void pci_epf_test_raise_irq(struct pci_epf_test *epf_test,
···
624
605
struct pci_epf *epf = epf_test->epf;
625
606
struct device *dev = &epf->dev;
626
607
struct pci_epc *epc = epf->epc;
627
-
u32 status = reg->status | STATUS_IRQ_RAISED;
608
+
u32 status = le32_to_cpu(reg->status);
609
+
u32 irq_number = le32_to_cpu(reg->irq_number);
610
+
u32 irq_type = le32_to_cpu(reg->irq_type);
628
611
int count;
629
612
630
613
/*
631
614
* Set the status before raising the IRQ to ensure that the host sees
632
615
* the updated value when it gets the IRQ.
633
616
*/
634
-
WRITE_ONCE(reg->status, status);
617
+
status |= STATUS_IRQ_RAISED;
618
+
WRITE_ONCE(reg->status, cpu_to_le32(status));
635
619
636
-
switch (reg->irq_type) {
620
+
switch (irq_type) {
637
621
case IRQ_TYPE_INTX:
638
622
pci_epc_raise_irq(epc, epf->func_no, epf->vfunc_no,
639
623
PCI_IRQ_INTX, 0);
640
624
break;
641
625
case IRQ_TYPE_MSI:
642
626
count = pci_epc_get_msi(epc, epf->func_no, epf->vfunc_no);
643
-
if (reg->irq_number > count || count <= 0) {
627
+
if (irq_number > count || count <= 0) {
644
628
dev_err(dev, "Invalid MSI IRQ number %d / %d\n",
645
-
reg->irq_number, count);
629
+
irq_number, count);
646
630
return;
647
631
}
648
632
pci_epc_raise_irq(epc, epf->func_no, epf->vfunc_no,
649
-
PCI_IRQ_MSI, reg->irq_number);
633
+
PCI_IRQ_MSI, irq_number);
650
634
break;
651
635
case IRQ_TYPE_MSIX:
652
636
count = pci_epc_get_msix(epc, epf->func_no, epf->vfunc_no);
653
-
if (reg->irq_number > count || count <= 0) {
654
-
dev_err(dev, "Invalid MSIX IRQ number %d / %d\n",
655
-
reg->irq_number, count);
637
+
if (irq_number > count || count <= 0) {
638
+
dev_err(dev, "Invalid MSI-X IRQ number %d / %d\n",
639
+
irq_number, count);
656
640
return;
657
641
}
658
642
pci_epc_raise_irq(epc, epf->func_no, epf->vfunc_no,
659
-
PCI_IRQ_MSIX, reg->irq_number);
643
+
PCI_IRQ_MSIX, irq_number);
660
644
break;
661
645
default:
662
646
dev_err(dev, "Failed to raise IRQ, unknown type\n");
···
676
654
struct device *dev = &epf->dev;
677
655
enum pci_barno test_reg_bar = epf_test->test_reg_bar;
678
656
struct pci_epf_test_reg *reg = epf_test->reg[test_reg_bar];
657
+
u32 irq_type = le32_to_cpu(reg->irq_type);
679
658
680
-
command = READ_ONCE(reg->command);
659
+
command = le32_to_cpu(READ_ONCE(reg->command));
681
660
if (!command)
682
661
goto reset_handler;
683
662
684
663
WRITE_ONCE(reg->command, 0);
685
664
WRITE_ONCE(reg->status, 0);
686
665
687
-
if ((READ_ONCE(reg->flags) & FLAG_USE_DMA) &&
666
+
if ((le32_to_cpu(READ_ONCE(reg->flags)) & FLAG_USE_DMA) &&
688
667
!epf_test->dma_supported) {
689
668
dev_err(dev, "Cannot transfer data using DMA\n");
690
669
goto reset_handler;
691
670
}
692
671
693
-
if (reg->irq_type > IRQ_TYPE_MSIX) {
672
+
if (irq_type > IRQ_TYPE_MSIX) {
694
673
dev_err(dev, "Failed to detect IRQ type\n");
695
674
goto reset_handler;
696
675
}
···
741
718
if (ret) {
742
719
pci_epf_free_space(epf, epf_test->reg[bar], bar,
743
720
PRIMARY_INTERFACE);
721
+
epf_test->reg[bar] = NULL;
744
722
dev_err(dev, "Failed to set BAR%d\n", bar);
745
723
if (bar == test_reg_bar)
746
724
return ret;
···
776
752
777
753
if (epc->ops->align_addr)
778
754
caps |= CAP_UNALIGNED_ACCESS;
755
+
756
+
if (epf_test->epc_features->msi_capable)
757
+
caps |= CAP_MSI;
758
+
759
+
if (epf_test->epc_features->msix_capable)
760
+
caps |= CAP_MSIX;
761
+
762
+
if (epf_test->epc_features->intx_capable)
763
+
caps |= CAP_INTX;
779
764
780
765
reg->caps = cpu_to_le32(caps);
781
766
}
···
942
909
943
910
pci_epf_free_space(epf, epf_test->reg[bar], bar,
944
911
PRIMARY_INTERFACE);
912
+
epf_test->reg[bar] = NULL;
945
913
}
946
914
}
947
915
+31
-25
drivers/pci/endpoint/pci-epc-core.c
+31
-25
drivers/pci/endpoint/pci-epc-core.c
···
25
25
pci_epc_destroy(epc);
26
26
}
27
27
28
-
static int devm_pci_epc_match(struct device *dev, void *res, void *match_data)
29
-
{
30
-
struct pci_epc **epc = res;
31
-
32
-
return *epc == match_data;
33
-
}
34
-
35
28
/**
36
29
* pci_epc_put() - release the PCI endpoint controller
37
30
* @epc: epc returned by pci_epc_get()
···
602
609
if (!epc_features)
603
610
return -EINVAL;
604
611
612
+
if (epc_features->bar[bar].type == BAR_RESIZABLE &&
613
+
(epf_bar->size < SZ_1M || (u64)epf_bar->size > (SZ_128G * 1024)))
614
+
return -EINVAL;
615
+
605
616
if (epc_features->bar[bar].type == BAR_FIXED &&
606
617
(epc_features->bar[bar].fixed_size != epf_bar->size))
607
618
return -EINVAL;
···
630
633
return ret;
631
634
}
632
635
EXPORT_SYMBOL_GPL(pci_epc_set_bar);
636
+
637
+
/**
638
+
* pci_epc_bar_size_to_rebar_cap() - convert a size to the representation used
639
+
* by the Resizable BAR Capability Register
640
+
* @size: the size to convert
641
+
* @cap: where to store the result
642
+
*
643
+
* Returns 0 on success and a negative error code in case of error.
644
+
*/
645
+
int pci_epc_bar_size_to_rebar_cap(size_t size, u32 *cap)
646
+
{
647
+
/*
648
+
* As per PCIe r6.0, sec 7.8.6.2, min size for a resizable BAR is 1 MB,
649
+
* thus disallow a requested BAR size smaller than 1 MB.
650
+
* Disallow a requested BAR size larger than 128 TB.
651
+
*/
652
+
if (size < SZ_1M || (u64)size > (SZ_128G * 1024))
653
+
return -EINVAL;
654
+
655
+
*cap = ilog2(size) - ilog2(SZ_1M);
656
+
657
+
/* Sizes in REBAR_CAP start at BIT(4). */
658
+
*cap = BIT(*cap + 4);
659
+
660
+
return 0;
661
+
}
662
+
EXPORT_SYMBOL_GPL(pci_epc_bar_size_to_rebar_cap);
633
663
634
664
/**
635
665
* pci_epc_write_header() - write standard configuration header
···
954
930
device_unregister(&epc->dev);
955
931
}
956
932
EXPORT_SYMBOL_GPL(pci_epc_destroy);
957
-
958
-
/**
959
-
* devm_pci_epc_destroy() - destroy the EPC device
960
-
* @dev: device that wants to destroy the EPC
961
-
* @epc: the EPC device that has to be destroyed
962
-
*
963
-
* Invoke to destroy the devres associated with this
964
-
* pci_epc and destroy the EPC device.
965
-
*/
966
-
void devm_pci_epc_destroy(struct device *dev, struct pci_epc *epc)
967
-
{
968
-
int r;
969
-
970
-
r = devres_release(dev, devm_pci_epc_release, devm_pci_epc_match,
971
-
epc);
972
-
dev_WARN_ONCE(dev, r, "couldn't find PCI EPC resource\n");
973
-
}
974
-
EXPORT_SYMBOL_GPL(devm_pci_epc_destroy);
975
933
976
934
static void pci_epc_release(struct device *dev)
977
935
{
+4
drivers/pci/endpoint/pci-epf-core.c
+4
drivers/pci/endpoint/pci-epf-core.c
···
274
274
if (size < 128)
275
275
size = 128;
276
276
277
+
/* According to PCIe base spec, min size for a resizable BAR is 1 MB. */
278
+
if (epc_features->bar[bar].type == BAR_RESIZABLE && size < SZ_1M)
279
+
size = SZ_1M;
280
+
277
281
if (epc_features->bar[bar].type == BAR_FIXED && bar_fixed_size) {
278
282
if (size > bar_fixed_size) {
279
283
dev_err(&epf->dev,
+1
-1
drivers/pci/hotplug/Kconfig
+1
-1
drivers/pci/hotplug/Kconfig
···
97
97
tristate "Ziatech ZT5550 CompactPCI Hotplug driver"
98
98
depends on HOTPLUG_PCI_CPCI && X86
99
99
help
100
-
Say Y here if you have an Performance Technologies (formerly Intel,
100
+
Say Y here if you have a Performance Technologies (formerly Intel,
101
101
formerly just Ziatech) Ziatech ZT5550 CompactPCI system card.
102
102
103
103
To compile this driver as a module, choose M here: the
-2
drivers/pci/hotplug/cpci_hotplug.h
-2
drivers/pci/hotplug/cpci_hotplug.h
+2
-15
drivers/pci/hotplug/cpci_hotplug_core.c
+2
-15
drivers/pci/hotplug/cpci_hotplug_core.c
···
71
71
enable_slot(struct hotplug_slot *hotplug_slot)
72
72
{
73
73
struct slot *slot = to_slot(hotplug_slot);
74
-
int retval = 0;
75
74
76
75
dbg("%s - physical_slot = %s", __func__, slot_name(slot));
77
76
78
-
if (controller->ops->set_power)
79
-
retval = controller->ops->set_power(slot, 1);
80
-
return retval;
77
+
return 0;
81
78
}
82
79
83
80
static int
···
106
109
}
107
110
cpci_led_on(slot);
108
111
109
-
if (controller->ops->set_power) {
110
-
retval = controller->ops->set_power(slot, 0);
111
-
if (retval)
112
-
goto disable_error;
113
-
}
114
-
115
112
slot->adapter_status = 0;
116
113
117
114
if (slot->extracting) {
···
120
129
static u8
121
130
cpci_get_power_status(struct slot *slot)
122
131
{
123
-
u8 power = 1;
124
-
125
-
if (controller->ops->get_power)
126
-
power = controller->ops->get_power(slot);
127
-
return power;
132
+
return 1;
128
133
}
129
134
130
135
static int
+41
-101
drivers/pci/hotplug/pci_hotplug_core.c
+41
-101
drivers/pci/hotplug/pci_hotplug_core.c
···
14
14
* Scott Murray <scottm@somanetworks.com>
15
15
*/
16
16
17
-
#include <linux/module.h> /* try_module_get & module_put */
17
+
#include <linux/module.h>
18
18
#include <linux/moduleparam.h>
19
19
#include <linux/kernel.h>
20
20
#include <linux/types.h>
21
-
#include <linux/list.h>
22
21
#include <linux/kobject.h>
23
22
#include <linux/sysfs.h>
24
23
#include <linux/pagemap.h>
25
24
#include <linux/init.h>
26
25
#include <linux/mount.h>
27
26
#include <linux/namei.h>
28
-
#include <linux/mutex.h>
29
27
#include <linux/pci.h>
30
28
#include <linux/pci_hotplug.h>
31
29
#include <linux/uaccess.h>
···
40
42
/* local variables */
41
43
static bool debug;
42
44
43
-
static LIST_HEAD(pci_hotplug_slot_list);
44
-
static DEFINE_MUTEX(pci_hp_mutex);
45
-
46
45
/* Weee, fun with macros... */
47
46
#define GET_STATUS(name, type) \
48
47
static int get_##name(struct hotplug_slot *slot, type *value) \
49
48
{ \
50
49
const struct hotplug_slot_ops *ops = slot->ops; \
51
50
int retval = 0; \
52
-
if (!try_module_get(slot->owner)) \
53
-
return -ENODEV; \
54
51
if (ops->get_##name) \
55
52
retval = ops->get_##name(slot, value); \
56
-
module_put(slot->owner); \
57
53
return retval; \
58
54
}
59
55
···
80
88
power = (u8)(lpower & 0xff);
81
89
dbg("power = %d\n", power);
82
90
83
-
if (!try_module_get(slot->owner)) {
84
-
retval = -ENODEV;
85
-
goto exit;
86
-
}
87
91
switch (power) {
88
92
case 0:
89
93
if (slot->ops->disable_slot)
···
95
107
err("Illegal value specified for power\n");
96
108
retval = -EINVAL;
97
109
}
98
-
module_put(slot->owner);
99
110
100
-
exit:
101
111
if (retval)
102
112
return retval;
103
113
return count;
···
132
146
attention = (u8)(lattention & 0xff);
133
147
dbg(" - attention = %d\n", attention);
134
148
135
-
if (!try_module_get(slot->owner)) {
136
-
retval = -ENODEV;
137
-
goto exit;
138
-
}
139
149
if (ops->set_attention_status)
140
150
retval = ops->set_attention_status(slot, attention);
141
-
module_put(slot->owner);
142
151
143
-
exit:
144
152
if (retval)
145
153
return retval;
146
154
return count;
···
192
212
test = (u32)(ltest & 0xffffffff);
193
213
dbg("test = %d\n", test);
194
214
195
-
if (!try_module_get(slot->owner)) {
196
-
retval = -ENODEV;
197
-
goto exit;
198
-
}
199
215
if (slot->ops->hardware_test)
200
216
retval = slot->ops->hardware_test(slot, test);
201
-
module_put(slot->owner);
202
217
203
-
exit:
204
218
if (retval)
205
219
return retval;
206
220
return count;
···
205
231
.store = test_write_file
206
232
};
207
233
208
-
static bool has_power_file(struct pci_slot *pci_slot)
234
+
static bool has_power_file(struct hotplug_slot *slot)
209
235
{
210
-
struct hotplug_slot *slot = pci_slot->hotplug;
211
-
212
-
if ((!slot) || (!slot->ops))
213
-
return false;
214
236
if ((slot->ops->enable_slot) ||
215
237
(slot->ops->disable_slot) ||
216
238
(slot->ops->get_power_status))
···
214
244
return false;
215
245
}
216
246
217
-
static bool has_attention_file(struct pci_slot *pci_slot)
247
+
static bool has_attention_file(struct hotplug_slot *slot)
218
248
{
219
-
struct hotplug_slot *slot = pci_slot->hotplug;
220
-
221
-
if ((!slot) || (!slot->ops))
222
-
return false;
223
249
if ((slot->ops->set_attention_status) ||
224
250
(slot->ops->get_attention_status))
225
251
return true;
226
252
return false;
227
253
}
228
254
229
-
static bool has_latch_file(struct pci_slot *pci_slot)
255
+
static bool has_latch_file(struct hotplug_slot *slot)
230
256
{
231
-
struct hotplug_slot *slot = pci_slot->hotplug;
232
-
233
-
if ((!slot) || (!slot->ops))
234
-
return false;
235
257
if (slot->ops->get_latch_status)
236
258
return true;
237
259
return false;
238
260
}
239
261
240
-
static bool has_adapter_file(struct pci_slot *pci_slot)
262
+
static bool has_adapter_file(struct hotplug_slot *slot)
241
263
{
242
-
struct hotplug_slot *slot = pci_slot->hotplug;
243
-
244
-
if ((!slot) || (!slot->ops))
245
-
return false;
246
264
if (slot->ops->get_adapter_status)
247
265
return true;
248
266
return false;
249
267
}
250
268
251
-
static bool has_test_file(struct pci_slot *pci_slot)
269
+
static bool has_test_file(struct hotplug_slot *slot)
252
270
{
253
-
struct hotplug_slot *slot = pci_slot->hotplug;
254
-
255
-
if ((!slot) || (!slot->ops))
256
-
return false;
257
271
if (slot->ops->hardware_test)
258
272
return true;
259
273
return false;
260
274
}
261
275
262
-
static int fs_add_slot(struct pci_slot *pci_slot)
276
+
static int fs_add_slot(struct hotplug_slot *slot, struct pci_slot *pci_slot)
263
277
{
278
+
struct kobject *kobj;
264
279
int retval = 0;
265
280
266
281
/* Create symbolic link to the hotplug driver module */
267
-
pci_hp_create_module_link(pci_slot);
282
+
kobj = kset_find_obj(module_kset, slot->mod_name);
283
+
if (kobj) {
284
+
retval = sysfs_create_link(&pci_slot->kobj, kobj, "module");
285
+
if (retval)
286
+
dev_err(&pci_slot->bus->dev,
287
+
"Error creating sysfs link (%d)\n", retval);
288
+
kobject_put(kobj);
289
+
}
268
290
269
-
if (has_power_file(pci_slot)) {
291
+
if (has_power_file(slot)) {
270
292
retval = sysfs_create_file(&pci_slot->kobj,
271
293
&hotplug_slot_attr_power.attr);
272
294
if (retval)
273
295
goto exit_power;
274
296
}
275
297
276
-
if (has_attention_file(pci_slot)) {
298
+
if (has_attention_file(slot)) {
277
299
retval = sysfs_create_file(&pci_slot->kobj,
278
300
&hotplug_slot_attr_attention.attr);
279
301
if (retval)
280
302
goto exit_attention;
281
303
}
282
304
283
-
if (has_latch_file(pci_slot)) {
305
+
if (has_latch_file(slot)) {
284
306
retval = sysfs_create_file(&pci_slot->kobj,
285
307
&hotplug_slot_attr_latch.attr);
286
308
if (retval)
287
309
goto exit_latch;
288
310
}
289
311
290
-
if (has_adapter_file(pci_slot)) {
312
+
if (has_adapter_file(slot)) {
291
313
retval = sysfs_create_file(&pci_slot->kobj,
292
314
&hotplug_slot_attr_presence.attr);
293
315
if (retval)
294
316
goto exit_adapter;
295
317
}
296
318
297
-
if (has_test_file(pci_slot)) {
319
+
if (has_test_file(slot)) {
298
320
retval = sysfs_create_file(&pci_slot->kobj,
299
321
&hotplug_slot_attr_test.attr);
300
322
if (retval)
···
296
334
goto exit;
297
335
298
336
exit_test:
299
-
if (has_adapter_file(pci_slot))
337
+
if (has_adapter_file(slot))
300
338
sysfs_remove_file(&pci_slot->kobj,
301
339
&hotplug_slot_attr_presence.attr);
302
340
exit_adapter:
303
-
if (has_latch_file(pci_slot))
341
+
if (has_latch_file(slot))
304
342
sysfs_remove_file(&pci_slot->kobj, &hotplug_slot_attr_latch.attr);
305
343
exit_latch:
306
-
if (has_attention_file(pci_slot))
344
+
if (has_attention_file(slot))
307
345
sysfs_remove_file(&pci_slot->kobj,
308
346
&hotplug_slot_attr_attention.attr);
309
347
exit_attention:
310
-
if (has_power_file(pci_slot))
348
+
if (has_power_file(slot))
311
349
sysfs_remove_file(&pci_slot->kobj, &hotplug_slot_attr_power.attr);
312
350
exit_power:
313
-
pci_hp_remove_module_link(pci_slot);
351
+
sysfs_remove_link(&pci_slot->kobj, "module");
314
352
exit:
315
353
return retval;
316
354
}
317
355
318
-
static void fs_remove_slot(struct pci_slot *pci_slot)
356
+
static void fs_remove_slot(struct hotplug_slot *slot, struct pci_slot *pci_slot)
319
357
{
320
-
if (has_power_file(pci_slot))
358
+
if (has_power_file(slot))
321
359
sysfs_remove_file(&pci_slot->kobj, &hotplug_slot_attr_power.attr);
322
360
323
-
if (has_attention_file(pci_slot))
361
+
if (has_attention_file(slot))
324
362
sysfs_remove_file(&pci_slot->kobj,
325
363
&hotplug_slot_attr_attention.attr);
326
364
327
-
if (has_latch_file(pci_slot))
365
+
if (has_latch_file(slot))
328
366
sysfs_remove_file(&pci_slot->kobj, &hotplug_slot_attr_latch.attr);
329
367
330
-
if (has_adapter_file(pci_slot))
368
+
if (has_adapter_file(slot))
331
369
sysfs_remove_file(&pci_slot->kobj,
332
370
&hotplug_slot_attr_presence.attr);
333
371
334
-
if (has_test_file(pci_slot))
372
+
if (has_test_file(slot))
335
373
sysfs_remove_file(&pci_slot->kobj, &hotplug_slot_attr_test.attr);
336
374
337
-
pci_hp_remove_module_link(pci_slot);
338
-
}
339
-
340
-
static struct hotplug_slot *get_slot_from_name(const char *name)
341
-
{
342
-
struct hotplug_slot *slot;
343
-
344
-
list_for_each_entry(slot, &pci_hotplug_slot_list, slot_list) {
345
-
if (strcmp(hotplug_slot_name(slot), name) == 0)
346
-
return slot;
347
-
}
348
-
return NULL;
375
+
sysfs_remove_link(&pci_slot->kobj, "module");
349
376
}
350
377
351
378
/**
···
427
476
*/
428
477
int pci_hp_add(struct hotplug_slot *slot)
429
478
{
430
-
struct pci_slot *pci_slot = slot->pci_slot;
479
+
struct pci_slot *pci_slot;
431
480
int result;
432
481
433
-
result = fs_add_slot(pci_slot);
482
+
if (WARN_ON(!slot))
483
+
return -EINVAL;
484
+
485
+
pci_slot = slot->pci_slot;
486
+
487
+
result = fs_add_slot(slot, pci_slot);
434
488
if (result)
435
489
return result;
436
490
437
491
kobject_uevent(&pci_slot->kobj, KOBJ_ADD);
438
-
mutex_lock(&pci_hp_mutex);
439
-
list_add(&slot->slot_list, &pci_hotplug_slot_list);
440
-
mutex_unlock(&pci_hp_mutex);
441
-
dbg("Added slot %s to the list\n", hotplug_slot_name(slot));
442
492
return 0;
443
493
}
444
494
EXPORT_SYMBOL_GPL(pci_hp_add);
···
466
514
*/
467
515
void pci_hp_del(struct hotplug_slot *slot)
468
516
{
469
-
struct hotplug_slot *temp;
470
-
471
517
if (WARN_ON(!slot))
472
518
return;
473
519
474
-
mutex_lock(&pci_hp_mutex);
475
-
temp = get_slot_from_name(hotplug_slot_name(slot));
476
-
if (WARN_ON(temp != slot)) {
477
-
mutex_unlock(&pci_hp_mutex);
478
-
return;
479
-
}
480
-
481
-
list_del(&slot->slot_list);
482
-
mutex_unlock(&pci_hp_mutex);
483
-
dbg("Removed slot %s from the list\n", hotplug_slot_name(slot));
484
-
fs_remove_slot(slot->pci_slot);
520
+
fs_remove_slot(slot, slot->pci_slot);
485
521
}
486
522
EXPORT_SYMBOL_GPL(pci_hp_del);
487
523
+4
-1
drivers/pci/hotplug/pciehp_core.c
+4
-1
drivers/pci/hotplug/pciehp_core.c
···
286
286
287
287
static bool pciehp_device_replaced(struct controller *ctrl)
288
288
{
289
-
struct pci_dev *pdev __free(pci_dev_put);
289
+
struct pci_dev *pdev __free(pci_dev_put) = NULL;
290
290
u32 reg;
291
+
292
+
if (pci_dev_is_disconnected(ctrl->pcie->port))
293
+
return false;
291
294
292
295
pdev = pci_get_slot(ctrl->pcie->port->subordinate, PCI_DEVFN(0, 0));
293
296
if (!pdev)
+7
-4
drivers/pci/hotplug/pciehp_hpc.c
+7
-4
drivers/pci/hotplug/pciehp_hpc.c
···
292
292
{
293
293
struct pci_dev *pdev = ctrl_dev(ctrl);
294
294
bool found;
295
-
u16 lnk_status;
295
+
u16 lnk_status, linksta2;
296
296
297
297
if (!pcie_wait_for_link(pdev, true)) {
298
298
ctrl_info(ctrl, "Slot(%s): No link\n", slot_name(ctrl));
···
319
319
return -1;
320
320
}
321
321
322
-
__pcie_update_link_speed(ctrl->pcie->port->subordinate, lnk_status);
322
+
pcie_capability_read_word(pdev, PCI_EXP_LNKSTA2, &linksta2);
323
+
__pcie_update_link_speed(ctrl->pcie->port->subordinate, lnk_status, linksta2);
323
324
324
325
if (!found) {
325
326
ctrl_info(ctrl, "Slot(%s): No device found\n",
···
431
430
* removed immediately after the check so the caller may need to take
432
431
* this into account.
433
432
*
434
-
* It the hotplug controller itself is not available anymore returns
433
+
* If the hotplug controller itself is not available anymore returns
435
434
* %-ENODEV.
436
435
*/
437
436
int pciehp_card_present(struct controller *ctrl)
···
843
842
{
844
843
u16 mask;
845
844
846
-
mask = PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_DLLSCE;
845
+
mask = PCI_EXP_SLTCTL_DLLSCE;
846
+
if (!pciehp_poll_mode)
847
+
mask |= PCI_EXP_SLTCTL_HPIE;
847
848
pcie_write_cmd(ctrl, mask, mask);
848
849
}
849
850
+1
-17
drivers/pci/hotplug/shpchp.h
+1
-17
drivers/pci/hotplug/shpchp.h
···
33
33
extern int shpchp_poll_time;
34
34
extern bool shpchp_debug;
35
35
36
-
#define dbg(format, arg...) \
37
-
do { \
38
-
if (shpchp_debug) \
39
-
printk(KERN_DEBUG "%s: " format, MY_NAME, ## arg); \
40
-
} while (0)
41
-
#define err(format, arg...) \
42
-
printk(KERN_ERR "%s: " format, MY_NAME, ## arg)
43
-
#define info(format, arg...) \
44
-
printk(KERN_INFO "%s: " format, MY_NAME, ## arg)
45
-
#define warn(format, arg...) \
46
-
printk(KERN_WARNING "%s: " format, MY_NAME, ## arg)
47
-
48
36
#define ctrl_dbg(ctrl, format, arg...) \
49
-
do { \
50
-
if (shpchp_debug) \
51
-
pci_printk(KERN_DEBUG, ctrl->pci_dev, \
52
-
format, ## arg); \
53
-
} while (0)
37
+
pci_dbg(ctrl->pci_dev, format, ## arg)
54
38
#define ctrl_err(ctrl, format, arg...) \
55
39
pci_err(ctrl->pci_dev, format, ## arg)
56
40
#define ctrl_info(ctrl, format, arg...) \
+1
-12
drivers/pci/hotplug/shpchp_core.c
+1
-12
drivers/pci/hotplug/shpchp_core.c
···
22
22
#include "shpchp.h"
23
23
24
24
/* Global variables */
25
-
bool shpchp_debug;
26
25
bool shpchp_poll_mode;
27
26
int shpchp_poll_time;
28
27
···
32
33
MODULE_AUTHOR(DRIVER_AUTHOR);
33
34
MODULE_DESCRIPTION(DRIVER_DESC);
34
35
35
-
module_param(shpchp_debug, bool, 0644);
36
36
module_param(shpchp_poll_mode, bool, 0644);
37
37
module_param(shpchp_poll_time, int, 0644);
38
-
MODULE_PARM_DESC(shpchp_debug, "Debugging mode enabled or not");
39
38
MODULE_PARM_DESC(shpchp_poll_mode, "Using polling mechanism for hot-plug events or not");
40
39
MODULE_PARM_DESC(shpchp_poll_time, "Polling mechanism frequency, in seconds");
41
40
···
321
324
322
325
static int __init shpcd_init(void)
323
326
{
324
-
int retval;
325
-
326
-
retval = pci_register_driver(&shpc_driver);
327
-
dbg("%s: pci_register_driver = %d\n", __func__, retval);
328
-
info(DRIVER_DESC " version: " DRIVER_VERSION "\n");
329
-
330
-
return retval;
327
+
return pci_register_driver(&shpc_driver);
331
328
}
332
329
333
330
static void __exit shpcd_cleanup(void)
334
331
{
335
-
dbg("unload_shpchpd()\n");
336
332
pci_unregister_driver(&shpc_driver);
337
-
info(DRIVER_DESC " version: " DRIVER_VERSION " unloaded\n");
338
333
}
339
334
340
335
module_init(shpcd_init);
+1
-1
drivers/pci/hotplug/shpchp_hpc.c
+1
-1
drivers/pci/hotplug/shpchp_hpc.c
+21
-8
drivers/pci/iomap.c
+21
-8
drivers/pci/iomap.c
···
9
9
10
10
#include <linux/export.h>
11
11
12
+
#include "pci.h" /* for pci_bar_index_is_valid() */
13
+
12
14
/**
13
15
* pci_iomap_range - create a virtual mapping cookie for a PCI BAR
14
16
* @dev: PCI device that owns the BAR
···
35
33
unsigned long offset,
36
34
unsigned long maxlen)
37
35
{
38
-
resource_size_t start = pci_resource_start(dev, bar);
39
-
resource_size_t len = pci_resource_len(dev, bar);
40
-
unsigned long flags = pci_resource_flags(dev, bar);
36
+
resource_size_t start, len;
37
+
unsigned long flags;
38
+
39
+
if (!pci_bar_index_is_valid(bar))
40
+
return NULL;
41
+
42
+
start = pci_resource_start(dev, bar);
43
+
len = pci_resource_len(dev, bar);
44
+
flags = pci_resource_flags(dev, bar);
41
45
42
46
if (len <= offset || !start)
43
47
return NULL;
48
+
44
49
len -= offset;
45
50
start += offset;
46
51
if (maxlen && len > maxlen)
···
86
77
unsigned long offset,
87
78
unsigned long maxlen)
88
79
{
89
-
resource_size_t start = pci_resource_start(dev, bar);
90
-
resource_size_t len = pci_resource_len(dev, bar);
91
-
unsigned long flags = pci_resource_flags(dev, bar);
80
+
resource_size_t start, len;
81
+
unsigned long flags;
92
82
93
-
94
-
if (flags & IORESOURCE_IO)
83
+
if (!pci_bar_index_is_valid(bar))
95
84
return NULL;
96
85
86
+
start = pci_resource_start(dev, bar);
87
+
len = pci_resource_len(dev, bar);
88
+
flags = pci_resource_flags(dev, bar);
89
+
97
90
if (len <= offset || !start)
91
+
return NULL;
92
+
if (flags & IORESOURCE_IO)
98
93
return NULL;
99
94
100
95
len -= offset;
+35
-15
drivers/pci/iov.c
+35
-15
drivers/pci/iov.c
···
285
285
.is_visible = sriov_vf_attrs_are_visible,
286
286
};
287
287
288
-
int pci_iov_add_virtfn(struct pci_dev *dev, int id)
288
+
static struct pci_dev *pci_iov_scan_device(struct pci_dev *dev, int id,
289
+
struct pci_bus *bus)
289
290
{
290
-
int i;
291
-
int rc = -ENOMEM;
292
-
u64 size;
293
-
struct pci_dev *virtfn;
294
-
struct resource *res;
295
291
struct pci_sriov *iov = dev->sriov;
296
-
struct pci_bus *bus;
297
-
298
-
bus = virtfn_add_bus(dev->bus, pci_iov_virtfn_bus(dev, id));
299
-
if (!bus)
300
-
goto failed;
292
+
struct pci_dev *virtfn;
293
+
int rc;
301
294
302
295
virtfn = pci_alloc_dev(bus);
303
296
if (!virtfn)
304
-
goto failed0;
297
+
return ERR_PTR(-ENOMEM);
305
298
306
299
virtfn->devfn = pci_iov_virtfn_devfn(dev, id);
307
300
virtfn->vendor = dev->vendor;
···
307
314
pci_read_vf_config_common(virtfn);
308
315
309
316
rc = pci_setup_device(virtfn);
310
-
if (rc)
311
-
goto failed1;
317
+
if (rc) {
318
+
pci_dev_put(dev);
319
+
pci_bus_put(virtfn->bus);
320
+
kfree(virtfn);
321
+
return ERR_PTR(rc);
322
+
}
323
+
324
+
return virtfn;
325
+
}
326
+
327
+
int pci_iov_add_virtfn(struct pci_dev *dev, int id)
328
+
{
329
+
struct pci_bus *bus;
330
+
struct pci_dev *virtfn;
331
+
struct resource *res;
332
+
int rc, i;
333
+
u64 size;
334
+
335
+
bus = virtfn_add_bus(dev->bus, pci_iov_virtfn_bus(dev, id));
336
+
if (!bus) {
337
+
rc = -ENOMEM;
338
+
goto failed;
339
+
}
340
+
341
+
virtfn = pci_iov_scan_device(dev, id, bus);
342
+
if (IS_ERR(virtfn)) {
343
+
rc = PTR_ERR(virtfn);
344
+
goto failed0;
345
+
}
312
346
313
347
virtfn->dev.parent = dev->dev.parent;
314
348
virtfn->multifunction = 0;
···
972
952
void pci_iov_update_resource(struct pci_dev *dev, int resno)
973
953
{
974
954
struct pci_sriov *iov = dev->is_physfn ? dev->sriov : NULL;
975
-
struct resource *res = dev->resource + resno;
955
+
struct resource *res = pci_resource_n(dev, resno);
976
956
int vf_bar = resno - PCI_IOV_RESOURCES;
977
957
struct pci_bus_region region;
978
958
u16 cmd;
+1
-1
drivers/pci/msi/api.c
+1
-1
drivers/pci/msi/api.c
···
162
162
EXPORT_SYMBOL_GPL(pci_msix_alloc_irq_at);
163
163
164
164
/**
165
-
* pci_msix_free_irq - Free an interrupt on a PCI/MSIX interrupt domain
165
+
* pci_msix_free_irq - Free an interrupt on a PCI/MSI-X interrupt domain
166
166
*
167
167
* @dev: The PCI device to operate on
168
168
* @map: A struct msi_map describing the interrupt to free
+121
-6
drivers/pci/of.c
+121
-6
drivers/pci/of.c
···
455
455
* @out_irq: structure of_phandle_args filled by this function
456
456
*
457
457
* This function resolves the PCI interrupt for a given PCI device. If a
458
-
* device-node exists for a given pci_dev, it will use normal OF tree
458
+
* device node exists for a given pci_dev, it will use normal OF tree
459
459
* walking. If not, it will implement standard swizzling and walk up the
460
-
* PCI tree until an device-node is found, at which point it will finish
460
+
* PCI tree until a device node is found, at which point it will finish
461
461
* resolving using the OF tree walking.
462
462
*/
463
463
static int of_irq_parse_pci(const struct pci_dev *pdev, struct of_phandle_args *out_irq)
···
517
517
}
518
518
519
519
/*
520
-
* Ok, we have found a parent with a device-node, hand over to
520
+
* Ok, we have found a parent with a device node, hand over to
521
521
* the OF parsing code.
522
+
*
522
523
* We build a unit address from the linux device to be used for
523
524
* resolution. Note that we use the linux bus number which may
524
525
* not match your firmware bus numbering.
526
+
*
525
527
* Fortunately, in most cases, interrupt-map-mask doesn't
526
528
* include the bus number as part of the matching.
529
+
*
527
530
* You should still be careful about that though if you intend
528
531
* to rely on this function (you ship a firmware that doesn't
529
532
* create device nodes for all PCI devices).
···
656
653
np = pci_device_to_OF_node(pdev);
657
654
if (!np || !of_node_check_flag(np, OF_DYNAMIC))
658
655
return;
659
-
pdev->dev.of_node = NULL;
660
656
657
+
device_remove_of_node(&pdev->dev);
661
658
of_changeset_revert(np->data);
662
659
of_changeset_destroy(np->data);
663
660
of_node_put(np);
···
714
711
goto out_free_node;
715
712
716
713
np->data = cset;
717
-
pdev->dev.of_node = np;
714
+
715
+
ret = device_add_of_node(&pdev->dev, np);
716
+
if (ret)
717
+
goto out_revert_cset;
718
+
718
719
kfree(name);
719
720
720
721
return;
721
722
723
+
out_revert_cset:
724
+
np->data = NULL;
725
+
of_changeset_revert(cset);
722
726
out_free_node:
723
727
of_node_put(np);
724
728
out_destroy_cset:
···
734
724
out_free_name:
735
725
kfree(name);
736
726
}
737
-
#endif
727
+
728
+
void of_pci_remove_host_bridge_node(struct pci_host_bridge *bridge)
729
+
{
730
+
struct device_node *np;
731
+
732
+
np = pci_bus_to_OF_node(bridge->bus);
733
+
if (!np || !of_node_check_flag(np, OF_DYNAMIC))
734
+
return;
735
+
736
+
device_remove_of_node(&bridge->bus->dev);
737
+
device_remove_of_node(&bridge->dev);
738
+
of_changeset_revert(np->data);
739
+
of_changeset_destroy(np->data);
740
+
of_node_put(np);
741
+
}
742
+
743
+
void of_pci_make_host_bridge_node(struct pci_host_bridge *bridge)
744
+
{
745
+
struct device_node *np = NULL;
746
+
struct of_changeset *cset;
747
+
const char *name;
748
+
int ret;
749
+
750
+
/*
751
+
* If there is already a device tree node linked to the PCI bus handled
752
+
* by this bridge (i.e. the PCI root bus), nothing to do.
753
+
*/
754
+
if (pci_bus_to_OF_node(bridge->bus))
755
+
return;
756
+
757
+
/*
758
+
* The root bus has no node. Check that the host bridge has no node
759
+
* too
760
+
*/
761
+
if (bridge->dev.of_node) {
762
+
dev_err(&bridge->dev, "PCI host bridge of_node already set");
763
+
return;
764
+
}
765
+
766
+
/* Check if there is a DT root node to attach the created node */
767
+
if (!of_root) {
768
+
pr_err("of_root node is NULL, cannot create PCI host bridge node\n");
769
+
return;
770
+
}
771
+
772
+
name = kasprintf(GFP_KERNEL, "pci@%x,%x", pci_domain_nr(bridge->bus),
773
+
bridge->bus->number);
774
+
if (!name)
775
+
return;
776
+
777
+
cset = kmalloc(sizeof(*cset), GFP_KERNEL);
778
+
if (!cset)
779
+
goto out_free_name;
780
+
of_changeset_init(cset);
781
+
782
+
np = of_changeset_create_node(cset, of_root, name);
783
+
if (!np)
784
+
goto out_destroy_cset;
785
+
786
+
ret = of_pci_add_host_bridge_properties(bridge, cset, np);
787
+
if (ret)
788
+
goto out_free_node;
789
+
790
+
/*
791
+
* This of_node will be added to an existing device. The of_node parent
792
+
* is the root OF node and so this node will be handled by the platform
793
+
* bus. Avoid any new device creation.
794
+
*/
795
+
of_node_set_flag(np, OF_POPULATED);
796
+
np->fwnode.dev = &bridge->dev;
797
+
fwnode_dev_initialized(&np->fwnode, true);
798
+
799
+
ret = of_changeset_apply(cset);
800
+
if (ret)
801
+
goto out_free_node;
802
+
803
+
np->data = cset;
804
+
805
+
/* Add the of_node to host bridge and the root bus */
806
+
ret = device_add_of_node(&bridge->dev, np);
807
+
if (ret)
808
+
goto out_revert_cset;
809
+
810
+
ret = device_add_of_node(&bridge->bus->dev, np);
811
+
if (ret)
812
+
goto out_remove_bridge_dev_of_node;
813
+
814
+
kfree(name);
815
+
816
+
return;
817
+
818
+
out_remove_bridge_dev_of_node:
819
+
device_remove_of_node(&bridge->dev);
820
+
out_revert_cset:
821
+
np->data = NULL;
822
+
of_changeset_revert(cset);
823
+
out_free_node:
824
+
of_node_put(np);
825
+
out_destroy_cset:
826
+
of_changeset_destroy(cset);
827
+
kfree(cset);
828
+
out_free_name:
829
+
kfree(name);
830
+
}
831
+
832
+
#endif /* CONFIG_PCI_DYNAMIC_OF_NODES */
738
833
739
834
/**
740
835
* of_pci_supply_present() - Check if the power supply is present for the PCI
+111
-4
drivers/pci/of_property.c
+111
-4
drivers/pci/of_property.c
···
54
54
static void of_pci_set_address(struct pci_dev *pdev, u32 *prop, u64 addr,
55
55
u32 reg_num, u32 flags, bool reloc)
56
56
{
57
-
prop[0] = FIELD_PREP(OF_PCI_ADDR_FIELD_BUS, pdev->bus->number) |
58
-
FIELD_PREP(OF_PCI_ADDR_FIELD_DEV, PCI_SLOT(pdev->devfn)) |
59
-
FIELD_PREP(OF_PCI_ADDR_FIELD_FUNC, PCI_FUNC(pdev->devfn));
57
+
if (pdev) {
58
+
prop[0] = FIELD_PREP(OF_PCI_ADDR_FIELD_BUS, pdev->bus->number) |
59
+
FIELD_PREP(OF_PCI_ADDR_FIELD_DEV, PCI_SLOT(pdev->devfn)) |
60
+
FIELD_PREP(OF_PCI_ADDR_FIELD_FUNC, PCI_FUNC(pdev->devfn));
61
+
} else
62
+
prop[0] = 0;
63
+
60
64
prop[0] |= flags | reg_num;
61
65
if (!reloc) {
62
66
prop[0] |= OF_PCI_ADDR_FIELD_NONRELOC;
···
69
65
}
70
66
}
71
67
72
-
static int of_pci_get_addr_flags(struct resource *res, u32 *flags)
68
+
static int of_pci_get_addr_flags(const struct resource *res, u32 *flags)
73
69
{
74
70
u32 ss;
75
71
···
389
385
return ret;
390
386
391
387
ret = of_pci_prop_interrupts(pdev, ocs, np);
388
+
if (ret)
389
+
return ret;
390
+
391
+
return 0;
392
+
}
393
+
394
+
static bool of_pci_is_range_resource(const struct resource *res, u32 *flags)
395
+
{
396
+
if (!(resource_type(res) & IORESOURCE_MEM) &&
397
+
!(resource_type(res) & IORESOURCE_MEM_64))
398
+
return false;
399
+
400
+
if (of_pci_get_addr_flags(res, flags))
401
+
return false;
402
+
403
+
return true;
404
+
}
405
+
406
+
static int of_pci_host_bridge_prop_ranges(struct pci_host_bridge *bridge,
407
+
struct of_changeset *ocs,
408
+
struct device_node *np)
409
+
{
410
+
struct resource_entry *window;
411
+
unsigned int ranges_sz = 0;
412
+
unsigned int n_range = 0;
413
+
struct resource *res;
414
+
int n_addr_cells;
415
+
u32 *ranges;
416
+
u64 val64;
417
+
u32 flags;
418
+
int ret;
419
+
420
+
n_addr_cells = of_n_addr_cells(np);
421
+
if (n_addr_cells <= 0 || n_addr_cells > 2)
422
+
return -EINVAL;
423
+
424
+
resource_list_for_each_entry(window, &bridge->windows) {
425
+
res = window->res;
426
+
if (!of_pci_is_range_resource(res, &flags))
427
+
continue;
428
+
n_range++;
429
+
}
430
+
431
+
if (!n_range)
432
+
return 0;
433
+
434
+
ranges = kcalloc(n_range,
435
+
(OF_PCI_ADDRESS_CELLS + OF_PCI_SIZE_CELLS +
436
+
n_addr_cells) * sizeof(*ranges),
437
+
GFP_KERNEL);
438
+
if (!ranges)
439
+
return -ENOMEM;
440
+
441
+
resource_list_for_each_entry(window, &bridge->windows) {
442
+
res = window->res;
443
+
if (!of_pci_is_range_resource(res, &flags))
444
+
continue;
445
+
446
+
/* PCI bus address */
447
+
val64 = res->start;
448
+
of_pci_set_address(NULL, &ranges[ranges_sz],
449
+
val64 - window->offset, 0, flags, false);
450
+
ranges_sz += OF_PCI_ADDRESS_CELLS;
451
+
452
+
/* Host bus address */
453
+
if (n_addr_cells == 2)
454
+
ranges[ranges_sz++] = upper_32_bits(val64);
455
+
ranges[ranges_sz++] = lower_32_bits(val64);
456
+
457
+
/* Size */
458
+
val64 = resource_size(res);
459
+
ranges[ranges_sz] = upper_32_bits(val64);
460
+
ranges[ranges_sz + 1] = lower_32_bits(val64);
461
+
ranges_sz += OF_PCI_SIZE_CELLS;
462
+
}
463
+
464
+
ret = of_changeset_add_prop_u32_array(ocs, np, "ranges", ranges,
465
+
ranges_sz);
466
+
kfree(ranges);
467
+
return ret;
468
+
}
469
+
470
+
int of_pci_add_host_bridge_properties(struct pci_host_bridge *bridge,
471
+
struct of_changeset *ocs,
472
+
struct device_node *np)
473
+
{
474
+
int ret;
475
+
476
+
ret = of_changeset_add_prop_string(ocs, np, "device_type", "pci");
477
+
if (ret)
478
+
return ret;
479
+
480
+
ret = of_changeset_add_prop_u32(ocs, np, "#address-cells",
481
+
OF_PCI_ADDRESS_CELLS);
482
+
if (ret)
483
+
return ret;
484
+
485
+
ret = of_changeset_add_prop_u32(ocs, np, "#size-cells",
486
+
OF_PCI_SIZE_CELLS);
487
+
if (ret)
488
+
return ret;
489
+
490
+
ret = of_pci_host_bridge_prop_ranges(bridge, ocs, np);
392
491
if (ret)
393
492
return ret;
394
493
+9
-2
drivers/pci/pci-sysfs.c
+9
-2
drivers/pci/pci-sysfs.c
···
1257
1257
int i;
1258
1258
int retval;
1259
1259
1260
+
/* Skip devices with non-mappable BARs */
1261
+
if (pdev->non_mappable_bars)
1262
+
return 0;
1263
+
1260
1264
/* Expose the PCI resources from this device as files */
1261
1265
for (i = 0; i < PCI_STD_NUM_BARS; i++) {
1262
1266
···
1560
1556
return -EINVAL;
1561
1557
1562
1558
device_lock(dev);
1563
-
if (dev->driver) {
1559
+
if (dev->driver || pci_num_vf(pdev)) {
1564
1560
ret = -EBUSY;
1565
1561
goto unlock;
1566
1562
}
···
1582
1578
1583
1579
pci_remove_resource_files(pdev);
1584
1580
1585
-
for (i = 0; i < PCI_STD_NUM_BARS; i++) {
1581
+
for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) {
1586
1582
if (pci_resource_len(pdev, i) &&
1587
1583
pci_resource_flags(pdev, i) == flags)
1588
1584
pci_release_resource(pdev, i);
···
1808
1804
#endif
1809
1805
#ifdef CONFIG_PCIEASPM
1810
1806
&aspm_ctrl_attr_group,
1807
+
#endif
1808
+
#ifdef CONFIG_PCI_DOE
1809
+
&pci_doe_sysfs_group,
1811
1810
#endif
1812
1811
NULL,
1813
1812
};
+52
-20
drivers/pci/pci.c
+52
-20
drivers/pci/pci.c
···
954
954
};
955
955
956
956
static void __pci_config_acs(struct pci_dev *dev, struct pci_acs *caps,
957
-
const char *p, u16 mask, u16 flags)
957
+
const char *p, const u16 acs_mask, const u16 acs_flags)
958
958
{
959
+
u16 flags = acs_flags;
960
+
u16 mask = acs_mask;
959
961
char *delimit;
960
962
int ret = 0;
961
963
···
965
963
return;
966
964
967
965
while (*p) {
968
-
if (!mask) {
966
+
if (!acs_mask) {
969
967
/* Check for ACS flags */
970
968
delimit = strstr(p, "@");
971
969
if (delimit) {
···
973
971
u32 shift = 0;
974
972
975
973
end = delimit - p - 1;
974
+
mask = 0;
975
+
flags = 0;
976
976
977
977
while (end > -1) {
978
978
if (*(p + end) == '0') {
···
1031
1027
1032
1028
pci_dbg(dev, "ACS mask = %#06x\n", mask);
1033
1029
pci_dbg(dev, "ACS flags = %#06x\n", flags);
1030
+
pci_dbg(dev, "ACS control = %#06x\n", caps->ctrl);
1031
+
pci_dbg(dev, "ACS fw_ctrl = %#06x\n", caps->fw_ctrl);
1034
1032
1035
-
/* If mask is 0 then we copy the bit from the firmware setting. */
1036
-
caps->ctrl = (caps->ctrl & ~mask) | (caps->fw_ctrl & mask);
1037
-
caps->ctrl |= flags;
1033
+
/*
1034
+
* For mask bits that are 0, copy them from the firmware setting
1035
+
* and apply flags for all the mask bits that are 1.
1036
+
*/
1037
+
caps->ctrl = (caps->fw_ctrl & ~mask) | (flags & mask);
1038
1038
1039
1039
pci_info(dev, "Configured ACS to %#06x\n", caps->ctrl);
1040
1040
}
···
1879
1871
unsigned int pos, nbars, i;
1880
1872
u32 ctrl;
1881
1873
1882
-
pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_REBAR);
1874
+
pos = pdev->rebar_cap;
1883
1875
if (!pos)
1884
1876
return;
1885
1877
···
1892
1884
1893
1885
pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
1894
1886
bar_idx = ctrl & PCI_REBAR_CTRL_BAR_IDX;
1895
-
res = pdev->resource + bar_idx;
1887
+
res = pci_resource_n(pdev, bar_idx);
1896
1888
size = pci_rebar_bytes_to_size(resource_size(res));
1897
1889
ctrl &= ~PCI_REBAR_CTRL_BAR_SIZE;
1898
1890
ctrl |= FIELD_PREP(PCI_REBAR_CTRL_BAR_SIZE, size);
···
3031
3023
* @bridge: Bridge to check
3032
3024
*
3033
3025
* This function checks if it is possible to move the bridge to D3.
3034
-
* Currently we only allow D3 for recent enough PCIe ports and Thunderbolt.
3026
+
* Currently we only allow D3 for some PCIe ports and for Thunderbolt.
3035
3027
*/
3036
3028
bool pci_bridge_d3_possible(struct pci_dev *bridge)
3037
3029
{
···
3075
3067
return false;
3076
3068
3077
3069
/*
3078
-
* It should be safe to put PCIe ports from 2015 or newer
3079
-
* to D3.
3070
+
* Out of caution, we only allow PCIe ports from 2015 or newer
3071
+
* into D3 on x86.
3080
3072
*/
3081
-
if (dmi_get_bios_year() >= 2015)
3073
+
if (!IS_ENABLED(CONFIG_X86) || dmi_get_bios_year() >= 2015)
3082
3074
return true;
3083
3075
break;
3084
3076
}
···
3726
3718
pci_enable_acs(dev);
3727
3719
}
3728
3720
3721
+
void pci_rebar_init(struct pci_dev *pdev)
3722
+
{
3723
+
pdev->rebar_cap = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_REBAR);
3724
+
}
3725
+
3729
3726
/**
3730
3727
* pci_rebar_find_pos - find position of resize ctrl reg for BAR
3731
3728
* @pdev: PCI device
···
3745
3732
unsigned int pos, nbars, i;
3746
3733
u32 ctrl;
3747
3734
3748
-
pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_REBAR);
3735
+
pos = pdev->rebar_cap;
3749
3736
if (!pos)
3750
3737
return -ENOTSUPP;
3751
3738
···
3770
3757
* @bar: BAR to query
3771
3758
*
3772
3759
* Get the possible sizes of a resizable BAR as bitmask defined in the spec
3773
-
* (bit 0=1MB, bit 19=512GB). Returns 0 if BAR isn't resizable.
3760
+
* (bit 0=1MB, bit 31=128TB). Returns 0 if BAR isn't resizable.
3774
3761
*/
3775
3762
u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar)
3776
3763
{
···
3818
3805
* pci_rebar_set_size - set a new size for a BAR
3819
3806
* @pdev: PCI device
3820
3807
* @bar: BAR to set size to
3821
-
* @size: new size as defined in the spec (0=1MB, 19=512GB)
3808
+
* @size: new size as defined in the spec (0=1MB, 31=128TB)
3822
3809
*
3823
3810
* Set the new size of a BAR as defined in the spec.
3824
3811
* Returns zero if resizing was successful, error code otherwise.
···
3934
3921
*/
3935
3922
void pci_release_region(struct pci_dev *pdev, int bar)
3936
3923
{
3924
+
if (!pci_bar_index_is_valid(bar))
3925
+
return;
3926
+
3937
3927
/*
3938
3928
* This is done for backwards compatibility, because the old PCI devres
3939
3929
* API had a mode in which the function became managed if it had been
···
3981
3965
static int __pci_request_region(struct pci_dev *pdev, int bar,
3982
3966
const char *name, int exclusive)
3983
3967
{
3968
+
if (!pci_bar_index_is_valid(bar))
3969
+
return -EINVAL;
3970
+
3984
3971
if (pci_is_managed(pdev)) {
3985
3972
if (exclusive == IORESOURCE_EXCLUSIVE)
3986
3973
return pcim_request_region_exclusive(pdev, bar, name);
···
4785
4766
4786
4767
/*
4787
4768
* PCIe r4.0 sec 6.6.1, a component must enter LTSSM Detect within 20ms,
4788
-
* after which we should expect an link active if the reset was
4769
+
* after which we should expect the link to be active if the reset was
4789
4770
* successful. If so, software must wait a minimum 100ms before sending
4790
4771
* configuration requests to devices downstream this port.
4791
4772
*
···
5249
5230
int __pci_reset_function_locked(struct pci_dev *dev)
5250
5231
{
5251
5232
int i, m, rc;
5233
+
const struct pci_reset_fn_method *method;
5252
5234
5253
5235
might_sleep();
5254
5236
···
5266
5246
if (!m)
5267
5247
return -ENOTTY;
5268
5248
5269
-
rc = pci_reset_fn_methods[m].reset_fn(dev, PCI_RESET_DO_RESET);
5249
+
method = &pci_reset_fn_methods[m];
5250
+
pci_dbg(dev, "reset via %s\n", method->name);
5251
+
rc = method->reset_fn(dev, PCI_RESET_DO_RESET);
5270
5252
if (!rc)
5271
5253
return 0;
5254
+
5255
+
pci_dbg(dev, "%s failed with %d\n", method->name, rc);
5272
5256
if (rc != -ENOTTY)
5273
5257
return rc;
5274
5258
}
···
5429
5405
return false;
5430
5406
5431
5407
list_for_each_entry(dev, &bus->devices, bus_list) {
5408
+
if (!pci_reset_supported(dev))
5409
+
return false;
5432
5410
if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET ||
5433
5411
(dev->subordinate && !pci_bus_resettable(dev->subordinate)))
5434
5412
return false;
···
5507
5481
list_for_each_entry(dev, &slot->bus->devices, bus_list) {
5508
5482
if (!dev->slot || dev->slot != slot)
5509
5483
continue;
5484
+
if (!pci_reset_supported(dev))
5485
+
return false;
5510
5486
if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET ||
5511
5487
(dev->subordinate && !pci_bus_resettable(dev->subordinate)))
5512
5488
return false;
···
6218
6190
enum pci_bus_speed speed, speed_cap;
6219
6191
struct pci_dev *limiting_dev = NULL;
6220
6192
u32 bw_avail, bw_cap;
6193
+
char *flit_mode = "";
6221
6194
6222
6195
bw_cap = pcie_bandwidth_capable(dev, &speed_cap, &width_cap);
6223
6196
bw_avail = pcie_bandwidth_available(dev, &limiting_dev, &speed, &width);
6224
6197
6198
+
if (dev->bus && dev->bus->flit_mode)
6199
+
flit_mode = ", in Flit mode";
6200
+
6225
6201
if (bw_avail >= bw_cap && verbose)
6226
-
pci_info(dev, "%u.%03u Gb/s available PCIe bandwidth (%s x%d link)\n",
6202
+
pci_info(dev, "%u.%03u Gb/s available PCIe bandwidth (%s x%d link)%s\n",
6227
6203
bw_cap / 1000, bw_cap % 1000,
6228
-
pci_speed_string(speed_cap), width_cap);
6204
+
pci_speed_string(speed_cap), width_cap, flit_mode);
6229
6205
else if (bw_avail < bw_cap)
6230
-
pci_info(dev, "%u.%03u Gb/s available PCIe bandwidth, limited by %s x%d link at %s (capable of %u.%03u Gb/s with %s x%d link)\n",
6206
+
pci_info(dev, "%u.%03u Gb/s available PCIe bandwidth, limited by %s x%d link at %s (capable of %u.%03u Gb/s with %s x%d link)%s\n",
6231
6207
bw_avail / 1000, bw_avail % 1000,
6232
6208
pci_speed_string(speed), width,
6233
6209
limiting_dev ? pci_name(limiting_dev) : "<unknown>",
6234
6210
bw_cap / 1000, bw_cap % 1000,
6235
-
pci_speed_string(speed_cap), width_cap);
6211
+
pci_speed_string(speed_cap), width_cap, flit_mode);
6236
6212
}
6237
6213
6238
6214
/**
+82
-7
drivers/pci/pci.h
+82
-7
drivers/pci/pci.h
···
167
167
pm_wakeup_event(&dev->dev, 100);
168
168
}
169
169
170
+
/**
171
+
* pci_bar_index_is_valid - Check whether a BAR index is within valid range
172
+
* @bar: BAR index
173
+
*
174
+
* Protects against overflowing &struct pci_dev.resource array.
175
+
*
176
+
* Return: true for valid index, false otherwise.
177
+
*/
178
+
static inline bool pci_bar_index_is_valid(int bar)
179
+
{
180
+
if (bar >= 0 && bar < PCI_NUM_RESOURCES)
181
+
return true;
182
+
183
+
return false;
184
+
}
185
+
170
186
static inline bool pci_has_subordinate(struct pci_dev *pci_dev)
171
187
{
172
188
return !!(pci_dev->subordinate);
···
269
253
extern const struct attribute_group *pci_dev_attr_groups[];
270
254
extern const struct attribute_group *pcibus_groups[];
271
255
extern const struct attribute_group *pci_bus_groups[];
256
+
extern const struct attribute_group pci_doe_sysfs_group;
272
257
#else
273
258
static inline int pci_create_sysfs_dev_files(struct pci_dev *pdev) { return 0; }
274
259
static inline void pci_remove_sysfs_dev_files(struct pci_dev *pdev) { }
···
283
266
extern unsigned long pci_hotplug_mmio_size;
284
267
extern unsigned long pci_hotplug_mmio_pref_size;
285
268
extern unsigned long pci_hotplug_bus_size;
269
+
extern unsigned long pci_cardbus_io_size;
270
+
extern unsigned long pci_cardbus_mem_size;
286
271
287
272
/**
288
273
* pci_match_one_device - Tell if a PCI device structure has a matching
···
328
309
struct device *pci_get_host_bridge_device(struct pci_dev *dev);
329
310
void pci_put_host_bridge_device(struct device *dev);
330
311
312
+
unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge);
313
+
int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long type);
314
+
int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align);
315
+
331
316
int pci_configure_extended_tags(struct pci_dev *dev, void *ign);
332
317
bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl,
333
318
int rrs_timeout);
···
356
333
void *userdata);
357
334
358
335
const char *pci_resource_name(struct pci_dev *dev, unsigned int i);
336
+
bool pci_resource_is_optional(const struct pci_dev *dev, int resno);
337
+
338
+
/**
339
+
* pci_resource_num - Reverse lookup resource number from device resources
340
+
* @dev: PCI device
341
+
* @res: Resource to lookup index for (MUST be a @dev's resource)
342
+
*
343
+
* Perform reverse lookup to determine the resource number for @res within
344
+
* @dev resource array. NOTE: The caller is responsible for ensuring @res is
345
+
* among @dev's resources!
346
+
*
347
+
* Returns: resource number.
348
+
*/
349
+
static inline int pci_resource_num(const struct pci_dev *dev,
350
+
const struct resource *res)
351
+
{
352
+
int resno = res - &dev->resource[0];
353
+
354
+
/* Passing a resource that is not among dev's resources? */
355
+
WARN_ON_ONCE(resno >= PCI_NUM_RESOURCES);
356
+
357
+
return resno;
358
+
}
359
359
360
360
void pci_reassigndev_resource_alignment(struct pci_dev *dev);
361
361
void pci_disable_bridge_window(struct pci_dev *dev);
···
452
406
void __pcie_print_link_status(struct pci_dev *dev, bool verbose);
453
407
void pcie_report_downtraining(struct pci_dev *dev);
454
408
455
-
static inline void __pcie_update_link_speed(struct pci_bus *bus, u16 linksta)
409
+
static inline void __pcie_update_link_speed(struct pci_bus *bus, u16 linksta, u16 linksta2)
456
410
{
457
411
bus->cur_bus_speed = pcie_link_speed[linksta & PCI_EXP_LNKSTA_CLS];
412
+
bus->flit_mode = (linksta2 & PCI_EXP_LNKSTA2_FLIT) ? 1 : 0;
458
413
}
459
414
void pcie_update_link_speed(struct pci_bus *bus);
460
415
···
501
454
#else
502
455
static inline void pci_npem_create(struct pci_dev *dev) { }
503
456
static inline void pci_npem_remove(struct pci_dev *dev) { }
457
+
#endif
458
+
459
+
#if defined(CONFIG_PCI_DOE) && defined(CONFIG_SYSFS)
460
+
void pci_doe_sysfs_init(struct pci_dev *pci_dev);
461
+
void pci_doe_sysfs_teardown(struct pci_dev *pdev);
462
+
#else
463
+
static inline void pci_doe_sysfs_init(struct pci_dev *pdev) { }
464
+
static inline void pci_doe_sysfs_teardown(struct pci_dev *pdev) { }
504
465
#endif
505
466
506
467
/**
···
608
553
void aer_print_error(struct pci_dev *dev, struct aer_err_info *info);
609
554
610
555
int pcie_read_tlp_log(struct pci_dev *dev, int where, int where2,
611
-
unsigned int tlp_len, struct pcie_tlp_log *log);
556
+
unsigned int tlp_len, bool flit,
557
+
struct pcie_tlp_log *log);
612
558
unsigned int aer_tlp_log_len(struct pci_dev *dev, u32 aercc);
613
559
void pcie_print_tlp_log(const struct pci_dev *dev,
614
560
const struct pcie_tlp_log *log, const char *pfx);
···
688
632
resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, int resno);
689
633
void pci_restore_iov_state(struct pci_dev *dev);
690
634
int pci_iov_bus_range(struct pci_bus *bus);
635
+
static inline bool pci_resource_is_iov(int resno)
636
+
{
637
+
return resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END;
638
+
}
691
639
extern const struct attribute_group sriov_pf_dev_attr_group;
692
640
extern const struct attribute_group sriov_vf_dev_attr_group;
693
641
#else
···
701
641
}
702
642
static inline void pci_iov_release(struct pci_dev *dev) { }
703
643
static inline void pci_iov_remove(struct pci_dev *dev) { }
644
+
static inline void pci_iov_update_resource(struct pci_dev *dev, int resno) { }
645
+
static inline resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev,
646
+
int resno)
647
+
{
648
+
return 0;
649
+
}
704
650
static inline void pci_restore_iov_state(struct pci_dev *dev) { }
705
651
static inline int pci_iov_bus_range(struct pci_bus *bus)
706
652
{
707
653
return 0;
708
654
}
709
-
655
+
static inline bool pci_resource_is_iov(int resno)
656
+
{
657
+
return false;
658
+
}
710
659
#endif /* CONFIG_PCI_IOV */
711
660
712
661
#ifdef CONFIG_PCIE_TPH
···
749
680
static inline resource_size_t pci_resource_alignment(struct pci_dev *dev,
750
681
struct resource *res)
751
682
{
752
-
#ifdef CONFIG_PCI_IOV
753
-
int resno = res - dev->resource;
683
+
int resno = pci_resource_num(dev, res);
754
684
755
-
if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END)
685
+
if (pci_resource_is_iov(resno))
756
686
return pci_sriov_resource_alignment(dev, resno);
757
-
#endif
758
687
if (dev->class >> 8 == PCI_CLASS_BRIDGE_CARDBUS)
759
688
return pci_cardbus_resource_alignment(res);
760
689
return resource_alignment(res);
···
866
799
}
867
800
#endif
868
801
802
+
void pci_rebar_init(struct pci_dev *pdev);
869
803
int pci_rebar_get_current_size(struct pci_dev *pdev, int bar);
870
804
int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size);
871
805
static inline u64 pci_rebar_size_to_bytes(int size)
···
944
876
void of_pci_remove_node(struct pci_dev *pdev);
945
877
int of_pci_add_properties(struct pci_dev *pdev, struct of_changeset *ocs,
946
878
struct device_node *np);
879
+
void of_pci_make_host_bridge_node(struct pci_host_bridge *bridge);
880
+
void of_pci_remove_host_bridge_node(struct pci_host_bridge *bridge);
881
+
int of_pci_add_host_bridge_properties(struct pci_host_bridge *bridge,
882
+
struct of_changeset *ocs,
883
+
struct device_node *np);
947
884
#else
948
885
static inline void of_pci_make_dev_node(struct pci_dev *pdev) { }
949
886
static inline void of_pci_remove_node(struct pci_dev *pdev) { }
887
+
static inline void of_pci_make_host_bridge_node(struct pci_host_bridge *bridge) { }
888
+
static inline void of_pci_remove_host_bridge_node(struct pci_host_bridge *bridge) { }
950
889
#endif
951
890
952
891
#ifdef CONFIG_PCIEAER
+42
-37
drivers/pci/pcie/aer.c
+42
-37
drivers/pci/pcie/aer.c
···
2
2
/*
3
3
* Implement the AER root port service driver. The driver registers an IRQ
4
4
* handler. When a root port triggers an AER interrupt, the IRQ handler
5
-
* collects root port status and schedules work.
5
+
* collects Root Port status and schedules work.
6
6
*
7
7
* Copyright (C) 2006 Intel Corp.
8
8
* Tom Long Nguyen (tom.l.nguyen@intel.com)
···
17
17
18
18
#include <linux/bitops.h>
19
19
#include <linux/cper.h>
20
+
#include <linux/dev_printk.h>
20
21
#include <linux/pci.h>
21
22
#include <linux/pci-acpi.h>
22
23
#include <linux/sched.h>
···
35
34
36
35
#include "../pci.h"
37
36
#include "portdrv.h"
37
+
38
+
#define aer_printk(level, pdev, fmt, arg...) \
39
+
dev_printk(level, &(pdev)->dev, fmt, ##arg)
38
40
39
41
#define AER_ERROR_SOURCES_MAX 128
40
42
···
60
56
/*
61
57
* Fields for all AER capable devices. They indicate the errors
62
58
* "as seen by this device". Note that this may mean that if an
63
-
* end point is causing problems, the AER counters may increment
64
-
* at its link partner (e.g. root port) because the errors will be
65
-
* "seen" by the link partner and not the problematic end point
59
+
* Endpoint is causing problems, the AER counters may increment
60
+
* at its link partner (e.g. Root Port) because the errors will be
61
+
* "seen" by the link partner and not the problematic Endpoint
66
62
* itself (which may report all counters as 0 as it never saw any
67
63
* problems).
68
64
*/
···
80
76
u64 dev_total_nonfatal_errs;
81
77
82
78
/*
83
-
* Fields for Root ports & root complex event collectors only, these
79
+
* Fields for Root Ports & Root Complex Event Collectors only; these
84
80
* indicate the total number of ERR_COR, ERR_FATAL, and ERR_NONFATAL
85
-
* messages received by the root port / event collector, INCLUDING the
86
-
* ones that are generated internally (by the rootport itself)
81
+
* messages received by the Root Port / Event Collector, INCLUDING the
82
+
* ones that are generated internally (by the Root Port itself)
87
83
*/
88
84
u64 rootport_total_cor_errs;
89
85
u64 rootport_total_fatal_errs;
···
142
138
* enable_ecrc_checking - enable PCIe ECRC checking for a device
143
139
* @dev: the PCI device
144
140
*
145
-
* Returns 0 on success, or negative on failure.
141
+
* Return: 0 on success, or negative on failure.
146
142
*/
147
143
static int enable_ecrc_checking(struct pci_dev *dev)
148
144
{
···
163
159
}
164
160
165
161
/**
166
-
* disable_ecrc_checking - disables PCIe ECRC checking for a device
162
+
* disable_ecrc_checking - disable PCIe ECRC checking for a device
167
163
* @dev: the PCI device
168
164
*
169
-
* Returns 0 on success, or negative on failure.
165
+
* Return: 0 on success, or negative on failure.
170
166
*/
171
167
static int disable_ecrc_checking(struct pci_dev *dev)
172
168
{
···
287
283
* pci_aer_raw_clear_status - Clear AER error registers.
288
284
* @dev: the PCI device
289
285
*
290
-
* Clearing AER error status registers unconditionally, regardless of
286
+
* Clear AER error status registers unconditionally, regardless of
291
287
* whether they're owned by firmware or the OS.
292
288
*
293
-
* Returns 0 on success, or negative on failure.
289
+
* Return: 0 on success, or negative on failure.
294
290
*/
295
291
int pci_aer_raw_clear_status(struct pci_dev *dev)
296
292
{
···
382
378
/*
383
379
* We save/restore PCI_ERR_UNCOR_MASK, PCI_ERR_UNCOR_SEVER,
384
380
* PCI_ERR_COR_MASK, and PCI_ERR_CAP. Root and Root Complex Event
385
-
* Collectors also implement PCI_ERR_ROOT_COMMAND (PCIe r5.0, sec
386
-
* 7.8.4).
381
+
* Collectors also implement PCI_ERR_ROOT_COMMAND (PCIe r6.0, sec
382
+
* 7.8.4.9).
387
383
*/
388
384
n = pcie_cap_has_rtctl(dev) ? 5 : 4;
389
385
pci_add_ext_cap_save_buffer(dev, PCI_EXT_CAP_ID_ERR, sizeof(u32) * n);
···
690
686
if (!errmsg)
691
687
errmsg = "Unknown Error Bit";
692
688
693
-
pci_printk(level, dev, " [%2d] %-22s%s\n", i, errmsg,
689
+
aer_printk(level, dev, " [%2d] %-22s%s\n", i, errmsg,
694
690
info->first_error == i ? " (First)" : "");
695
691
}
696
692
pci_dev_aer_stats_incr(dev, info);
···
713
709
714
710
level = (info->severity == AER_CORRECTABLE) ? KERN_WARNING : KERN_ERR;
715
711
716
-
pci_printk(level, dev, "PCIe Bus Error: severity=%s, type=%s, (%s)\n",
712
+
aer_printk(level, dev, "PCIe Bus Error: severity=%s, type=%s, (%s)\n",
717
713
aer_error_severity_string[info->severity],
718
714
aer_error_layer[layer], aer_agent_string[agent]);
719
715
720
-
pci_printk(level, dev, " device [%04x:%04x] error status/mask=%08x/%08x\n",
716
+
aer_printk(level, dev, " device [%04x:%04x] error status/mask=%08x/%08x\n",
721
717
dev->vendor, dev->device, info->status, info->mask);
722
718
723
719
__aer_print_error(dev, info);
···
829
825
u16 reg16;
830
826
831
827
/*
832
-
* When bus id is equal to 0, it might be a bad id
833
-
* reported by root port.
828
+
* When bus ID is equal to 0, it might be a bad ID
829
+
* reported by Root Port.
834
830
*/
835
831
if ((PCI_BUS_NUM(e_info->id) != 0) &&
836
832
!(dev->bus->bus_flags & PCI_BUS_FLAGS_NO_AERSID)) {
···
838
834
if (e_info->id == pci_dev_id(dev))
839
835
return true;
840
836
841
-
/* Continue id comparing if there is no multiple error */
837
+
/* Continue ID comparing if there is no multiple error */
842
838
if (!e_info->multi_error_valid)
843
839
return false;
844
840
}
845
841
846
842
/*
847
843
* When either
848
-
* 1) bus id is equal to 0. Some ports might lose the bus
849
-
* id of error source id;
844
+
* 1) bus ID is equal to 0. Some ports might lose the bus
845
+
* ID of error source id;
850
846
* 2) bus flag PCI_BUS_FLAGS_NO_AERSID is set
851
847
* 3) There are multiple errors and prior ID comparing fails;
852
848
* We check AER status registers to find possible reporter.
···
898
894
/**
899
895
* find_source_device - search through device hierarchy for source device
900
896
* @parent: pointer to Root Port pci_dev data structure
901
-
* @e_info: including detailed error information such like id
897
+
* @e_info: including detailed error information such as ID
902
898
*
903
-
* Return true if found.
899
+
* Return: true if found.
904
900
*
905
901
* Invoked by DPC when error is detected at the Root Port.
906
902
* Caller of this function must set id, severity, and multi_error_valid of
···
942
938
943
939
/**
944
940
* pci_aer_unmask_internal_errors - unmask internal errors
945
-
* @dev: pointer to the pcie_dev data structure
941
+
* @dev: pointer to the pci_dev data structure
946
942
*
947
-
* Unmasks internal errors in the Uncorrectable and Correctable Error
943
+
* Unmask internal errors in the Uncorrectable and Correctable Error
948
944
* Mask registers.
949
945
*
950
946
* Note: AER must be enabled and supported by the device which must be
···
1007
1003
if (!is_cxl_mem_dev(dev) || !cxl_error_is_native(dev))
1008
1004
return 0;
1009
1005
1010
-
/* protect dev->driver */
1006
+
/* Protect dev->driver */
1011
1007
device_lock(&dev->dev);
1012
1008
1013
1009
err_handler = dev->driver ? dev->driver->err_handler : NULL;
···
1199
1195
1200
1196
/**
1201
1197
* aer_get_device_error_info - read error status from dev and store it to info
1202
-
* @dev: pointer to the device expected to have a error record
1198
+
* @dev: pointer to the device expected to have an error record
1203
1199
* @info: pointer to structure to store the error record
1204
1200
*
1205
-
* Return 1 on success, 0 on error.
1201
+
* Return: 1 on success, 0 on error.
1206
1202
*
1207
1203
* Note that @info is reused among all error devices. Clear fields properly.
1208
1204
*/
···
1249
1245
pcie_read_tlp_log(dev, aer + PCI_ERR_HEADER_LOG,
1250
1246
aer + PCI_ERR_PREFIX_LOG,
1251
1247
aer_tlp_log_len(dev, aercc),
1248
+
aercc & PCI_ERR_CAP_TLP_LOG_FLIT,
1252
1249
&info->tlp);
1253
1250
}
1254
1251
}
···
1261
1256
{
1262
1257
int i;
1263
1258
1264
-
/* Report all before handle them, not to lost records by reset etc. */
1259
+
/* Report all before handling them, to not lose records by reset etc. */
1265
1260
for (i = 0; i < e_info->error_dev_num && e_info->dev[i]; i++) {
1266
1261
if (aer_get_device_error_info(e_info->dev[i], e_info))
1267
1262
aer_print_error(e_info->dev[i], e_info);
···
1273
1268
}
1274
1269
1275
1270
/**
1276
-
* aer_isr_one_error - consume an error detected by root port
1277
-
* @rpc: pointer to the root port which holds an error
1271
+
* aer_isr_one_error - consume an error detected by Root Port
1272
+
* @rpc: pointer to the Root Port which holds an error
1278
1273
* @e_src: pointer to an error source
1279
1274
*/
1280
1275
static void aer_isr_one_error(struct aer_rpc *rpc,
···
1324
1319
}
1325
1320
1326
1321
/**
1327
-
* aer_isr - consume errors detected by root port
1322
+
* aer_isr - consume errors detected by Root Port
1328
1323
* @irq: IRQ assigned to Root Port
1329
1324
* @context: pointer to Root Port data structure
1330
1325
*
1331
-
* Invoked, as DPC, when root port records new detected error
1326
+
* Invoked, as DPC, when Root Port records new detected error
1332
1327
*/
1333
1328
static irqreturn_t aer_isr(int irq, void *context)
1334
1329
{
···
1388
1383
int aer = pdev->aer_cap;
1389
1384
u32 reg32;
1390
1385
1391
-
/* Disable Root's interrupt in response to error messages */
1386
+
/* Disable Root Port's interrupt in response to error messages */
1392
1387
pci_read_config_dword(pdev, aer + PCI_ERR_ROOT_COMMAND, ®32);
1393
1388
reg32 &= ~ROOT_PORT_INTR_ON_MESG_MASK;
1394
1389
pci_write_config_dword(pdev, aer + PCI_ERR_ROOT_COMMAND, reg32);
···
1588
1583
};
1589
1584
1590
1585
/**
1591
-
* pcie_aer_init - register AER root service driver
1586
+
* pcie_aer_init - register AER service driver
1592
1587
*
1593
-
* Invoked when AER root service driver is loaded.
1588
+
* Invoked when AER service driver is loaded.
1594
1589
*/
1595
1590
int __init pcie_aer_init(void)
1596
1591
{
+9
-8
drivers/pci/pcie/aspm.c
+9
-8
drivers/pci/pcie/aspm.c
···
1270
1270
parent_link = link->parent;
1271
1271
1272
1272
/*
1273
-
* link->downstream is a pointer to the pci_dev of function 0. If
1274
-
* we remove that function, the pci_dev is about to be deallocated,
1275
-
* so we can't use link->downstream again. Free the link state to
1276
-
* avoid this.
1273
+
* Free the parent link state, no later than function 0 (i.e.
1274
+
* link->downstream) being removed.
1277
1275
*
1278
-
* If we're removing a non-0 function, it's possible we could
1279
-
* retain the link state, but PCIe r6.0, sec 7.5.3.7, recommends
1280
-
* programming the same ASPM Control value for all functions of
1281
-
* multi-function devices, so disable ASPM for all of them.
1276
+
* Do not free the link state any earlier. If function 0 is a
1277
+
* switch upstream port, this link state is parent_link to all
1278
+
* subordinate ones.
1282
1279
*/
1280
+
if (pdev != link->downstream)
1281
+
goto out;
1282
+
1283
1283
pcie_config_aspm_link(link, 0);
1284
1284
list_del(&link->sibling);
1285
1285
free_link_state(link);
···
1290
1290
pcie_config_aspm_path(parent_link);
1291
1291
}
1292
1292
1293
+
out:
1293
1294
mutex_unlock(&aspm_lock);
1294
1295
up_read(&pci_bus_sem);
1295
1296
}
+5
-1
drivers/pci/pcie/bwctrl.c
+5
-1
drivers/pci/pcie/bwctrl.c
···
113
113
up_read(&pci_bus_sem);
114
114
}
115
115
if (!supported_speeds)
116
-
return PCI_EXP_LNKCAP2_SLS_2_5GB;
116
+
supported_speeds = PCI_EXP_LNKCAP2_SLS_2_5GB;
117
117
118
118
return pcie_supported_speeds2target_speed(supported_speeds & desired_speeds);
119
119
}
···
293
293
{
294
294
struct pci_dev *port = srv->port;
295
295
int ret;
296
+
297
+
/* Can happen if we run out of bus numbers during enumeration. */
298
+
if (!port->subordinate)
299
+
return -ENODEV;
296
300
297
301
struct pcie_bwctrl_data *data = devm_kzalloc(&srv->device,
298
302
sizeof(*data), GFP_KERNEL);
+15
-3
drivers/pci/pcie/dpc.c
+15
-3
drivers/pci/pcie/dpc.c
···
219
219
goto clear_status;
220
220
pcie_read_tlp_log(pdev, cap + PCI_EXP_DPC_RP_PIO_HEADER_LOG,
221
221
cap + PCI_EXP_DPC_RP_PIO_TLPPREFIX_LOG,
222
-
dpc_tlp_log_len(pdev), &tlp_log);
222
+
dpc_tlp_log_len(pdev),
223
+
pdev->subordinate->flit_mode,
224
+
&tlp_log);
223
225
pcie_print_tlp_log(pdev, &tlp_log, dev_fmt(""));
224
226
225
227
if (pdev->dpc_rp_log_size < PCIE_STD_NUM_TLP_HEADERLOG + 1)
···
400
398
401
399
/* Quirks may set dpc_rp_log_size if device or firmware is buggy */
402
400
if (!pdev->dpc_rp_log_size) {
401
+
u16 flags;
402
+
int ret;
403
+
404
+
ret = pcie_capability_read_word(pdev, PCI_EXP_FLAGS, &flags);
405
+
if (ret)
406
+
return;
407
+
403
408
pdev->dpc_rp_log_size =
404
409
FIELD_GET(PCI_EXP_DPC_RP_PIO_LOG_SIZE, cap);
410
+
if (FIELD_GET(PCI_EXP_FLAGS_FLIT, flags))
411
+
pdev->dpc_rp_log_size += FIELD_GET(PCI_EXP_DPC_RP_PIO_LOG_SIZE4,
412
+
cap) << 4;
413
+
405
414
if (pdev->dpc_rp_log_size < PCIE_STD_NUM_TLP_HEADERLOG ||
406
-
pdev->dpc_rp_log_size > PCIE_STD_NUM_TLP_HEADERLOG + 1 +
407
-
PCIE_STD_MAX_TLP_PREFIXLOG) {
415
+
pdev->dpc_rp_log_size > PCIE_STD_MAX_TLP_HEADERLOG + 1) {
408
416
pci_err(pdev, "RP PIO log size %u is invalid\n",
409
417
pdev->dpc_rp_log_size);
410
418
pdev->dpc_rp_log_size = 0;
+5
-3
drivers/pci/pcie/portdrv.c
+5
-3
drivers/pci/pcie/portdrv.c
···
228
228
229
229
/*
230
230
* Disable hot-plug interrupts in case they have been enabled
231
-
* by the BIOS and the hot-plug service driver is not loaded.
231
+
* by the BIOS and the hot-plug service driver won't be loaded
232
+
* to handle them.
232
233
*/
233
-
pcie_capability_clear_word(dev, PCI_EXP_SLTCTL,
234
-
PCI_EXP_SLTCTL_CCIE | PCI_EXP_SLTCTL_HPIE);
234
+
if (!IS_ENABLED(CONFIG_HOTPLUG_PCI_PCIE))
235
+
pcie_capability_clear_word(dev, PCI_EXP_SLTCTL,
236
+
PCI_EXP_SLTCTL_CCIE | PCI_EXP_SLTCTL_HPIE);
235
237
}
236
238
237
239
#ifdef CONFIG_PCIEAER
+38
-18
drivers/pci/pcie/tlp.c
+38
-18
drivers/pci/pcie/tlp.c
···
7
7
8
8
#include <linux/aer.h>
9
9
#include <linux/array_size.h>
10
+
#include <linux/bitfield.h>
10
11
#include <linux/pci.h>
11
12
#include <linux/string.h>
12
13
···
22
21
*/
23
22
unsigned int aer_tlp_log_len(struct pci_dev *dev, u32 aercc)
24
23
{
24
+
if (aercc & PCI_ERR_CAP_TLP_LOG_FLIT)
25
+
return FIELD_GET(PCI_ERR_CAP_TLP_LOG_SIZE, aercc);
26
+
25
27
return PCIE_STD_NUM_TLP_HEADERLOG +
26
28
((aercc & PCI_ERR_CAP_PREFIX_LOG_PRESENT) ?
27
29
dev->eetlp_prefix_max : 0);
···
53
49
* @where: PCI Config offset of TLP Header Log
54
50
* @where2: PCI Config offset of TLP Prefix Log
55
51
* @tlp_len: TLP Log length (Header Log + TLP Prefix Log in DWORDs)
52
+
* @flit: TLP Logged in Flit mode
56
53
* @log: TLP Log structure to fill
57
54
*
58
55
* Fill @log from TLP Header Log registers, e.g., AER or DPC.
···
61
56
* Return: 0 on success and filled TLP Log structure, <0 on error.
62
57
*/
63
58
int pcie_read_tlp_log(struct pci_dev *dev, int where, int where2,
64
-
unsigned int tlp_len, struct pcie_tlp_log *log)
59
+
unsigned int tlp_len, bool flit, struct pcie_tlp_log *log)
65
60
{
66
61
unsigned int i;
67
62
int off, ret;
68
-
u32 *to;
63
+
64
+
if (tlp_len > ARRAY_SIZE(log->dw))
65
+
tlp_len = ARRAY_SIZE(log->dw);
69
66
70
67
memset(log, 0, sizeof(*log));
71
68
72
69
for (i = 0; i < tlp_len; i++) {
73
-
if (i < PCIE_STD_NUM_TLP_HEADERLOG) {
70
+
if (i < PCIE_STD_NUM_TLP_HEADERLOG)
74
71
off = where + i * 4;
75
-
to = &log->dw[i];
76
-
} else {
72
+
else
77
73
off = where2 + (i - PCIE_STD_NUM_TLP_HEADERLOG) * 4;
78
-
to = &log->prefix[i - PCIE_STD_NUM_TLP_HEADERLOG];
79
-
}
80
74
81
-
ret = pci_read_config_dword(dev, off, to);
75
+
ret = pci_read_config_dword(dev, off, &log->dw[i]);
82
76
if (ret)
83
77
return pcibios_err_to_errno(ret);
84
78
}
79
+
80
+
/*
81
+
* Hard-code non-Flit mode to 4 DWORDs, for now. The exact length
82
+
* can only be known if the TLP is parsed.
83
+
*/
84
+
log->header_len = flit ? tlp_len : 4;
85
+
log->flit = flit;
85
86
86
87
return 0;
87
88
}
···
105
94
void pcie_print_tlp_log(const struct pci_dev *dev,
106
95
const struct pcie_tlp_log *log, const char *pfx)
107
96
{
108
-
char buf[11 * (PCIE_STD_NUM_TLP_HEADERLOG + ARRAY_SIZE(log->prefix)) +
109
-
sizeof(EE_PREFIX_STR)];
97
+
/* EE_PREFIX_STR fits the extended DW space needed for the Flit mode */
98
+
char buf[11 * PCIE_STD_MAX_TLP_HEADERLOG + 1];
110
99
unsigned int i;
111
100
int len;
112
101
113
102
len = scnprintf(buf, sizeof(buf), "%#010x %#010x %#010x %#010x",
114
103
log->dw[0], log->dw[1], log->dw[2], log->dw[3]);
115
104
116
-
if (log->prefix[0])
117
-
len += scnprintf(buf + len, sizeof(buf) - len, EE_PREFIX_STR);
118
-
for (i = 0; i < ARRAY_SIZE(log->prefix); i++) {
119
-
if (!log->prefix[i])
120
-
break;
121
-
len += scnprintf(buf + len, sizeof(buf) - len,
122
-
" %#010x", log->prefix[i]);
105
+
if (log->flit) {
106
+
for (i = PCIE_STD_NUM_TLP_HEADERLOG; i < log->header_len; i++) {
107
+
len += scnprintf(buf + len, sizeof(buf) - len,
108
+
" %#010x", log->dw[i]);
109
+
}
110
+
} else {
111
+
if (log->prefix[0])
112
+
len += scnprintf(buf + len, sizeof(buf) - len,
113
+
EE_PREFIX_STR);
114
+
for (i = 0; i < ARRAY_SIZE(log->prefix); i++) {
115
+
if (!log->prefix[i])
116
+
break;
117
+
len += scnprintf(buf + len, sizeof(buf) - len,
118
+
" %#010x", log->prefix[i]);
119
+
}
123
120
}
124
121
125
-
pci_err(dev, "%sTLP Header: %s\n", pfx, buf);
122
+
pci_err(dev, "%sTLP Header%s: %s\n", pfx,
123
+
log->flit ? " (Flit)" : "", buf);
126
124
}
+67
-11
drivers/pci/probe.c
+67
-11
drivers/pci/probe.c
···
9
9
#include <linux/pci.h>
10
10
#include <linux/msi.h>
11
11
#include <linux/of_pci.h>
12
+
#include <linux/of_platform.h>
13
+
#include <linux/platform_device.h>
12
14
#include <linux/pci_hotplug.h>
13
15
#include <linux/slab.h>
14
16
#include <linux/module.h>
···
791
789
void pcie_update_link_speed(struct pci_bus *bus)
792
790
{
793
791
struct pci_dev *bridge = bus->self;
794
-
u16 linksta;
792
+
u16 linksta, linksta2;
795
793
796
794
pcie_capability_read_word(bridge, PCI_EXP_LNKSTA, &linksta);
797
-
__pcie_update_link_speed(bus, linksta);
795
+
pcie_capability_read_word(bridge, PCI_EXP_LNKSTA2, &linksta2);
796
+
__pcie_update_link_speed(bus, linksta, linksta2);
798
797
}
799
798
EXPORT_SYMBOL_GPL(pcie_update_link_speed);
800
799
···
957
954
resource_size_t offset, next_offset;
958
955
LIST_HEAD(resources);
959
956
struct resource *res, *next_res;
957
+
bool bus_registered = false;
960
958
char addr[64], *fmt;
961
959
const char *name;
962
960
int err;
···
1000
996
/* Temporarily move resources off the list */
1001
997
list_splice_init(&bridge->windows, &resources);
1002
998
err = device_add(&bridge->dev);
1003
-
if (err) {
1004
-
put_device(&bridge->dev);
999
+
if (err)
1005
1000
goto free;
1006
-
}
1001
+
1007
1002
bus->bridge = get_device(&bridge->dev);
1008
1003
device_enable_async_suspend(bus->bridge);
1009
1004
pci_set_bus_of_node(bus);
···
1021
1018
name = dev_name(&bus->dev);
1022
1019
1023
1020
err = device_register(&bus->dev);
1021
+
bus_registered = true;
1024
1022
if (err)
1025
1023
goto unregister;
1026
1024
···
1099
1095
dev_info(&bus->dev, "root bus resource %pR%s\n", res, addr);
1100
1096
}
1101
1097
1098
+
of_pci_make_host_bridge_node(bridge);
1099
+
1102
1100
down_write(&pci_bus_sem);
1103
1101
list_add_tail(&bus->node, &pci_root_buses);
1104
1102
up_write(&pci_bus_sem);
···
1110
1104
unregister:
1111
1105
put_device(&bridge->dev);
1112
1106
device_del(&bridge->dev);
1113
-
1114
1107
free:
1115
1108
#ifdef CONFIG_PCI_DOMAINS_GENERIC
1116
1109
pci_bus_release_domain_nr(parent, bus->domain_nr);
1117
1110
#endif
1118
-
kfree(bus);
1111
+
if (bus_registered)
1112
+
put_device(&bus->dev);
1113
+
else
1114
+
kfree(bus);
1115
+
1119
1116
return err;
1120
1117
}
1121
1118
···
1227
1218
add_dev:
1228
1219
pci_set_bus_msi_domain(child);
1229
1220
ret = device_register(&child->dev);
1230
-
WARN_ON(ret < 0);
1221
+
if (WARN_ON(ret < 0)) {
1222
+
put_device(&child->dev);
1223
+
return NULL;
1224
+
}
1231
1225
1232
1226
pcibios_add_bus(child);
1233
1227
···
1385
1373
pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);
1386
1374
pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
1387
1375
bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);
1388
-
1389
-
pci_enable_rrs_sv(dev);
1390
1376
1391
1377
if ((secondary || subordinate) && !pcibios_assign_all_busses() &&
1392
1378
!is_cardbus && !broken) {
···
1626
1616
pdev->pcie_cap = pos;
1627
1617
pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16);
1628
1618
pdev->pcie_flags_reg = reg16;
1619
+
1620
+
type = pci_pcie_type(pdev);
1621
+
if (type == PCI_EXP_TYPE_ROOT_PORT)
1622
+
pci_enable_rrs_sv(pdev);
1623
+
1629
1624
pci_read_config_dword(pdev, pos + PCI_EXP_DEVCAP, &pdev->devcap);
1630
1625
pdev->pcie_mpss = FIELD_GET(PCI_EXP_DEVCAP_PAYLOAD, pdev->devcap);
1631
1626
···
1647
1632
* correctly so detect impossible configurations here and correct
1648
1633
* the port type accordingly.
1649
1634
*/
1650
-
type = pci_pcie_type(pdev);
1651
1635
if (type == PCI_EXP_TYPE_DOWNSTREAM) {
1652
1636
/*
1653
1637
* If pdev claims to be downstream port but the parent
···
2508
2494
}
2509
2495
EXPORT_SYMBOL(pci_bus_read_dev_vendor_id);
2510
2496
2497
+
static struct platform_device *pci_pwrctrl_create_device(struct pci_bus *bus, int devfn)
2498
+
{
2499
+
struct pci_host_bridge *host = pci_find_host_bridge(bus);
2500
+
struct platform_device *pdev;
2501
+
struct device_node *np;
2502
+
2503
+
np = of_pci_find_child_device(dev_of_node(&bus->dev), devfn);
2504
+
if (!np || of_find_device_by_node(np))
2505
+
return NULL;
2506
+
2507
+
/*
2508
+
* First check whether the pwrctrl device really needs to be created or
2509
+
* not. This is decided based on at least one of the power supplies
2510
+
* being defined in the devicetree node of the device.
2511
+
*/
2512
+
if (!of_pci_supply_present(np)) {
2513
+
pr_debug("PCI/pwrctrl: Skipping OF node: %s\n", np->name);
2514
+
return NULL;
2515
+
}
2516
+
2517
+
/* Now create the pwrctrl device */
2518
+
pdev = of_platform_device_create(np, NULL, &host->dev);
2519
+
if (!pdev) {
2520
+
pr_err("PCI/pwrctrl: Failed to create pwrctrl device for node: %s\n", np->name);
2521
+
return NULL;
2522
+
}
2523
+
2524
+
return pdev;
2525
+
}
2526
+
2511
2527
/*
2512
2528
* Read the config data for a PCI device, sanity-check it,
2513
2529
* and fill in the dev structure.
···
2546
2502
{
2547
2503
struct pci_dev *dev;
2548
2504
u32 l;
2505
+
2506
+
/*
2507
+
* Create pwrctrl device (if required) for the PCI device to handle the
2508
+
* power state. If the pwrctrl device is created, then skip scanning
2509
+
* further as the pwrctrl core will rescan the bus after powering on
2510
+
* the device.
2511
+
*/
2512
+
if (pci_pwrctrl_create_device(bus, devfn))
2513
+
return NULL;
2549
2514
2550
2515
if (!pci_bus_read_dev_vendor_id(bus, devfn, &l, 60*1000))
2551
2516
return NULL;
···
2618
2565
pci_rcec_init(dev); /* Root Complex Event Collector */
2619
2566
pci_doe_init(dev); /* Data Object Exchange */
2620
2567
pci_tph_init(dev); /* TLP Processing Hints */
2568
+
pci_rebar_init(dev); /* Resizable BAR */
2621
2569
2622
2570
pcie_report_downtraining(dev);
2623
2571
pci_init_reset_methods(dev);
···
2716
2662
WARN_ON(ret < 0);
2717
2663
2718
2664
pci_npem_create(dev);
2665
+
2666
+
pci_doe_sysfs_init(dev);
2719
2667
}
2720
2668
2721
2669
struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn)
+4
drivers/pci/proc.c
+4
drivers/pci/proc.c
···
251
251
security_locked_down(LOCKDOWN_PCI_ACCESS))
252
252
return -EPERM;
253
253
254
+
/* Skip devices with non-mappable BARs */
255
+
if (dev->non_mappable_bars)
256
+
return -EINVAL;
257
+
254
258
if (fpriv->mmap_state == pci_mmap_io) {
255
259
if (!arch_can_pci_mmap_io())
256
260
return -EINVAL;
+11
drivers/pci/pwrctrl/Kconfig
+11
drivers/pci/pwrctrl/Kconfig
···
10
10
tristate
11
11
select POWER_SEQUENCING
12
12
select PCI_PWRCTL
13
+
14
+
config PCI_PWRCTL_SLOT
15
+
tristate "PCI Power Control driver for PCI slots"
16
+
select PCI_PWRCTL
17
+
help
18
+
Say Y here to enable the PCI Power Control driver to control the power
19
+
state of PCI slots.
20
+
21
+
This is a generic driver that controls the power state of different
22
+
PCI slots. The voltage regulators powering the rails of the PCI slots
23
+
are expected to be defined in the devicetree node of the PCI bridge.
+3
drivers/pci/pwrctrl/Makefile
+3
drivers/pci/pwrctrl/Makefile
+1
-1
drivers/pci/pwrctrl/core.c
+1
-1
drivers/pci/pwrctrl/core.c
+93
drivers/pci/pwrctrl/slot.c
+93
drivers/pci/pwrctrl/slot.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/*
3
+
* Copyright (C) 2024 Linaro Ltd.
4
+
* Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
5
+
*/
6
+
7
+
#include <linux/device.h>
8
+
#include <linux/mod_devicetable.h>
9
+
#include <linux/module.h>
10
+
#include <linux/pci-pwrctrl.h>
11
+
#include <linux/platform_device.h>
12
+
#include <linux/regulator/consumer.h>
13
+
#include <linux/slab.h>
14
+
15
+
struct pci_pwrctrl_slot_data {
16
+
struct pci_pwrctrl ctx;
17
+
struct regulator_bulk_data *supplies;
18
+
int num_supplies;
19
+
};
20
+
21
+
static void devm_pci_pwrctrl_slot_power_off(void *data)
22
+
{
23
+
struct pci_pwrctrl_slot_data *slot = data;
24
+
25
+
regulator_bulk_disable(slot->num_supplies, slot->supplies);
26
+
regulator_bulk_free(slot->num_supplies, slot->supplies);
27
+
}
28
+
29
+
static int pci_pwrctrl_slot_probe(struct platform_device *pdev)
30
+
{
31
+
struct pci_pwrctrl_slot_data *slot;
32
+
struct device *dev = &pdev->dev;
33
+
int ret;
34
+
35
+
slot = devm_kzalloc(dev, sizeof(*slot), GFP_KERNEL);
36
+
if (!slot)
37
+
return -ENOMEM;
38
+
39
+
ret = of_regulator_bulk_get_all(dev, dev_of_node(dev),
40
+
&slot->supplies);
41
+
if (ret < 0) {
42
+
dev_err_probe(dev, ret, "Failed to get slot regulators\n");
43
+
return ret;
44
+
}
45
+
46
+
slot->num_supplies = ret;
47
+
ret = regulator_bulk_enable(slot->num_supplies, slot->supplies);
48
+
if (ret < 0) {
49
+
dev_err_probe(dev, ret, "Failed to enable slot regulators\n");
50
+
goto err_regulator_free;
51
+
}
52
+
53
+
ret = devm_add_action_or_reset(dev, devm_pci_pwrctrl_slot_power_off,
54
+
slot);
55
+
if (ret)
56
+
goto err_regulator_disable;
57
+
58
+
pci_pwrctrl_init(&slot->ctx, dev);
59
+
60
+
ret = devm_pci_pwrctrl_device_set_ready(dev, &slot->ctx);
61
+
if (ret)
62
+
return dev_err_probe(dev, ret, "Failed to register pwrctrl driver\n");
63
+
64
+
return 0;
65
+
66
+
err_regulator_disable:
67
+
regulator_bulk_disable(slot->num_supplies, slot->supplies);
68
+
err_regulator_free:
69
+
regulator_bulk_free(slot->num_supplies, slot->supplies);
70
+
71
+
return ret;
72
+
}
73
+
74
+
static const struct of_device_id pci_pwrctrl_slot_of_match[] = {
75
+
{
76
+
.compatible = "pciclass,0604",
77
+
},
78
+
{ }
79
+
};
80
+
MODULE_DEVICE_TABLE(of, pci_pwrctrl_slot_of_match);
81
+
82
+
static struct platform_driver pci_pwrctrl_slot_driver = {
83
+
.driver = {
84
+
.name = "pci-pwrctrl-slot",
85
+
.of_match_table = pci_pwrctrl_slot_of_match,
86
+
},
87
+
.probe = pci_pwrctrl_slot_probe,
88
+
};
89
+
module_platform_driver(pci_pwrctrl_slot_driver);
90
+
91
+
MODULE_AUTHOR("Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>");
92
+
MODULE_DESCRIPTION("Generic PCI Power Control driver for PCI Slots");
93
+
MODULE_LICENSE("GPL");
+2
-2
drivers/pci/quirks.c
+2
-2
drivers/pci/quirks.c
···
621
621
{
622
622
u32 region;
623
623
struct pci_bus_region bus_region;
624
-
struct resource *res = dev->resource + pos;
624
+
struct resource *res = pci_resource_n(dev, pos);
625
625
const char *res_name = pci_resource_name(dev, pos);
626
626
627
627
pci_read_config_dword(dev, PCI_BASE_ADDRESS_0 + (pos << 2), ®ion);
···
671
671
{
672
672
u16 region;
673
673
struct pci_bus_region bus_region;
674
-
struct resource *res = dev->resource + nr;
674
+
struct resource *res = pci_resource_n(dev, nr);
675
675
676
676
pci_read_config_word(dev, port, ®ion);
677
677
region &= ~(size - 1);
+4
-1
drivers/pci/remove.c
+4
-1
drivers/pci/remove.c
···
41
41
if (!pci_dev_test_and_clear_added(dev))
42
42
return;
43
43
44
-
pci_pwrctrl_unregister(&dev->dev);
45
44
device_release_driver(&dev->dev);
46
45
pci_proc_detach_device(dev);
47
46
pci_remove_sysfs_dev_files(dev);
···
52
53
if (pci_dev_test_and_set_removed(dev))
53
54
return;
54
55
56
+
pci_doe_sysfs_teardown(dev);
55
57
pci_npem_remove(dev);
56
58
57
59
device_del(&dev->dev);
···
64
64
pci_doe_destroy(dev);
65
65
pcie_aspm_exit_link_state(dev);
66
66
pci_bridge_d3_update(dev);
67
+
pci_pwrctrl_unregister(&dev->dev);
67
68
pci_free_resources(dev);
68
69
put_device(&dev->dev);
69
70
}
···
163
162
list_for_each_entry_safe_reverse(child, tmp,
164
163
&bus->devices, bus_list)
165
164
pci_stop_bus_device(child);
165
+
166
+
of_pci_remove_host_bridge_node(host_bridge);
166
167
167
168
/* stop the host bridge */
168
169
device_release_driver(&host_bridge->dev);
+328
-249
drivers/pci/setup-bus.c
+328
-249
drivers/pci/setup-bus.c
···
127
127
return dev_res ? dev_res->min_align : 0;
128
128
}
129
129
130
+
static void restore_dev_resource(struct pci_dev_resource *dev_res)
131
+
{
132
+
struct resource *res = dev_res->res;
133
+
134
+
res->start = dev_res->start;
135
+
res->end = dev_res->end;
136
+
res->flags = dev_res->flags;
137
+
}
138
+
139
+
static bool pdev_resources_assignable(struct pci_dev *dev)
140
+
{
141
+
u16 class = dev->class >> 8, command;
142
+
143
+
/* Don't touch classless devices or host bridges or IOAPICs */
144
+
if (class == PCI_CLASS_NOT_DEFINED || class == PCI_CLASS_BRIDGE_HOST)
145
+
return false;
146
+
147
+
/* Don't touch IOAPIC devices already enabled by firmware */
148
+
if (class == PCI_CLASS_SYSTEM_PIC) {
149
+
pci_read_config_word(dev, PCI_COMMAND, &command);
150
+
if (command & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY))
151
+
return false;
152
+
}
153
+
154
+
return true;
155
+
}
156
+
130
157
/* Sort resources by alignment */
131
158
static void pdev_sort_resources(struct pci_dev *dev, struct list_head *head)
132
159
{
133
160
struct resource *r;
134
161
int i;
162
+
163
+
if (!pdev_resources_assignable(dev))
164
+
return;
135
165
136
166
pci_dev_for_each_resource(dev, r, i) {
137
167
const char *r_name = pci_resource_name(dev, i);
···
206
176
}
207
177
}
208
178
209
-
static void __dev_sort_resources(struct pci_dev *dev, struct list_head *head)
179
+
bool pci_resource_is_optional(const struct pci_dev *dev, int resno)
210
180
{
211
-
u16 class = dev->class >> 8;
181
+
const struct resource *res = pci_resource_n(dev, resno);
212
182
213
-
/* Don't touch classless devices or host bridges or IOAPICs */
214
-
if (class == PCI_CLASS_NOT_DEFINED || class == PCI_CLASS_BRIDGE_HOST)
215
-
return;
183
+
if (pci_resource_is_iov(resno))
184
+
return true;
185
+
if (resno == PCI_ROM_RESOURCE && !(res->flags & IORESOURCE_ROM_ENABLE))
186
+
return true;
216
187
217
-
/* Don't touch IOAPIC devices already enabled by firmware */
218
-
if (class == PCI_CLASS_SYSTEM_PIC) {
219
-
u16 command;
220
-
pci_read_config_word(dev, PCI_COMMAND, &command);
221
-
if (command & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY))
222
-
return;
223
-
}
224
-
225
-
pdev_sort_resources(dev, head);
188
+
return false;
226
189
}
227
190
228
191
static inline void reset_resource(struct resource *res)
···
239
216
static void reassign_resources_sorted(struct list_head *realloc_head,
240
217
struct list_head *head)
241
218
{
242
-
struct resource *res;
243
-
const char *res_name;
244
219
struct pci_dev_resource *add_res, *tmp;
245
220
struct pci_dev_resource *dev_res;
221
+
struct pci_dev *dev;
222
+
struct resource *res;
223
+
const char *res_name;
246
224
resource_size_t add_size, align;
247
225
int idx;
248
226
···
251
227
bool found_match = false;
252
228
253
229
res = add_res->res;
230
+
dev = add_res->dev;
231
+
idx = pci_resource_num(dev, res);
254
232
255
-
/* Skip resource that has been reset */
256
-
if (!res->flags)
233
+
/*
234
+
* Skip resource that failed the earlier assignment and is
235
+
* not optional as it would just fail again.
236
+
*/
237
+
if (!res->parent && resource_size(res) &&
238
+
!pci_resource_is_optional(dev, idx))
257
239
goto out;
258
240
259
241
/* Skip this resource if not found in head list */
···
272
242
if (!found_match) /* Just skip */
273
243
continue;
274
244
275
-
idx = res - &add_res->dev->resource[0];
276
-
res_name = pci_resource_name(add_res->dev, idx);
245
+
res_name = pci_resource_name(dev, idx);
277
246
add_size = add_res->add_size;
278
247
align = add_res->min_align;
279
-
if (!resource_size(res)) {
280
-
resource_set_range(res, align, add_size);
281
-
if (pci_assign_resource(add_res->dev, idx))
282
-
reset_resource(res);
283
-
} else {
248
+
if (!res->parent) {
249
+
resource_set_range(res, align,
250
+
resource_size(res) + add_size);
251
+
if (pci_assign_resource(dev, idx)) {
252
+
pci_dbg(dev,
253
+
"%s %pR: ignoring failure in optional allocation\n",
254
+
res_name, res);
255
+
}
256
+
} else if (add_size > 0) {
284
257
res->flags |= add_res->flags &
285
258
(IORESOURCE_STARTALIGN|IORESOURCE_SIZEALIGN);
286
-
if (pci_reassign_resource(add_res->dev, idx,
287
-
add_size, align))
288
-
pci_info(add_res->dev, "%s %pR: failed to add %llx\n",
259
+
if (pci_reassign_resource(dev, idx, add_size, align))
260
+
pci_info(dev, "%s %pR: failed to add optional %llx\n",
289
261
res_name, res,
290
262
(unsigned long long) add_size);
291
263
}
···
303
271
* @head: Head of the list tracking requests for resources
304
272
* @fail_head: Head of the list tracking requests that could not be
305
273
* allocated
274
+
* @optional: Assign also optional resources
306
275
*
307
276
* Satisfy resource requests of each element in the list. Add requests that
308
277
* could not be satisfied to the failed_list.
309
278
*/
310
279
static void assign_requested_resources_sorted(struct list_head *head,
311
-
struct list_head *fail_head)
280
+
struct list_head *fail_head,
281
+
bool optional)
312
282
{
313
-
struct resource *res;
314
283
struct pci_dev_resource *dev_res;
284
+
struct resource *res;
285
+
struct pci_dev *dev;
286
+
bool optional_res;
315
287
int idx;
316
288
317
289
list_for_each_entry(dev_res, head, list) {
318
290
res = dev_res->res;
319
-
idx = res - &dev_res->dev->resource[0];
320
-
if (resource_size(res) &&
321
-
pci_assign_resource(dev_res->dev, idx)) {
291
+
dev = dev_res->dev;
292
+
idx = pci_resource_num(dev, res);
293
+
optional_res = pci_resource_is_optional(dev, idx);
294
+
295
+
if (!resource_size(res))
296
+
continue;
297
+
298
+
if (!optional && optional_res)
299
+
continue;
300
+
301
+
if (pci_assign_resource(dev, idx)) {
322
302
if (fail_head) {
323
-
/*
324
-
* If the failed resource is a ROM BAR and
325
-
* it will be enabled later, don't add it
326
-
* to the list.
327
-
*/
328
-
if (!((idx == PCI_ROM_RESOURCE) &&
329
-
(!(res->flags & IORESOURCE_ROM_ENABLE))))
330
-
add_to_list(fail_head,
331
-
dev_res->dev, res,
332
-
0 /* don't care */,
333
-
0 /* don't care */);
303
+
add_to_list(fail_head, dev, res,
304
+
0 /* don't care */,
305
+
0 /* don't care */);
334
306
}
335
-
reset_resource(res);
336
307
}
337
308
}
338
309
}
···
380
345
return false; /* Should not get here */
381
346
}
382
347
348
+
/* Return: @true if assignment of a required resource failed. */
349
+
static bool pci_required_resource_failed(struct list_head *fail_head)
350
+
{
351
+
struct pci_dev_resource *fail_res;
352
+
353
+
list_for_each_entry(fail_res, fail_head, list) {
354
+
int idx = pci_resource_num(fail_res->dev, fail_res->res);
355
+
356
+
if (!pci_resource_is_optional(fail_res->dev, idx))
357
+
return true;
358
+
}
359
+
return false;
360
+
}
361
+
383
362
static void __assign_resources_sorted(struct list_head *head,
384
363
struct list_head *realloc_head,
385
364
struct list_head *fail_head)
···
403
354
* adjacent, so later reassign can not reallocate them one by one in
404
355
* parent resource window.
405
356
*
406
-
* Try to assign requested + add_size at beginning. If could do that,
407
-
* could get out early. If could not do that, we still try to assign
408
-
* requested at first, then try to reassign add_size for some resources.
357
+
* Try to assign required and any optional resources at beginning
358
+
* (add_size included). If all required resources were successfully
359
+
* assigned, get out early. If could not do that, we still try to
360
+
* assign required at first, then try to reassign some optional
361
+
* resources.
409
362
*
410
363
* Separate three resource type checking if we need to release
411
364
* assigned resource after requested + add_size try.
···
423
372
*/
424
373
LIST_HEAD(save_head);
425
374
LIST_HEAD(local_fail_head);
375
+
LIST_HEAD(dummy_head);
426
376
struct pci_dev_resource *save_res;
427
377
struct pci_dev_resource *dev_res, *tmp_res, *dev_res2;
378
+
struct resource *res;
379
+
struct pci_dev *dev;
380
+
const char *res_name;
381
+
int idx;
428
382
unsigned long fail_type;
429
383
resource_size_t add_align, align;
430
384
385
+
if (!realloc_head)
386
+
realloc_head = &dummy_head;
387
+
431
388
/* Check if optional add_size is there */
432
-
if (!realloc_head || list_empty(realloc_head))
433
-
goto requested_and_reassign;
389
+
if (list_empty(realloc_head))
390
+
goto assign;
434
391
435
392
/* Save original start, end, flags etc at first */
436
393
list_for_each_entry(dev_res, head, list) {
437
394
if (add_to_list(&save_head, dev_res->dev, dev_res->res, 0, 0)) {
438
395
free_list(&save_head);
439
-
goto requested_and_reassign;
396
+
goto assign;
440
397
}
441
398
}
442
399
443
400
/* Update res in head list with add_size in realloc_head list */
444
401
list_for_each_entry_safe(dev_res, tmp_res, head, list) {
445
-
dev_res->res->end += get_res_add_size(realloc_head,
446
-
dev_res->res);
402
+
res = dev_res->res;
403
+
404
+
res->end += get_res_add_size(realloc_head, res);
447
405
448
406
/*
449
407
* There are two kinds of additional resources in the list:
···
460
400
* 2. SR-IOV resource -- IORESOURCE_SIZEALIGN
461
401
* Here just fix the additional alignment for bridge
462
402
*/
463
-
if (!(dev_res->res->flags & IORESOURCE_STARTALIGN))
403
+
if (!(res->flags & IORESOURCE_STARTALIGN))
464
404
continue;
465
405
466
-
add_align = get_res_add_align(realloc_head, dev_res->res);
406
+
add_align = get_res_add_align(realloc_head, res);
467
407
468
408
/*
469
409
* The "head" list is sorted by alignment so resources with
···
472
412
* need to reorder the list by alignment to make it
473
413
* consistent.
474
414
*/
475
-
if (add_align > dev_res->res->start) {
476
-
resource_size_t r_size = resource_size(dev_res->res);
477
-
478
-
dev_res->res->start = add_align;
479
-
dev_res->res->end = add_align + r_size - 1;
415
+
if (add_align > res->start) {
416
+
resource_set_range(res, add_align, resource_size(res));
480
417
481
418
list_for_each_entry(dev_res2, head, list) {
482
419
align = pci_resource_alignment(dev_res2->dev,
···
488
431
489
432
}
490
433
491
-
/* Try updated head list with add_size added */
492
-
assign_requested_resources_sorted(head, &local_fail_head);
434
+
assign:
435
+
assign_requested_resources_sorted(head, &local_fail_head, true);
493
436
494
-
/* All assigned with add_size? */
437
+
/* All non-optional resources assigned? */
495
438
if (list_empty(&local_fail_head)) {
496
439
/* Remove head list from realloc_head list */
497
440
list_for_each_entry(dev_res, head, list)
498
441
remove_from_list(realloc_head, dev_res->res);
499
442
free_list(&save_head);
500
-
free_list(head);
501
-
return;
443
+
goto out;
444
+
}
445
+
446
+
/* Without realloc_head and only optional fails, nothing more to do. */
447
+
if (!pci_required_resource_failed(&local_fail_head) &&
448
+
list_empty(realloc_head)) {
449
+
list_for_each_entry(save_res, &save_head, list) {
450
+
struct resource *res = save_res->res;
451
+
452
+
if (res->parent)
453
+
continue;
454
+
455
+
restore_dev_resource(save_res);
456
+
}
457
+
free_list(&local_fail_head);
458
+
free_list(&save_head);
459
+
goto out;
502
460
}
503
461
504
462
/* Check failed type */
505
463
fail_type = pci_fail_res_type_mask(&local_fail_head);
506
464
/* Remove not need to be released assigned res from head list etc */
507
-
list_for_each_entry_safe(dev_res, tmp_res, head, list)
508
-
if (dev_res->res->parent &&
509
-
!pci_need_to_release(fail_type, dev_res->res)) {
465
+
list_for_each_entry_safe(dev_res, tmp_res, head, list) {
466
+
res = dev_res->res;
467
+
468
+
if (res->parent && !pci_need_to_release(fail_type, res)) {
510
469
/* Remove it from realloc_head list */
511
-
remove_from_list(realloc_head, dev_res->res);
512
-
remove_from_list(&save_head, dev_res->res);
470
+
remove_from_list(realloc_head, res);
471
+
remove_from_list(&save_head, res);
513
472
list_del(&dev_res->list);
514
473
kfree(dev_res);
515
474
}
475
+
}
516
476
517
477
free_list(&local_fail_head);
518
478
/* Release assigned resource */
519
-
list_for_each_entry(dev_res, head, list)
520
-
if (dev_res->res->parent)
521
-
release_resource(dev_res->res);
522
-
/* Restore start/end/flags from saved list */
523
-
list_for_each_entry(save_res, &save_head, list) {
524
-
struct resource *res = save_res->res;
479
+
list_for_each_entry(dev_res, head, list) {
480
+
res = dev_res->res;
481
+
dev = dev_res->dev;
525
482
526
-
res->start = save_res->start;
527
-
res->end = save_res->end;
528
-
res->flags = save_res->flags;
483
+
if (!res->parent)
484
+
continue;
485
+
486
+
idx = pci_resource_num(dev, res);
487
+
res_name = pci_resource_name(dev, idx);
488
+
pci_dbg(dev, "%s %pR: releasing\n", res_name, res);
489
+
490
+
release_resource(res);
529
491
}
492
+
/* Restore start/end/flags from saved list */
493
+
list_for_each_entry(save_res, &save_head, list)
494
+
restore_dev_resource(save_res);
530
495
free_list(&save_head);
531
496
532
-
requested_and_reassign:
533
497
/* Satisfy the must-have resource requests */
534
-
assign_requested_resources_sorted(head, fail_head);
498
+
assign_requested_resources_sorted(head, NULL, false);
535
499
536
500
/* Try to satisfy any additional optional resource requests */
537
-
if (realloc_head)
501
+
if (!list_empty(realloc_head))
538
502
reassign_resources_sorted(realloc_head, head);
503
+
504
+
out:
505
+
/* Reset any failed resource, cannot use fail_head as it can be NULL. */
506
+
list_for_each_entry(dev_res, head, list) {
507
+
res = dev_res->res;
508
+
dev = dev_res->dev;
509
+
510
+
if (res->parent)
511
+
continue;
512
+
513
+
if (fail_head) {
514
+
add_to_list(fail_head, dev, res,
515
+
0 /* don't care */,
516
+
0 /* don't care */);
517
+
}
518
+
519
+
reset_resource(res);
520
+
}
521
+
539
522
free_list(head);
540
523
}
541
524
···
585
488
{
586
489
LIST_HEAD(head);
587
490
588
-
__dev_sort_resources(dev, &head);
491
+
pdev_sort_resources(dev, &head);
589
492
__assign_resources_sorted(&head, add_head, fail_head);
590
493
591
494
}
···
598
501
LIST_HEAD(head);
599
502
600
503
list_for_each_entry(dev, &bus->devices, bus_list)
601
-
__dev_sort_resources(dev, &head);
504
+
pdev_sort_resources(dev, &head);
602
505
603
506
__assign_resources_sorted(&head, realloc_head, fail_head);
604
507
}
···
791
694
{
792
695
}
793
696
794
-
void pci_setup_bridge(struct pci_bus *bus)
697
+
static void pci_setup_bridge(struct pci_bus *bus)
795
698
{
796
699
unsigned long type = IORESOURCE_IO | IORESOURCE_MEM |
797
700
IORESOURCE_PREFETCH;
···
911
814
size = (size & 0xff) + ((size & ~0xffUL) << 2);
912
815
#endif
913
816
size = size + size1;
914
-
if (size < old_size)
915
-
size = old_size;
916
817
917
-
size = ALIGN(max(size, add_size) + children_add_size, align);
918
-
return size;
818
+
size = max(size, add_size) + children_add_size;
819
+
return ALIGN(max(size, old_size), align);
919
820
}
920
821
921
822
static resource_size_t calculate_memsize(resource_size_t size,
···
938
843
return 1;
939
844
}
940
845
941
-
#define PCI_P2P_DEFAULT_MEM_ALIGN 0x100000 /* 1MiB */
942
-
#define PCI_P2P_DEFAULT_IO_ALIGN 0x1000 /* 4KiB */
943
-
#define PCI_P2P_DEFAULT_IO_ALIGN_1K 0x400 /* 1KiB */
846
+
#define PCI_P2P_DEFAULT_MEM_ALIGN SZ_1M
847
+
#define PCI_P2P_DEFAULT_IO_ALIGN SZ_4K
848
+
#define PCI_P2P_DEFAULT_IO_ALIGN_1K SZ_1K
944
849
945
850
static resource_size_t window_alignment(struct pci_bus *bus, unsigned long type)
946
851
{
···
1005
910
continue;
1006
911
r_size = resource_size(r);
1007
912
1008
-
if (r_size < 0x400)
913
+
if (r_size < SZ_1K)
1009
914
/* Might be re-aligned for ISA */
1010
915
size += r_size;
1011
916
else
···
1022
927
1023
928
size0 = calculate_iosize(size, min_size, size1, 0, 0,
1024
929
resource_size(b_res), min_align);
1025
-
size1 = (!realloc_head || (realloc_head && !add_size && !children_add_size)) ? size0 :
1026
-
calculate_iosize(size, min_size, size1, add_size, children_add_size,
1027
-
resource_size(b_res), min_align);
930
+
931
+
size1 = size0;
932
+
if (realloc_head && (add_size > 0 || children_add_size > 0)) {
933
+
size1 = calculate_iosize(size, min_size, size1, add_size,
934
+
children_add_size, resource_size(b_res),
935
+
min_align);
936
+
}
937
+
1028
938
if (!size0 && !size1) {
1029
939
if (bus->self && (b_res->start || b_res->end))
1030
940
pci_info(bus->self, "disabling bridge window %pR to %pR (unused)\n",
···
1158
1058
struct list_head *realloc_head)
1159
1059
{
1160
1060
struct pci_dev *dev;
1161
-
resource_size_t min_align, win_align, align, size, size0, size1;
1162
-
resource_size_t aligns[24]; /* Alignments from 1MB to 8TB */
1061
+
resource_size_t min_align, win_align, align, size, size0, size1 = 0;
1062
+
resource_size_t aligns[28]; /* Alignments from 1MB to 128TB */
1163
1063
int order, max_order;
1164
1064
struct resource *b_res = find_bus_resource_of_type(bus,
1165
1065
mask | IORESOURCE_PREFETCH, type);
···
1192
1092
(r->flags & mask) != type3))
1193
1093
continue;
1194
1094
r_size = resource_size(r);
1195
-
#ifdef CONFIG_PCI_IOV
1095
+
1196
1096
/* Put SRIOV requested res to the optional list */
1197
-
if (realloc_head && i >= PCI_IOV_RESOURCES &&
1198
-
i <= PCI_IOV_RESOURCE_END) {
1097
+
if (realloc_head && pci_resource_is_optional(dev, i)) {
1199
1098
add_align = max(pci_resource_alignment(dev, r), add_align);
1200
-
r->end = r->start - 1;
1201
-
add_to_list(realloc_head, dev, r, r_size, 0 /* Don't care */);
1099
+
add_to_list(realloc_head, dev, r, 0, 0 /* Don't care */);
1202
1100
children_add_size += r_size;
1203
1101
continue;
1204
1102
}
1205
-
#endif
1103
+
1206
1104
/*
1207
1105
* aligns[0] is for 1MB (since bridge memory
1208
1106
* windows are always at least 1MB aligned), so
···
1239
1141
min_align = calculate_mem_align(aligns, max_order);
1240
1142
min_align = max(min_align, win_align);
1241
1143
size0 = calculate_memsize(size, min_size, 0, 0, resource_size(b_res), min_align);
1242
-
add_align = max(min_align, add_align);
1243
1144
1244
1145
if (bus->self && size0 &&
1245
1146
!pbus_upstream_space_available(bus, mask | IORESOURCE_PREFETCH, type,
1246
-
size0, add_align)) {
1147
+
size0, min_align)) {
1247
1148
min_align = 1ULL << (max_order + __ffs(SZ_1M));
1248
1149
min_align = max(min_align, win_align);
1249
1150
size0 = calculate_memsize(size, min_size, 0, 0, resource_size(b_res), win_align);
1250
-
add_align = win_align;
1251
1151
pci_info(bus->self, "bridge window %pR to %pR requires relaxed alignment rules\n",
1252
1152
b_res, &bus->busn_res);
1253
1153
}
1254
1154
1255
-
size1 = (!realloc_head || (realloc_head && !add_size && !children_add_size)) ? size0 :
1256
-
calculate_memsize(size, min_size, add_size, children_add_size,
1257
-
resource_size(b_res), add_align);
1155
+
if (realloc_head && (add_size > 0 || children_add_size > 0)) {
1156
+
add_align = max(min_align, add_align);
1157
+
size1 = calculate_memsize(size, min_size, add_size, children_add_size,
1158
+
resource_size(b_res), add_align);
1159
+
1160
+
if (bus->self && size1 &&
1161
+
!pbus_upstream_space_available(bus, mask | IORESOURCE_PREFETCH, type,
1162
+
size1, add_align)) {
1163
+
min_align = 1ULL << (max_order + __ffs(SZ_1M));
1164
+
min_align = max(min_align, win_align);
1165
+
size1 = calculate_memsize(size, min_size, add_size, children_add_size,
1166
+
resource_size(b_res), win_align);
1167
+
pci_info(bus->self,
1168
+
"bridge window %pR to %pR requires relaxed alignment rules\n",
1169
+
b_res, &bus->busn_res);
1170
+
}
1171
+
}
1172
+
1258
1173
if (!size0 && !size1) {
1259
1174
if (bus->self && (b_res->start || b_res->end))
1260
1175
pci_info(bus->self, "disabling bridge window %pR to %pR (unused)\n",
···
1275
1164
b_res->flags = 0;
1276
1165
return 0;
1277
1166
}
1278
-
b_res->start = min_align;
1279
-
b_res->end = size0 + min_align - 1;
1167
+
1168
+
resource_set_range(b_res, min_align, size0);
1280
1169
b_res->flags |= IORESOURCE_STARTALIGN;
1281
1170
if (bus->self && size1 > size0 && realloc_head) {
1282
1171
add_to_list(realloc_head, bus->self, b_res, size1-size0, add_align);
···
1751
1640
pci_info(dev, "resource %d %pR released\n",
1752
1641
PCI_BRIDGE_RESOURCES + idx, r);
1753
1642
/* Keep the old size */
1754
-
r->end = resource_size(r) - 1;
1755
-
r->start = 0;
1643
+
resource_set_range(r, 0, resource_size(r));
1756
1644
r->flags = 0;
1757
1645
1758
1646
/* Avoiding touch the one without PREF */
···
1990
1880
* Make sure prefetchable memory is reduced from
1991
1881
* the correct resource. Specifically we put 32-bit
1992
1882
* prefetchable memory in non-prefetchable window
1993
-
* if there is an 64-bit prefetchable window.
1883
+
* if there is a 64-bit prefetchable window.
1994
1884
*
1995
1885
* See comments in __pci_bus_size_bridges() for
1996
1886
* more information.
···
2212
2102
* in case of root bus.
2213
2103
*/
2214
2104
if (bridge && pci_bridge_resources_not_assigned(dev))
2215
-
pci_bridge_distribute_available_resources(bridge,
2216
-
add_list);
2105
+
pci_bridge_distribute_available_resources(dev, add_list);
2217
2106
else
2218
2107
pci_root_bus_distribute_available_resources(b, add_list);
2219
2108
}
2109
+
}
2110
+
2111
+
static void pci_prepare_next_assign_round(struct list_head *fail_head,
2112
+
int tried_times,
2113
+
enum release_type rel_type)
2114
+
{
2115
+
struct pci_dev_resource *fail_res;
2116
+
2117
+
pr_info("PCI: No. %d try to assign unassigned res\n", tried_times + 1);
2118
+
2119
+
/*
2120
+
* Try to release leaf bridge's resources that aren't big
2121
+
* enough to contain child device resources.
2122
+
*/
2123
+
list_for_each_entry(fail_res, fail_head, list) {
2124
+
pci_bus_release_bridge_resources(fail_res->dev->bus,
2125
+
fail_res->flags & PCI_RES_TYPE_MASK,
2126
+
rel_type);
2127
+
}
2128
+
2129
+
/* Restore size and flags */
2130
+
list_for_each_entry(fail_res, fail_head, list) {
2131
+
struct resource *res = fail_res->res;
2132
+
struct pci_dev *dev = fail_res->dev;
2133
+
int idx = pci_resource_num(dev, res);
2134
+
2135
+
restore_dev_resource(fail_res);
2136
+
2137
+
if (!pci_is_bridge(dev))
2138
+
continue;
2139
+
2140
+
if (idx >= PCI_BRIDGE_RESOURCES &&
2141
+
idx <= PCI_BRIDGE_RESOURCE_END)
2142
+
res->flags = 0;
2143
+
}
2144
+
2145
+
free_list(fail_head);
2220
2146
}
2221
2147
2222
2148
/*
···
2268
2122
int tried_times = 0;
2269
2123
enum release_type rel_type = leaf_only;
2270
2124
LIST_HEAD(fail_head);
2271
-
struct pci_dev_resource *fail_res;
2272
2125
int pci_try_num = 1;
2273
2126
enum enable_type enable_local;
2274
2127
···
2281
2136
max_depth, pci_try_num);
2282
2137
}
2283
2138
2284
-
again:
2285
-
/*
2286
-
* Last try will use add_list, otherwise will try good to have as must
2287
-
* have, so can realloc parent bridge resource
2288
-
*/
2289
-
if (tried_times + 1 == pci_try_num)
2290
-
add_list = &realloc_head;
2291
-
/*
2292
-
* Depth first, calculate sizes and alignments of all subordinate buses.
2293
-
*/
2294
-
__pci_bus_size_bridges(bus, add_list);
2139
+
while (1) {
2140
+
/*
2141
+
* Last try will use add_list, otherwise will try good to
2142
+
* have as must have, so can realloc parent bridge resource
2143
+
*/
2144
+
if (tried_times + 1 == pci_try_num)
2145
+
add_list = &realloc_head;
2146
+
/*
2147
+
* Depth first, calculate sizes and alignments of all
2148
+
* subordinate buses.
2149
+
*/
2150
+
__pci_bus_size_bridges(bus, add_list);
2295
2151
2296
-
pci_root_bus_distribute_available_resources(bus, add_list);
2152
+
pci_root_bus_distribute_available_resources(bus, add_list);
2297
2153
2298
-
/* Depth last, allocate resources and update the hardware. */
2299
-
__pci_bus_assign_resources(bus, add_list, &fail_head);
2300
-
if (add_list)
2301
-
BUG_ON(!list_empty(add_list));
2302
-
tried_times++;
2154
+
/* Depth last, allocate resources and update the hardware. */
2155
+
__pci_bus_assign_resources(bus, add_list, &fail_head);
2156
+
if (add_list)
2157
+
BUG_ON(!list_empty(add_list));
2158
+
tried_times++;
2303
2159
2304
-
/* Any device complain? */
2305
-
if (list_empty(&fail_head))
2306
-
goto dump;
2160
+
/* Any device complain? */
2161
+
if (list_empty(&fail_head))
2162
+
break;
2307
2163
2308
-
if (tried_times >= pci_try_num) {
2309
-
if (enable_local == undefined)
2310
-
dev_info(&bus->dev, "Some PCI device resources are unassigned, try booting with pci=realloc\n");
2311
-
else if (enable_local == auto_enabled)
2312
-
dev_info(&bus->dev, "Automatically enabled pci realloc, if you have problem, try booting with pci=realloc=off\n");
2313
-
2314
-
free_list(&fail_head);
2315
-
goto dump;
2316
-
}
2317
-
2318
-
dev_info(&bus->dev, "No. %d try to assign unassigned res\n",
2319
-
tried_times + 1);
2320
-
2321
-
/* Third times and later will not check if it is leaf */
2322
-
if ((tried_times + 1) > 2)
2323
-
rel_type = whole_subtree;
2324
-
2325
-
/*
2326
-
* Try to release leaf bridge's resources that doesn't fit resource of
2327
-
* child device under that bridge.
2328
-
*/
2329
-
list_for_each_entry(fail_res, &fail_head, list)
2330
-
pci_bus_release_bridge_resources(fail_res->dev->bus,
2331
-
fail_res->flags & PCI_RES_TYPE_MASK,
2332
-
rel_type);
2333
-
2334
-
/* Restore size and flags */
2335
-
list_for_each_entry(fail_res, &fail_head, list) {
2336
-
struct resource *res = fail_res->res;
2337
-
int idx;
2338
-
2339
-
res->start = fail_res->start;
2340
-
res->end = fail_res->end;
2341
-
res->flags = fail_res->flags;
2342
-
2343
-
if (pci_is_bridge(fail_res->dev)) {
2344
-
idx = res - &fail_res->dev->resource[0];
2345
-
if (idx >= PCI_BRIDGE_RESOURCES &&
2346
-
idx <= PCI_BRIDGE_RESOURCE_END)
2347
-
res->flags = 0;
2164
+
if (tried_times >= pci_try_num) {
2165
+
if (enable_local == undefined) {
2166
+
dev_info(&bus->dev,
2167
+
"Some PCI device resources are unassigned, try booting with pci=realloc\n");
2168
+
} else if (enable_local == auto_enabled) {
2169
+
dev_info(&bus->dev,
2170
+
"Automatically enabled pci realloc, if you have problem, try booting with pci=realloc=off\n");
2171
+
}
2172
+
free_list(&fail_head);
2173
+
break;
2348
2174
}
2175
+
2176
+
/* Third times and later will not check if it is leaf */
2177
+
if (tried_times + 1 > 2)
2178
+
rel_type = whole_subtree;
2179
+
2180
+
pci_prepare_next_assign_round(&fail_head, tried_times, rel_type);
2349
2181
}
2350
-
free_list(&fail_head);
2351
2182
2352
-
goto again;
2353
-
2354
-
dump:
2355
-
/* Dump the resource on buses */
2356
2183
pci_bus_dump_resources(bus);
2357
2184
}
2358
2185
···
2346
2229
struct pci_bus *parent = bridge->subordinate;
2347
2230
/* List of resources that want additional resources */
2348
2231
LIST_HEAD(add_list);
2349
-
2350
2232
int tried_times = 0;
2351
2233
LIST_HEAD(fail_head);
2352
-
struct pci_dev_resource *fail_res;
2353
-
int retval;
2234
+
int ret;
2354
2235
2355
-
again:
2356
-
__pci_bus_size_bridges(parent, &add_list);
2236
+
while (1) {
2237
+
__pci_bus_size_bridges(parent, &add_list);
2357
2238
2358
-
/*
2359
-
* Distribute remaining resources (if any) equally between hotplug
2360
-
* bridges below. This makes it possible to extend the hierarchy
2361
-
* later without running out of resources.
2362
-
*/
2363
-
pci_bridge_distribute_available_resources(bridge, &add_list);
2239
+
/*
2240
+
* Distribute remaining resources (if any) equally between
2241
+
* hotplug bridges below. This makes it possible to extend
2242
+
* the hierarchy later without running out of resources.
2243
+
*/
2244
+
pci_bridge_distribute_available_resources(bridge, &add_list);
2364
2245
2365
-
__pci_bridge_assign_resources(bridge, &add_list, &fail_head);
2366
-
BUG_ON(!list_empty(&add_list));
2367
-
tried_times++;
2246
+
__pci_bridge_assign_resources(bridge, &add_list, &fail_head);
2247
+
BUG_ON(!list_empty(&add_list));
2248
+
tried_times++;
2368
2249
2369
-
if (list_empty(&fail_head))
2370
-
goto enable_all;
2250
+
if (list_empty(&fail_head))
2251
+
break;
2371
2252
2372
-
if (tried_times >= 2) {
2373
-
/* Still fail, don't need to try more */
2374
-
free_list(&fail_head);
2375
-
goto enable_all;
2376
-
}
2377
-
2378
-
printk(KERN_DEBUG "PCI: No. %d try to assign unassigned res\n",
2379
-
tried_times + 1);
2380
-
2381
-
/*
2382
-
* Try to release leaf bridge's resources that aren't big enough
2383
-
* to contain child device resources.
2384
-
*/
2385
-
list_for_each_entry(fail_res, &fail_head, list)
2386
-
pci_bus_release_bridge_resources(fail_res->dev->bus,
2387
-
fail_res->flags & PCI_RES_TYPE_MASK,
2388
-
whole_subtree);
2389
-
2390
-
/* Restore size and flags */
2391
-
list_for_each_entry(fail_res, &fail_head, list) {
2392
-
struct resource *res = fail_res->res;
2393
-
int idx;
2394
-
2395
-
res->start = fail_res->start;
2396
-
res->end = fail_res->end;
2397
-
res->flags = fail_res->flags;
2398
-
2399
-
if (pci_is_bridge(fail_res->dev)) {
2400
-
idx = res - &fail_res->dev->resource[0];
2401
-
if (idx >= PCI_BRIDGE_RESOURCES &&
2402
-
idx <= PCI_BRIDGE_RESOURCE_END)
2403
-
res->flags = 0;
2253
+
if (tried_times >= 2) {
2254
+
/* Still fail, don't need to try more */
2255
+
free_list(&fail_head);
2256
+
break;
2404
2257
}
2258
+
2259
+
pci_prepare_next_assign_round(&fail_head, tried_times,
2260
+
whole_subtree);
2405
2261
}
2406
-
free_list(&fail_head);
2407
2262
2408
-
goto again;
2409
-
2410
-
enable_all:
2411
-
retval = pci_reenable_device(bridge);
2412
-
if (retval)
2413
-
pci_err(bridge, "Error reenabling bridge (%d)\n", retval);
2263
+
ret = pci_reenable_device(bridge);
2264
+
if (ret)
2265
+
pci_err(bridge, "Error reenabling bridge (%d)\n", ret);
2414
2266
pci_set_master(bridge);
2415
2267
}
2416
2268
EXPORT_SYMBOL_GPL(pci_assign_unassigned_bridge_resources);
···
2459
2373
2460
2374
cleanup:
2461
2375
/* Restore size and flags */
2462
-
list_for_each_entry(dev_res, &failed, list) {
2463
-
struct resource *res = dev_res->res;
2464
-
2465
-
res->start = dev_res->start;
2466
-
res->end = dev_res->end;
2467
-
res->flags = dev_res->flags;
2468
-
}
2376
+
list_for_each_entry(dev_res, &failed, list)
2377
+
restore_dev_resource(dev_res);
2469
2378
free_list(&failed);
2470
2379
2471
2380
/* Revert to the old configuration */
···
2468
2387
struct resource *res = dev_res->res;
2469
2388
2470
2389
bridge = dev_res->dev;
2471
-
i = res - bridge->resource;
2390
+
i = pci_resource_num(bridge, res);
2472
2391
2473
-
res->start = dev_res->start;
2474
-
res->end = dev_res->end;
2475
-
res->flags = dev_res->flags;
2392
+
restore_dev_resource(dev_res);
2476
2393
2477
2394
pci_claim_resource(bridge, i);
2478
2395
pci_setup_bridge(bridge->subordinate);
+10
-14
drivers/pci/setup-res.c
+10
-14
drivers/pci/setup-res.c
···
29
29
u16 cmd;
30
30
u32 new, check, mask;
31
31
int reg;
32
-
struct resource *res = dev->resource + resno;
32
+
struct resource *res = pci_resource_n(dev, resno);
33
33
const char *res_name = pci_resource_name(dev, resno);
34
34
35
35
/* Per SR-IOV spec 3.4.1.11, VF BARs are RO zero */
···
127
127
{
128
128
if (resno <= PCI_ROM_RESOURCE)
129
129
pci_std_update_resource(dev, resno);
130
-
#ifdef CONFIG_PCI_IOV
131
-
else if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END)
130
+
else if (pci_resource_is_iov(resno))
132
131
pci_iov_update_resource(dev, resno);
133
-
#endif
134
132
}
135
133
136
134
int pci_claim_resource(struct pci_dev *dev, int resource)
···
260
262
static int __pci_assign_resource(struct pci_bus *bus, struct pci_dev *dev,
261
263
int resno, resource_size_t size, resource_size_t align)
262
264
{
263
-
struct resource *res = dev->resource + resno;
265
+
struct resource *res = pci_resource_n(dev, resno);
264
266
resource_size_t min;
265
267
int ret;
266
268
···
323
325
324
326
int pci_assign_resource(struct pci_dev *dev, int resno)
325
327
{
326
-
struct resource *res = dev->resource + resno;
328
+
struct resource *res = pci_resource_n(dev, resno);
327
329
const char *res_name = pci_resource_name(dev, resno);
328
330
resource_size_t align, size;
329
331
int ret;
···
370
372
int pci_reassign_resource(struct pci_dev *dev, int resno,
371
373
resource_size_t addsize, resource_size_t min_align)
372
374
{
373
-
struct resource *res = dev->resource + resno;
375
+
struct resource *res = pci_resource_n(dev, resno);
374
376
const char *res_name = pci_resource_name(dev, resno);
375
377
unsigned long flags;
376
378
resource_size_t new_size;
···
387
389
return -EINVAL;
388
390
}
389
391
390
-
/* already aligned with min_align */
391
392
new_size = resource_size(res) + addsize;
392
393
ret = _pci_assign_resource(dev, resno, new_size, min_align);
393
394
if (ret) {
···
408
411
409
412
void pci_release_resource(struct pci_dev *dev, int resno)
410
413
{
411
-
struct resource *res = dev->resource + resno;
414
+
struct resource *res = pci_resource_n(dev, resno);
412
415
const char *res_name = pci_resource_name(dev, resno);
413
-
414
-
pci_info(dev, "%s %pR: releasing\n", res_name, res);
415
416
416
417
if (!res->parent)
417
418
return;
419
+
420
+
pci_info(dev, "%s %pR: releasing\n", res_name, res);
418
421
419
422
release_resource(res);
420
423
res->end = resource_size(res) - 1;
···
425
428
426
429
int pci_resize_resource(struct pci_dev *dev, int resno, int size)
427
430
{
428
-
struct resource *res = dev->resource + resno;
431
+
struct resource *res = pci_resource_n(dev, resno);
429
432
struct pci_host_bridge *host;
430
433
int old, ret;
431
434
u32 sizes;
···
494
497
495
498
if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM)))
496
499
continue;
497
-
if ((i == PCI_ROM_RESOURCE) &&
498
-
(!(r->flags & IORESOURCE_ROM_ENABLE)))
500
+
if (pci_resource_is_optional(dev, i))
499
501
continue;
500
502
501
503
if (r->flags & IORESOURCE_UNSET) {
-44
drivers/pci/slot.c
-44
drivers/pci/slot.c
···
7
7
8
8
#include <linux/kobject.h>
9
9
#include <linux/slab.h>
10
-
#include <linux/module.h>
11
10
#include <linux/pci.h>
12
11
#include <linux/err.h>
13
12
#include "pci.h"
···
323
324
mutex_unlock(&pci_slot_mutex);
324
325
}
325
326
EXPORT_SYMBOL_GPL(pci_destroy_slot);
326
-
327
-
#if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
328
-
#include <linux/pci_hotplug.h>
329
-
/**
330
-
* pci_hp_create_module_link - create symbolic link to hotplug driver module
331
-
* @pci_slot: struct pci_slot
332
-
*
333
-
* Helper function for pci_hotplug_core.c to create symbolic link to
334
-
* the hotplug driver module.
335
-
*/
336
-
void pci_hp_create_module_link(struct pci_slot *pci_slot)
337
-
{
338
-
struct hotplug_slot *slot = pci_slot->hotplug;
339
-
struct kobject *kobj = NULL;
340
-
int ret;
341
-
342
-
if (!slot || !slot->ops)
343
-
return;
344
-
kobj = kset_find_obj(module_kset, slot->mod_name);
345
-
if (!kobj)
346
-
return;
347
-
ret = sysfs_create_link(&pci_slot->kobj, kobj, "module");
348
-
if (ret)
349
-
dev_err(&pci_slot->bus->dev, "Error creating sysfs link (%d)\n",
350
-
ret);
351
-
kobject_put(kobj);
352
-
}
353
-
EXPORT_SYMBOL_GPL(pci_hp_create_module_link);
354
-
355
-
/**
356
-
* pci_hp_remove_module_link - remove symbolic link to the hotplug driver
357
-
* module.
358
-
* @pci_slot: struct pci_slot
359
-
*
360
-
* Helper function for pci_hotplug_core.c to remove symbolic link to
361
-
* the hotplug driver module.
362
-
*/
363
-
void pci_hp_remove_module_link(struct pci_slot *pci_slot)
364
-
{
365
-
sysfs_remove_link(&pci_slot->kobj, "module");
366
-
}
367
-
EXPORT_SYMBOL_GPL(pci_hp_remove_module_link);
368
-
#endif
369
327
370
328
static int pci_slot_init(void)
371
329
{
+3
-22
drivers/perf/dwc_pcie_pmu.c
+3
-22
drivers/perf/dwc_pcie_pmu.c
···
13
13
#include <linux/errno.h>
14
14
#include <linux/kernel.h>
15
15
#include <linux/list.h>
16
+
#include <linux/pcie-dwc.h>
16
17
#include <linux/perf_event.h>
17
18
#include <linux/pci.h>
18
19
#include <linux/platform_device.h>
···
98
97
struct platform_device *plat_dev;
99
98
struct pci_dev *pdev;
100
99
struct list_head dev_node;
101
-
};
102
-
103
-
struct dwc_pcie_pmu_vsec_id {
104
-
u16 vendor_id;
105
-
u16 vsec_id;
106
-
u8 vsec_rev;
107
-
};
108
-
109
-
/*
110
-
* VSEC IDs are allocated by the vendor, so a given ID may mean different
111
-
* things to different vendors. See PCIe r6.0, sec 7.9.5.2.
112
-
*/
113
-
static const struct dwc_pcie_pmu_vsec_id dwc_pcie_pmu_vsec_ids[] = {
114
-
{ .vendor_id = PCI_VENDOR_ID_ALIBABA,
115
-
.vsec_id = 0x02, .vsec_rev = 0x4 },
116
-
{ .vendor_id = PCI_VENDOR_ID_AMPERE,
117
-
.vsec_id = 0x02, .vsec_rev = 0x4 },
118
-
{ .vendor_id = PCI_VENDOR_ID_QCOM,
119
-
.vsec_id = 0x02, .vsec_rev = 0x4 },
120
-
{} /* terminator */
121
100
};
122
101
123
102
static ssize_t cpumask_show(struct device *dev,
···
510
529
511
530
static u16 dwc_pcie_des_cap(struct pci_dev *pdev)
512
531
{
513
-
const struct dwc_pcie_pmu_vsec_id *vid;
532
+
const struct dwc_pcie_vsec_id *vid;
514
533
u16 vsec;
515
534
u32 val;
516
535
517
536
if (!pci_is_pcie(pdev) || !(pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT))
518
537
return 0;
519
538
520
-
for (vid = dwc_pcie_pmu_vsec_ids; vid->vendor_id; vid++) {
539
+
for (vid = dwc_pcie_rasdes_vsec_ids; vid->vendor_id; vid++) {
521
540
vsec = pci_find_vsec_capability(pdev, vid->vendor_id,
522
541
vid->vsec_id);
523
542
if (vsec) {
-1
drivers/s390/net/ism_drv.c
-1
drivers/s390/net/ism_drv.c
-4
drivers/vfio/pci/Kconfig
-4
drivers/vfio/pci/Kconfig
+1
-1
drivers/vfio/pci/vfio_pci_core.c
+1
-1
drivers/vfio/pci/vfio_pci_core.c
+10
-2
include/linux/aer.h
+10
-2
include/linux/aer.h
···
22
22
*/
23
23
#define PCIE_STD_NUM_TLP_HEADERLOG 4
24
24
#define PCIE_STD_MAX_TLP_PREFIXLOG 4
25
+
#define PCIE_STD_MAX_TLP_HEADERLOG (PCIE_STD_NUM_TLP_HEADERLOG + 10)
25
26
26
27
struct pci_dev;
27
28
28
29
struct pcie_tlp_log {
29
-
u32 dw[PCIE_STD_NUM_TLP_HEADERLOG];
30
-
u32 prefix[PCIE_STD_MAX_TLP_PREFIXLOG];
30
+
union {
31
+
u32 dw[PCIE_STD_MAX_TLP_HEADERLOG];
32
+
struct {
33
+
u32 _do_not_use[PCIE_STD_NUM_TLP_HEADERLOG];
34
+
u32 prefix[PCIE_STD_MAX_TLP_PREFIXLOG];
35
+
};
36
+
};
37
+
u8 header_len; /* Length of the Logged TLP Header in DWORDs */
38
+
bool flit; /* TLP was logged when in Flit mode */
31
39
};
32
40
33
41
struct aer_capability_regs {
+2
include/linux/device.h
+2
include/linux/device.h
···
1083
1083
void set_primary_fwnode(struct device *dev, struct fwnode_handle *fwnode);
1084
1084
void set_secondary_fwnode(struct device *dev, struct fwnode_handle *fwnode);
1085
1085
void device_set_node(struct device *dev, struct fwnode_handle *fwnode);
1086
+
int device_add_of_node(struct device *dev, struct device_node *of_node);
1087
+
void device_remove_of_node(struct device *dev);
1086
1088
void device_set_of_node_from_dev(struct device *dev, const struct device *dev2);
1087
1089
1088
1090
static inline struct device_node *dev_of_node(struct device *dev)
+7
-1
include/linux/pci-epc.h
+7
-1
include/linux/pci-epc.h
···
188
188
* enum pci_epc_bar_type - configurability of endpoint BAR
189
189
* @BAR_PROGRAMMABLE: The BAR mask can be configured by the EPC.
190
190
* @BAR_FIXED: The BAR mask is fixed by the hardware.
191
+
* @BAR_RESIZABLE: The BAR implements the PCI-SIG Resizable BAR Capability.
192
+
* NOTE: An EPC driver can currently only set a single supported
193
+
* size.
191
194
* @BAR_RESERVED: The BAR should not be touched by an EPF driver.
192
195
*/
193
196
enum pci_epc_bar_type {
194
197
BAR_PROGRAMMABLE = 0,
195
198
BAR_FIXED,
199
+
BAR_RESIZABLE,
196
200
BAR_RESERVED,
197
201
};
198
202
···
225
221
* @linkup_notifier: indicate if the EPC device can notify EPF driver on link up
226
222
* @msi_capable: indicate if the endpoint function has MSI capability
227
223
* @msix_capable: indicate if the endpoint function has MSI-X capability
224
+
* @intx_capable: indicate if the endpoint can raise INTx interrupts
228
225
* @bar: array specifying the hardware description for each BAR
229
226
* @align: alignment size required for BAR buffer allocation
230
227
*/
···
233
228
unsigned int linkup_notifier : 1;
234
229
unsigned int msi_capable : 1;
235
230
unsigned int msix_capable : 1;
231
+
unsigned int intx_capable : 1;
236
232
struct pci_epc_bar_desc bar[PCI_STD_NUM_BARS];
237
233
size_t align;
238
234
};
···
263
257
struct pci_epc *
264
258
__pci_epc_create(struct device *dev, const struct pci_epc_ops *ops,
265
259
struct module *owner);
266
-
void devm_pci_epc_destroy(struct device *dev, struct pci_epc *epc);
267
260
void pci_epc_destroy(struct pci_epc *epc);
268
261
int pci_epc_add_epf(struct pci_epc *epc, struct pci_epf *epf,
269
262
enum pci_epc_interface_type type);
···
276
271
enum pci_epc_interface_type type);
277
272
int pci_epc_write_header(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
278
273
struct pci_epf_header *hdr);
274
+
int pci_epc_bar_size_to_rebar_cap(size_t size, u32 *cap);
279
275
int pci_epc_set_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
280
276
struct pci_epf_bar *epf_bar);
281
277
void pci_epc_clear_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
+9
-8
include/linux/pci-epf.h
+9
-8
include/linux/pci-epf.h
···
38
38
* @baseclass_code: broadly classifies the type of function the device performs
39
39
* @cache_line_size: specifies the system cacheline size in units of DWORDs
40
40
* @subsys_vendor_id: vendor of the add-in card or subsystem
41
-
* @subsys_id: id specific to vendor
41
+
* @subsys_id: ID specific to vendor
42
42
* @interrupt_pin: interrupt pin the device (or device function) uses
43
43
*/
44
44
struct pci_epf_header {
···
59
59
* @bind: ops to perform when a EPC device has been bound to EPF device
60
60
* @unbind: ops to perform when a binding has been lost between a EPC device
61
61
* and EPF device
62
-
* @add_cfs: ops to initialize function specific configfs attributes
62
+
* @add_cfs: ops to initialize function-specific configfs attributes
63
63
*/
64
64
struct pci_epf_ops {
65
65
int (*bind)(struct pci_epf *epf);
···
138
138
* @epc: the EPC device to which this EPF device is bound
139
139
* @epf_pf: the physical EPF device to which this virtual EPF device is bound
140
140
* @driver: the EPF driver to which this EPF device is bound
141
-
* @id: Pointer to the EPF device ID
141
+
* @id: pointer to the EPF device ID
142
142
* @list: to add pci_epf as a list of PCI endpoint functions to pci_epc
143
143
* @lock: mutex to protect pci_epf_ops
144
144
* @sec_epc: the secondary EPC device to which this EPF device is bound
···
151
151
* @is_vf: true - virtual function, false - physical function
152
152
* @vfunction_num_map: bitmap to manage virtual function number
153
153
* @pci_vepf: list of virtual endpoint functions associated with this function
154
-
* @event_ops: Callbacks for capturing the EPC events
154
+
* @event_ops: callbacks for capturing the EPC events
155
155
*/
156
156
struct pci_epf {
157
157
struct device dev;
···
185
185
};
186
186
187
187
/**
188
-
* struct pci_epf_msix_tbl - represents the MSIX table entry structure
189
-
* @msg_addr: Writes to this address will trigger MSIX interrupt in host
190
-
* @msg_data: Data that should be written to @msg_addr to trigger MSIX interrupt
188
+
* struct pci_epf_msix_tbl - represents the MSI-X table entry structure
189
+
* @msg_addr: Writes to this address will trigger MSI-X interrupt in host
190
+
* @msg_data: Data that should be written to @msg_addr to trigger MSI-X
191
+
* interrupt
191
192
* @vector_ctrl: Identifies if the function is prohibited from sending a message
192
-
* using this MSIX table entry
193
+
* using this MSI-X table entry
193
194
*/
194
195
struct pci_epf_msix_tbl {
195
196
u64 msg_addr;
+3
-11
include/linux/pci.h
+3
-11
include/linux/pci.h
···
353
353
struct pci_dev *rcec; /* Associated RCEC device */
354
354
#endif
355
355
u32 devcap; /* PCIe Device Capabilities */
356
+
u16 rebar_cap; /* Resizable BAR capability offset */
356
357
u8 pcie_cap; /* PCIe capability offset */
357
358
u8 msi_cap; /* MSI capability offset */
358
359
u8 msix_cap; /* MSI-X capability offset */
···
477
476
unsigned int no_command_memory:1; /* No PCI_COMMAND_MEMORY */
478
477
unsigned int rom_bar_overlap:1; /* ROM BAR disable broken */
479
478
unsigned int rom_attr_enabled:1; /* Display of ROM attribute enabled? */
479
+
unsigned int non_mappable_bars:1; /* BARs can't be mapped to user-space */
480
480
pci_dev_flags_t dev_flags;
481
481
atomic_t enable_cnt; /* pci_enable_device has been called */
482
482
···
683
681
struct bin_attribute *legacy_mem; /* Legacy mem */
684
682
unsigned int is_added:1;
685
683
unsigned int unsafe_warn:1; /* warned about RW1C config write */
684
+
unsigned int flit_mode:1; /* Link in Flit mode */
686
685
};
687
686
688
687
#define to_pci_bus(n) container_of(n, struct pci_bus, dev)
···
1399
1396
void pcibios_reset_secondary_bus(struct pci_dev *dev);
1400
1397
void pci_update_resource(struct pci_dev *dev, int resno);
1401
1398
int __must_check pci_assign_resource(struct pci_dev *dev, int i);
1402
-
int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align);
1403
1399
void pci_release_resource(struct pci_dev *dev, int resno);
1404
1400
static inline int pci_rebar_bytes_to_size(u64 bytes)
1405
1401
{
···
1457
1455
void set_pcie_hotplug_bridge(struct pci_dev *pdev);
1458
1456
1459
1457
/* Functions for PCI Hotplug drivers to use */
1460
-
unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge);
1461
1458
unsigned int pci_rescan_bus(struct pci_bus *bus);
1462
1459
void pci_lock_rescan_remove(void);
1463
1460
void pci_unlock_rescan_remove(void);
···
1478
1477
void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge);
1479
1478
void pci_assign_unassigned_bus_resources(struct pci_bus *bus);
1480
1479
void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus);
1481
-
int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long type);
1482
1480
int pci_enable_resources(struct pci_dev *, int mask);
1483
1481
void pci_assign_irq(struct pci_dev *dev);
1484
1482
struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res);
···
1637
1637
void *userdata);
1638
1638
int pci_cfg_space_size(struct pci_dev *dev);
1639
1639
unsigned char pci_bus_max_busnr(struct pci_bus *bus);
1640
-
void pci_setup_bridge(struct pci_bus *bus);
1641
1640
resource_size_t pcibios_window_alignment(struct pci_bus *bus,
1642
1641
unsigned long type);
1643
1642
···
2335
2336
#define PCIPCI_ALIMAGIK 32 /* Need low latency setting */
2336
2337
#define PCIAGP_FAIL 64 /* No PCI to AGP DMA */
2337
2338
2338
-
extern unsigned long pci_cardbus_io_size;
2339
-
extern unsigned long pci_cardbus_mem_size;
2340
2339
extern u8 pci_dfl_cache_line_size;
2341
2340
extern u8 pci_cache_line_size;
2342
2341
···
2442
2445
static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno)
2443
2446
{ return 0; }
2444
2447
static inline void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe) { }
2445
-
#endif
2446
-
2447
-
#if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
2448
-
void pci_hp_create_module_link(struct pci_slot *pci_slot);
2449
-
void pci_hp_remove_module_link(struct pci_slot *pci_slot);
2450
2448
#endif
2451
2449
2452
2450
/**
-2
include/linux/pci_hotplug.h
-2
include/linux/pci_hotplug.h
···
50
50
/**
51
51
* struct hotplug_slot - used to register a physical slot with the hotplug pci core
52
52
* @ops: pointer to the &struct hotplug_slot_ops to be used for this slot
53
-
* @slot_list: internal list used to track hotplug PCI slots
54
53
* @pci_slot: represents a physical slot
55
54
* @owner: The module owner of this structure
56
55
* @mod_name: The module name (KBUILD_MODNAME) of this structure
···
58
59
const struct hotplug_slot_ops *ops;
59
60
60
61
/* Variables below this are for use only by the hotplug pci core. */
61
-
struct list_head slot_list;
62
62
struct pci_slot *pci_slot;
63
63
struct module *owner;
64
64
const char *mod_name;
+3
include/linux/pci_ids.h
+3
include/linux/pci_ids.h
···
518
518
#define PCI_DEVICE_ID_IBM_ICOM_V2_ONE_PORT_RVX_ONE_PORT_MDM 0x0251
519
519
#define PCI_DEVICE_ID_IBM_ICOM_V2_ONE_PORT_RVX_ONE_PORT_MDM_PCIE 0x0361
520
520
#define PCI_DEVICE_ID_IBM_ICOM_FOUR_PORT_MODEL 0x252
521
+
#define PCI_DEVICE_ID_IBM_ISM 0x04ed
521
522
522
523
#define PCI_SUBVENDOR_ID_IBM 0x1014
523
524
#define PCI_SUBDEVICE_ID_IBM_SATURN_SERIAL_ONE_PORT 0x03d4
···
2610
2609
#define PCI_VENDOR_ID_AMAZON 0x1d0f
2611
2610
2612
2611
#define PCI_VENDOR_ID_ZHAOXIN 0x1d17
2612
+
2613
+
#define PCI_VENDOR_ID_ROCKCHIP 0x1d87
2613
2614
2614
2615
#define PCI_VENDOR_ID_HYGON 0x1d94
2615
2616
+38
include/linux/pcie-dwc.h
+38
include/linux/pcie-dwc.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0 */
2
+
/*
3
+
* Copyright (C) 2021-2023 Alibaba Inc.
4
+
* Copyright (C) 2025 Linaro Ltd.
5
+
*
6
+
* Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
7
+
*/
8
+
9
+
#ifndef LINUX_PCIE_DWC_H
10
+
#define LINUX_PCIE_DWC_H
11
+
12
+
#include <linux/pci_ids.h>
13
+
14
+
struct dwc_pcie_vsec_id {
15
+
u16 vendor_id;
16
+
u16 vsec_id;
17
+
u8 vsec_rev;
18
+
};
19
+
20
+
/*
21
+
* VSEC IDs are allocated by the vendor, so a given ID may mean different
22
+
* things to different vendors. See PCIe r6.0, sec 7.9.5.2.
23
+
*/
24
+
static const struct dwc_pcie_vsec_id dwc_pcie_rasdes_vsec_ids[] = {
25
+
{ .vendor_id = PCI_VENDOR_ID_ALIBABA,
26
+
.vsec_id = 0x02, .vsec_rev = 0x4 },
27
+
{ .vendor_id = PCI_VENDOR_ID_AMPERE,
28
+
.vsec_id = 0x02, .vsec_rev = 0x4 },
29
+
{ .vendor_id = PCI_VENDOR_ID_QCOM,
30
+
.vsec_id = 0x02, .vsec_rev = 0x4 },
31
+
{ .vendor_id = PCI_VENDOR_ID_ROCKCHIP,
32
+
.vsec_id = 0x02, .vsec_rev = 0x4 },
33
+
{ .vendor_id = PCI_VENDOR_ID_SAMSUNG,
34
+
.vsec_id = 0x02, .vsec_rev = 0x4 },
35
+
{}
36
+
};
37
+
38
+
#endif /* LINUX_PCIE_DWC_H */
+6
-6
include/ras/ras_event.h
+6
-6
include/ras/ras_event.h
···
309
309
__field( u32, status )
310
310
__field( u8, severity )
311
311
__field( u8, tlp_header_valid)
312
-
__array( u32, tlp_header, 4 )
312
+
__array( u32, tlp_header, PCIE_STD_MAX_TLP_HEADERLOG)
313
313
),
314
314
315
315
TP_fast_assign(
···
318
318
__entry->severity = severity;
319
319
__entry->tlp_header_valid = tlp_header_valid;
320
320
if (tlp_header_valid) {
321
-
__entry->tlp_header[0] = tlp->dw[0];
322
-
__entry->tlp_header[1] = tlp->dw[1];
323
-
__entry->tlp_header[2] = tlp->dw[2];
324
-
__entry->tlp_header[3] = tlp->dw[3];
321
+
int i;
322
+
323
+
for (i = 0; i < PCIE_STD_MAX_TLP_HEADERLOG; i++)
324
+
__entry->tlp_header[i] = tlp->dw[i];
325
325
}
326
326
),
327
327
···
334
334
__print_flags(__entry->status, "|", aer_correctable_errors) :
335
335
__print_flags(__entry->status, "|", aer_uncorrectable_errors),
336
336
__entry->tlp_header_valid ?
337
-
__print_array(__entry->tlp_header, 4, 4) :
337
+
__print_array(__entry->tlp_header, PCIE_STD_MAX_TLP_HEADERLOG, 4) :
338
338
"Not available")
339
339
);
340
340
+10
-3
include/uapi/linux/pci_regs.h
+10
-3
include/uapi/linux/pci_regs.h
···
486
486
#define PCI_EXP_TYPE_RC_EC 0xa /* Root Complex Event Collector */
487
487
#define PCI_EXP_FLAGS_SLOT 0x0100 /* Slot implemented */
488
488
#define PCI_EXP_FLAGS_IRQ 0x3e00 /* Interrupt message number */
489
+
#define PCI_EXP_FLAGS_FLIT 0x8000 /* Flit Mode Supported */
489
490
#define PCI_EXP_DEVCAP 0x04 /* Device capabilities */
490
491
#define PCI_EXP_DEVCAP_PAYLOAD 0x00000007 /* Max_Payload_Size */
491
492
#define PCI_EXP_DEVCAP_PHANTOM 0x00000018 /* Phantom functions */
···
796
795
#define PCI_ERR_CAP_ECRC_CHKC 0x00000080 /* ECRC Check Capable */
797
796
#define PCI_ERR_CAP_ECRC_CHKE 0x00000100 /* ECRC Check Enable */
798
797
#define PCI_ERR_CAP_PREFIX_LOG_PRESENT 0x00000800 /* TLP Prefix Log Present */
798
+
#define PCI_ERR_CAP_TLP_LOG_FLIT 0x00040000 /* TLP was logged in Flit Mode */
799
+
#define PCI_ERR_CAP_TLP_LOG_SIZE 0x00f80000 /* Logged TLP Size (only in Flit mode) */
799
800
#define PCI_ERR_HEADER_LOG 0x1c /* Header Log Register (16 bytes) */
800
801
#define PCI_ERR_ROOT_COMMAND 0x2c /* Root Error Command */
801
802
#define PCI_ERR_ROOT_CMD_COR_EN 0x00000001 /* Correctable Err Reporting Enable */
···
1016
1013
1017
1014
/* Resizable BARs */
1018
1015
#define PCI_REBAR_CAP 4 /* capability register */
1019
-
#define PCI_REBAR_CAP_SIZES 0x00FFFFF0 /* supported BAR sizes */
1016
+
#define PCI_REBAR_CAP_SIZES 0xFFFFFFF0 /* supported BAR sizes */
1020
1017
#define PCI_REBAR_CTRL 8 /* control register */
1021
1018
#define PCI_REBAR_CTRL_BAR_IDX 0x00000007 /* BAR index */
1022
1019
#define PCI_REBAR_CTRL_NBAR_MASK 0x000000E0 /* # of resizable BARs */
···
1064
1061
#define PCI_EXP_DPC_CAP_RP_EXT 0x0020 /* Root Port Extensions */
1065
1062
#define PCI_EXP_DPC_CAP_POISONED_TLP 0x0040 /* Poisoned TLP Egress Blocking Supported */
1066
1063
#define PCI_EXP_DPC_CAP_SW_TRIGGER 0x0080 /* Software Triggering Supported */
1067
-
#define PCI_EXP_DPC_RP_PIO_LOG_SIZE 0x0F00 /* RP PIO Log Size */
1064
+
#define PCI_EXP_DPC_RP_PIO_LOG_SIZE 0x0F00 /* RP PIO Log Size [3:0] */
1068
1065
#define PCI_EXP_DPC_CAP_DL_ACTIVE 0x1000 /* ERR_COR signal on DL_Active supported */
1066
+
#define PCI_EXP_DPC_RP_PIO_LOG_SIZE4 0x2000 /* RP PIO Log Size [4] */
1069
1067
1070
1068
#define PCI_EXP_DPC_CTL 0x06 /* DPC control */
1071
1069
#define PCI_EXP_DPC_CTL_EN_FATAL 0x0001 /* Enable trigger on ERR_FATAL message */
···
1209
1205
#define PCI_DOE_DATA_OBJECT_DISC_REQ_3_INDEX 0x000000ff
1210
1206
#define PCI_DOE_DATA_OBJECT_DISC_REQ_3_VER 0x0000ff00
1211
1207
#define PCI_DOE_DATA_OBJECT_DISC_RSP_3_VID 0x0000ffff
1212
-
#define PCI_DOE_DATA_OBJECT_DISC_RSP_3_PROTOCOL 0x00ff0000
1208
+
#define PCI_DOE_DATA_OBJECT_DISC_RSP_3_TYPE 0x00ff0000
1213
1209
#define PCI_DOE_DATA_OBJECT_DISC_RSP_3_NEXT_INDEX 0xff000000
1210
+
1211
+
/* Deprecated old name, replaced with PCI_DOE_DATA_OBJECT_DISC_RSP_3_TYPE */
1212
+
#define PCI_DOE_DATA_OBJECT_DISC_RSP_3_PROTOCOL PCI_DOE_DATA_OBJECT_DISC_RSP_3_TYPE
1214
1213
1215
1214
/* Compute Express Link (CXL r3.1, sec 8.1.5) */
1216
1215
#define PCI_DVSEC_CXL_PORT 3
+6
include/uapi/linux/pcitest.h
+6
include/uapi/linux/pcitest.h
···
23
23
#define PCITEST_BARS _IO('P', 0xa)
24
24
#define PCITEST_CLEAR_IRQ _IO('P', 0x10)
25
25
26
+
#define PCITEST_IRQ_TYPE_UNDEFINED -1
27
+
#define PCITEST_IRQ_TYPE_INTX 0
28
+
#define PCITEST_IRQ_TYPE_MSI 1
29
+
#define PCITEST_IRQ_TYPE_MSIX 2
30
+
#define PCITEST_IRQ_TYPE_AUTO 3
31
+
26
32
#define PCITEST_FLAGS_USE_DMA 0x00000001
27
33
28
34
struct pci_endpoint_test_xfer_param {
+6
-7
tools/Makefile
+6
-7
tools/Makefile
···
25
25
@echo ' leds - LEDs tools'
26
26
@echo ' nolibc - nolibc headers testing and installation'
27
27
@echo ' objtool - an ELF object analysis tool'
28
-
@echo ' pci - PCI tools'
29
28
@echo ' perf - Linux performance measurement and analysis tool'
30
29
@echo ' selftests - various kernel selftests'
31
30
@echo ' sched_ext - sched_ext example schedulers'
···
68
69
cpupower: FORCE
69
70
$(call descend,power/$@)
70
71
71
-
counter firewire hv guest bootconfig spi usb virtio mm bpf iio gpio objtool leds wmi pci firmware debugging tracing: FORCE
72
+
counter firewire hv guest bootconfig spi usb virtio mm bpf iio gpio objtool leds wmi firmware debugging tracing: FORCE
72
73
$(call descend,$@)
73
74
74
75
bpf/%: FORCE
···
122
123
perf selftests bootconfig spi turbostat usb \
123
124
virtio mm bpf x86_energy_perf_policy \
124
125
tmon freefall iio objtool kvm_stat wmi \
125
-
pci debugging tracing thermal thermometer thermal-engine
126
+
debugging tracing thermal thermometer thermal-engine
126
127
127
128
acpi_install:
128
129
$(call descend,power/$(@:_install=),install)
···
130
131
cpupower_install:
131
132
$(call descend,power/$(@:_install=),install)
132
133
133
-
counter_install firewire_install gpio_install hv_install iio_install perf_install bootconfig_install spi_install usb_install virtio_install mm_install bpf_install objtool_install wmi_install pci_install debugging_install tracing_install:
134
+
counter_install firewire_install gpio_install hv_install iio_install perf_install bootconfig_install spi_install usb_install virtio_install mm_install bpf_install objtool_install wmi_install debugging_install tracing_install:
134
135
$(call descend,$(@:_install=),install)
135
136
136
137
selftests_install:
···
162
163
perf_install selftests_install turbostat_install usb_install \
163
164
virtio_install mm_install bpf_install x86_energy_perf_policy_install \
164
165
tmon_install freefall_install objtool_install kvm_stat_install \
165
-
wmi_install pci_install debugging_install intel-speed-select_install \
166
+
wmi_install debugging_install intel-speed-select_install \
166
167
tracing_install thermometer_install thermal-engine_install
167
168
168
169
acpi_clean:
···
171
172
cpupower_clean:
172
173
$(call descend,power/cpupower,clean)
173
174
174
-
counter_clean hv_clean firewire_clean bootconfig_clean spi_clean usb_clean virtio_clean mm_clean wmi_clean bpf_clean iio_clean gpio_clean objtool_clean leds_clean pci_clean firmware_clean debugging_clean tracing_clean:
175
+
counter_clean hv_clean firewire_clean bootconfig_clean spi_clean usb_clean virtio_clean mm_clean wmi_clean bpf_clean iio_clean gpio_clean objtool_clean leds_clean firmware_clean debugging_clean tracing_clean:
175
176
$(call descend,$(@:_clean=),clean)
176
177
177
178
libapi_clean:
···
218
219
perf_clean selftests_clean turbostat_clean bootconfig_clean spi_clean usb_clean virtio_clean \
219
220
mm_clean bpf_clean iio_clean x86_energy_perf_policy_clean tmon_clean \
220
221
freefall_clean build_clean libbpf_clean libsubcmd_clean \
221
-
gpio_clean objtool_clean leds_clean wmi_clean pci_clean firmware_clean debugging_clean \
222
+
gpio_clean objtool_clean leds_clean wmi_clean firmware_clean debugging_clean \
222
223
intel-speed-select_clean tracing_clean thermal_clean thermometer_clean thermal-engine_clean \
223
224
sched_ext_clean
224
225
+21
-10
tools/testing/selftests/pci_endpoint/pci_endpoint_test.c
+21
-10
tools/testing/selftests/pci_endpoint/pci_endpoint_test.c
···
25
25
#define pci_ep_ioctl(cmd, arg) \
26
26
({ \
27
27
ret = ioctl(self->fd, cmd, arg); \
28
-
ret = ret < 0 ? -errno : 0; \
28
+
ret = ret < 0 ? -errno : ret; \
29
29
})
30
30
31
31
static const char *test_device = "/dev/pci-endpoint-test.0";
···
65
65
int ret;
66
66
67
67
pci_ep_ioctl(PCITEST_BAR, variant->barno);
68
+
if (ret == -ENODATA)
69
+
SKIP(return, "BAR is disabled");
68
70
EXPECT_FALSE(ret) TH_LOG("Test failed for BAR%d", variant->barno);
69
71
}
70
72
···
99
97
{
100
98
int ret;
101
99
102
-
pci_ep_ioctl(PCITEST_SET_IRQTYPE, 0);
100
+
pci_ep_ioctl(PCITEST_SET_IRQTYPE, PCITEST_IRQ_TYPE_INTX);
103
101
ASSERT_EQ(0, ret) TH_LOG("Can't set Legacy IRQ type");
102
+
103
+
pci_ep_ioctl(PCITEST_GET_IRQTYPE, 0);
104
+
ASSERT_EQ(PCITEST_IRQ_TYPE_INTX, ret) TH_LOG("Can't get Legacy IRQ type");
104
105
105
106
pci_ep_ioctl(PCITEST_LEGACY_IRQ, 0);
106
107
EXPECT_FALSE(ret) TH_LOG("Test failed for Legacy IRQ");
···
113
108
{
114
109
int ret, i;
115
110
116
-
pci_ep_ioctl(PCITEST_SET_IRQTYPE, 1);
111
+
pci_ep_ioctl(PCITEST_SET_IRQTYPE, PCITEST_IRQ_TYPE_MSI);
117
112
ASSERT_EQ(0, ret) TH_LOG("Can't set MSI IRQ type");
113
+
114
+
pci_ep_ioctl(PCITEST_GET_IRQTYPE, 0);
115
+
ASSERT_EQ(PCITEST_IRQ_TYPE_MSI, ret) TH_LOG("Can't get MSI IRQ type");
118
116
119
117
for (i = 1; i <= 32; i++) {
120
118
pci_ep_ioctl(PCITEST_MSI, i);
···
129
121
{
130
122
int ret, i;
131
123
132
-
pci_ep_ioctl(PCITEST_SET_IRQTYPE, 2);
124
+
pci_ep_ioctl(PCITEST_SET_IRQTYPE, PCITEST_IRQ_TYPE_MSIX);
133
125
ASSERT_EQ(0, ret) TH_LOG("Can't set MSI-X IRQ type");
126
+
127
+
pci_ep_ioctl(PCITEST_GET_IRQTYPE, 0);
128
+
ASSERT_EQ(PCITEST_IRQ_TYPE_MSIX, ret) TH_LOG("Can't get MSI-X IRQ type");
134
129
135
130
for (i = 1; i <= 2048; i++) {
136
131
pci_ep_ioctl(PCITEST_MSIX, i);
···
181
170
if (variant->use_dma)
182
171
param.flags = PCITEST_FLAGS_USE_DMA;
183
172
184
-
pci_ep_ioctl(PCITEST_SET_IRQTYPE, 1);
185
-
ASSERT_EQ(0, ret) TH_LOG("Can't set MSI IRQ type");
173
+
pci_ep_ioctl(PCITEST_SET_IRQTYPE, PCITEST_IRQ_TYPE_AUTO);
174
+
ASSERT_EQ(0, ret) TH_LOG("Can't set AUTO IRQ type");
186
175
187
176
for (i = 0; i < ARRAY_SIZE(test_size); i++) {
188
177
param.size = test_size[i];
···
200
189
if (variant->use_dma)
201
190
param.flags = PCITEST_FLAGS_USE_DMA;
202
191
203
-
pci_ep_ioctl(PCITEST_SET_IRQTYPE, 1);
204
-
ASSERT_EQ(0, ret) TH_LOG("Can't set MSI IRQ type");
192
+
pci_ep_ioctl(PCITEST_SET_IRQTYPE, PCITEST_IRQ_TYPE_AUTO);
193
+
ASSERT_EQ(0, ret) TH_LOG("Can't set AUTO IRQ type");
205
194
206
195
for (i = 0; i < ARRAY_SIZE(test_size); i++) {
207
196
param.size = test_size[i];
···
219
208
if (variant->use_dma)
220
209
param.flags = PCITEST_FLAGS_USE_DMA;
221
210
222
-
pci_ep_ioctl(PCITEST_SET_IRQTYPE, 1);
223
-
ASSERT_EQ(0, ret) TH_LOG("Can't set MSI IRQ type");
211
+
pci_ep_ioctl(PCITEST_SET_IRQTYPE, PCITEST_IRQ_TYPE_AUTO);
212
+
ASSERT_EQ(0, ret) TH_LOG("Can't set AUTO IRQ type");
224
213
225
214
for (i = 0; i < ARRAY_SIZE(test_size); i++) {
226
215
param.size = test_size[i];