Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux
Pull arm64 fixes from Catalin Marinas:
"A couple of last-minute arm64 fixes for 4.8:
- Fix secondary CPU to NUMA node assignment
- Fix kgdb breakpoint insertion in read-only text sections (when
CONFIG_DEBUG_RODATA or CONFIG_DEBUG_SET_MODULE_RONX are enabled)"
* tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux:
arm64: kgdb: handle read-only text / modules
arm64: Call numa_store_cpu_info() earlier.
+30
-22
-2
arch/arm64/include/asm/debug-monitors.h
-2
arch/arm64/include/asm/debug-monitors.h
+24
-12
arch/arm64/kernel/kgdb.c
+24
-12
arch/arm64/kernel/kgdb.c
···
19
19
* along with this program. If not, see <http://www.gnu.org/licenses/>.
20
20
*/
21
21
22
+
#include <linux/bug.h>
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23
#include <linux/irq.h>
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24
#include <linux/kdebug.h>
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#include <linux/kgdb.h>
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26
#include <linux/kprobes.h>
27
+
#include <asm/debug-monitors.h>
28
+
#include <asm/insn.h>
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29
#include <asm/traps.h>
27
30
28
31
struct dbg_reg_def_t dbg_reg_def[DBG_MAX_REG_NUM] = {
···
341
338
unregister_die_notifier(&kgdb_notifier);
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}
343
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-
/*
345
-
* ARM instructions are always in LE.
346
-
* Break instruction is encoded in LE format
347
-
*/
348
-
struct kgdb_arch arch_kgdb_ops = {
349
-
.gdb_bpt_instr = {
350
-
KGDB_DYN_BRK_INS_BYTE(0),
351
-
KGDB_DYN_BRK_INS_BYTE(1),
352
-
KGDB_DYN_BRK_INS_BYTE(2),
353
-
KGDB_DYN_BRK_INS_BYTE(3),
354
-
}
355
-
};
341
+
struct kgdb_arch arch_kgdb_ops;
342
+
343
+
int kgdb_arch_set_breakpoint(struct kgdb_bkpt *bpt)
344
+
{
345
+
int err;
346
+
347
+
BUILD_BUG_ON(AARCH64_INSN_SIZE != BREAK_INSTR_SIZE);
348
+
349
+
err = aarch64_insn_read((void *)bpt->bpt_addr, (u32 *)bpt->saved_instr);
350
+
if (err)
351
+
return err;
352
+
353
+
return aarch64_insn_write((void *)bpt->bpt_addr,
354
+
(u32)AARCH64_BREAK_KGDB_DYN_DBG);
355
+
}
356
+
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+
int kgdb_arch_remove_breakpoint(struct kgdb_bkpt *bpt)
358
+
{
359
+
return aarch64_insn_write((void *)bpt->bpt_addr,
360
+
*(u32 *)bpt->saved_instr);
361
+
}
+6
-8
arch/arm64/kernel/smp.c
+6
-8
arch/arm64/kernel/smp.c
···
201
201
return ret;
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202
}
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204
-
static void smp_store_cpu_info(unsigned int cpuid)
205
-
{
206
-
store_cpu_topology(cpuid);
207
-
numa_store_cpu_info(cpuid);
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-
}
209
-
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/*
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205
* This is the secondary CPU boot entry. We're using this CPUs
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* idle thread stack, but a set of temporary page tables.
···
248
254
*/
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255
notify_cpu_starting(cpu);
250
256
251
-
smp_store_cpu_info(cpu);
257
+
store_cpu_topology(cpu);
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258
253
259
/*
254
260
* OK, now it's safe to let the boot CPU continue. Wait for
···
683
689
{
684
690
int err;
685
691
unsigned int cpu;
692
+
unsigned int this_cpu;
686
693
687
694
init_cpu_topology();
688
695
689
-
smp_store_cpu_info(smp_processor_id());
696
+
this_cpu = smp_processor_id();
697
+
store_cpu_topology(this_cpu);
698
+
numa_store_cpu_info(this_cpu);
690
699
691
700
/*
692
701
* If UP is mandated by "nosmp" (which implies "maxcpus=0"), don't set
···
716
719
continue;
717
720
718
721
set_cpu_present(cpu, true);
722
+
numa_store_cpu_info(cpu);
719
723
}
720
724
}
721
725