spi: aspeed: Improve clock, timing and address

Merge series from Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>:

This patch series introduces several improvements to the
ASPEED SPI driver, targeting better stability, compatibility
and, flexibility across multiple ASPEED platforms.

Key changes include:

* Clock selection strategy update
Improves fallback logic when timing calibration is skipped or
fails, ensuring reliable boot behavior.

* Timing calibration enhancement for AST2600
Replaces the previous "first-pass" strategy with a more robust
algorithm that selects the optimal timing point.

* Default address decoding assignment
Ensures each chip select (CS) has a valid decoding range during
probe, avoiding detection failures due to missing or incorrect
bootloader setup.

* Centralized address decoding management
Refactors the decoding logic to centrally assign address windows,
preventing improper trimming and improving layout flexibility.

* Per-platform decoding adjustment
Introduces platform-specific `adjust_window` callbacks to handle
platform specific hardware constraints for address decoding range.

* Selective memory mapping
Optimizes memory usage by mapping only the required address window
per CS to avoid exhaustion.