Merge tag 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/rdma/rdma

+30 -13

drivers/infiniband/core/rw.c

··· 608 608 if (rdma_rw_io_needs_mr(qp->device, port_num, dir, sg_cnt)) { 609 609 ret = rdma_rw_init_mr_wrs(ctx, qp, port_num, sg, sg_cnt, 610 610 sg_offset, remote_addr, rkey, dir); 611 - } else if (sg_cnt > 1) { 612 - ret = rdma_rw_init_map_wrs(ctx, qp, sg, sg_cnt, sg_offset, 613 - remote_addr, rkey, dir); 614 - } else { 615 - ret = rdma_rw_init_single_wr(ctx, qp, sg, sg_offset, 616 - remote_addr, rkey, dir); 611 + /* 612 + * If MR init succeeded or failed for a reason other 613 + * than pool exhaustion, that result is final. 614 + * 615 + * Pool exhaustion (-EAGAIN) from the max_sgl_rd 616 + * optimization is recoverable: fall back to 617 + * direct SGE posting. iWARP and force_mr require 618 + * MRs unconditionally, so -EAGAIN is terminal. 619 + */ 620 + if (ret != -EAGAIN || 621 + rdma_protocol_iwarp(qp->device, port_num) || 622 + unlikely(rdma_rw_force_mr)) 623 + goto out; 617 624 } 618 625 626 + if (sg_cnt > 1) 627 + ret = rdma_rw_init_map_wrs(ctx, qp, sg, sg_cnt, sg_offset, 628 + remote_addr, rkey, dir); 629 + else 630 + ret = rdma_rw_init_single_wr(ctx, qp, sg, sg_offset, 631 + remote_addr, rkey, dir); 632 + 633 + out: 619 634 if (ret < 0) 620 635 goto out_unmap_sg; 621 636 return ret; ··· 701 686 return ret; 702 687 703 688 /* 704 - * IOVA mapping not available. Check if MR registration provides 705 - * better performance than multiple SGE entries. 689 + * IOVA not available; fall back to the map_wrs path, which maps 690 + * each bvec as a direct SGE. This is always correct: the MR path 691 + * is a throughput optimization, not a correctness requirement. 692 + * (iWARP, which does require MRs, is handled by the check above.) 693 + * 694 + * The rdma_rw_io_needs_mr() gate is not used here because nr_bvec 695 + * is a raw page count that overstates DMA entry demand -- the bvec 696 + * caller has no post-DMA-coalescing segment count, and feeding the 697 + * inflated count into the MR path exhausts the pool on RDMA READs. 706 698 */ 707 - if (rdma_rw_io_needs_mr(dev, port_num, dir, nr_bvec)) 708 - return rdma_rw_init_mr_wrs_bvec(ctx, qp, port_num, bvecs, 709 - nr_bvec, &iter, remote_addr, 710 - rkey, dir); 711 - 712 699 return rdma_rw_init_map_wrs_bvec(ctx, qp, bvecs, nr_bvec, &iter, 713 700 remote_addr, rkey, dir); 714 701 }

+9 -5

drivers/infiniband/hw/bng_re/bng_dev.c

··· 210 210 return rc; 211 211 } 212 212 213 - static void bng_re_query_hwrm_version(struct bng_re_dev *rdev) 213 + static int bng_re_query_hwrm_version(struct bng_re_dev *rdev) 214 214 { 215 215 struct bnge_auxr_dev *aux_dev = rdev->aux_dev; 216 216 struct hwrm_ver_get_output ver_get_resp = {}; ··· 230 230 if (rc) { 231 231 ibdev_err(&rdev->ibdev, "Failed to query HW version, rc = 0x%x", 232 232 rc); 233 - return; 233 + return rc; 234 234 } 235 235 236 236 cctx = rdev->chip_ctx; ··· 244 244 245 245 if (!cctx->hwrm_cmd_max_timeout) 246 246 cctx->hwrm_cmd_max_timeout = BNG_ROCE_FW_MAX_TIMEOUT; 247 + 248 + return 0; 247 249 } 248 250 249 251 static void bng_re_dev_uninit(struct bng_re_dev *rdev) ··· 308 306 goto msix_ctx_fail; 309 307 } 310 308 311 - bng_re_query_hwrm_version(rdev); 309 + rc = bng_re_query_hwrm_version(rdev); 310 + if (rc) 311 + goto destroy_chip_ctx; 312 312 313 313 rc = bng_re_alloc_fw_channel(&rdev->bng_res, &rdev->rcfw); 314 314 if (rc) { 315 315 ibdev_err(&rdev->ibdev, 316 316 "Failed to allocate RCFW Channel: %#x\n", rc); 317 - goto alloc_fw_chl_fail; 317 + goto destroy_chip_ctx; 318 318 } 319 319 320 320 /* Allocate nq record memory */ ··· 395 391 kfree(rdev->nqr); 396 392 nq_alloc_fail: 397 393 bng_re_free_rcfw_channel(&rdev->rcfw); 398 - alloc_fw_chl_fail: 394 + destroy_chip_ctx: 399 395 bng_re_destroy_chip_ctx(rdev); 400 396 msix_ctx_fail: 401 397 bnge_unregister_dev(rdev->aux_dev);

+40 -48

drivers/infiniband/hw/efa/efa_com.c

··· 1 1 // SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause 2 2 /* 3 - * Copyright 2018-2025 Amazon.com, Inc. or its affiliates. All rights reserved. 3 + * Copyright 2018-2026 Amazon.com, Inc. or its affiliates. All rights reserved. 4 4 */ 5 5 6 6 #include <linux/log2.h> ··· 310 310 return &aq->comp_ctx[ctx_id]; 311 311 } 312 312 313 - static struct efa_comp_ctx *__efa_com_submit_admin_cmd(struct efa_com_admin_queue *aq, 314 - struct efa_admin_aq_entry *cmd, 315 - size_t cmd_size_in_bytes, 316 - struct efa_admin_acq_entry *comp, 317 - size_t comp_size_in_bytes) 313 + static void __efa_com_submit_admin_cmd(struct efa_com_admin_queue *aq, 314 + struct efa_comp_ctx *comp_ctx, 315 + struct efa_admin_aq_entry *cmd, 316 + size_t cmd_size_in_bytes, 317 + struct efa_admin_acq_entry *comp, 318 + size_t comp_size_in_bytes) 318 319 { 319 320 struct efa_admin_aq_entry *aqe; 320 - struct efa_comp_ctx *comp_ctx; 321 321 u16 queue_size_mask; 322 322 u16 cmd_id; 323 323 u16 ctx_id; 324 324 u16 pi; 325 - 326 - comp_ctx = efa_com_alloc_comp_ctx(aq); 327 - if (!comp_ctx) 328 - return ERR_PTR(-EINVAL); 329 325 330 326 queue_size_mask = aq->depth - 1; 331 327 pi = aq->sq.pc & queue_size_mask; ··· 356 360 357 361 /* barrier not needed in case of writel */ 358 362 writel(aq->sq.pc, aq->sq.db_addr); 359 - 360 - return comp_ctx; 361 363 } 362 364 363 365 static inline int efa_com_init_comp_ctxt(struct efa_com_admin_queue *aq) ··· 388 394 return 0; 389 395 } 390 396 391 - static struct efa_comp_ctx *efa_com_submit_admin_cmd(struct efa_com_admin_queue *aq, 392 - struct efa_admin_aq_entry *cmd, 393 - size_t cmd_size_in_bytes, 394 - struct efa_admin_acq_entry *comp, 395 - size_t comp_size_in_bytes) 397 + static int efa_com_submit_admin_cmd(struct efa_com_admin_queue *aq, 398 + struct efa_comp_ctx *comp_ctx, 399 + struct efa_admin_aq_entry *cmd, 400 + size_t cmd_size_in_bytes, 401 + struct efa_admin_acq_entry *comp, 402 + size_t comp_size_in_bytes) 396 403 { 397 - struct efa_comp_ctx *comp_ctx; 398 - 399 404 spin_lock(&aq->sq.lock); 400 405 if (!test_bit(EFA_AQ_STATE_RUNNING_BIT, &aq->state)) { 401 406 ibdev_err_ratelimited(aq->efa_dev, "Admin queue is closed\n"); 402 407 spin_unlock(&aq->sq.lock); 403 - return ERR_PTR(-ENODEV); 408 + return -ENODEV; 404 409 } 405 410 406 - comp_ctx = __efa_com_submit_admin_cmd(aq, cmd, cmd_size_in_bytes, comp, 407 - comp_size_in_bytes); 411 + __efa_com_submit_admin_cmd(aq, comp_ctx, cmd, cmd_size_in_bytes, comp, 412 + comp_size_in_bytes); 408 413 spin_unlock(&aq->sq.lock); 409 - if (IS_ERR(comp_ctx)) 410 - clear_bit(EFA_AQ_STATE_RUNNING_BIT, &aq->state); 411 414 412 - return comp_ctx; 415 + return 0; 413 416 } 414 417 415 418 static int efa_com_handle_single_admin_completion(struct efa_com_admin_queue *aq, ··· 503 512 { 504 513 unsigned long timeout; 505 514 unsigned long flags; 506 - int err; 507 515 508 516 timeout = jiffies + usecs_to_jiffies(aq->completion_timeout); 509 517 ··· 522 532 atomic64_inc(&aq->stats.no_completion); 523 533 524 534 clear_bit(EFA_AQ_STATE_RUNNING_BIT, &aq->state); 525 - err = -ETIME; 526 - goto out; 535 + return -ETIME; 527 536 } 528 537 529 538 msleep(aq->poll_interval); 530 539 } 531 540 532 - err = efa_com_comp_status_to_errno(comp_ctx->user_cqe->acq_common_descriptor.status); 533 - out: 534 - efa_com_dealloc_comp_ctx(aq, comp_ctx); 535 - return err; 541 + return efa_com_comp_status_to_errno( 542 + comp_ctx->user_cqe->acq_common_descriptor.status); 536 543 } 537 544 538 545 static int efa_com_wait_and_process_admin_cq_interrupts(struct efa_comp_ctx *comp_ctx, 539 546 struct efa_com_admin_queue *aq) 540 547 { 541 548 unsigned long flags; 542 - int err; 543 549 544 550 wait_for_completion_timeout(&comp_ctx->wait_event, 545 551 usecs_to_jiffies(aq->completion_timeout)); ··· 571 585 aq->cq.cc); 572 586 573 587 clear_bit(EFA_AQ_STATE_RUNNING_BIT, &aq->state); 574 - err = -ETIME; 575 - goto out; 588 + return -ETIME; 576 589 } 577 590 578 - err = efa_com_comp_status_to_errno(comp_ctx->user_cqe->acq_common_descriptor.status); 579 - out: 580 - efa_com_dealloc_comp_ctx(aq, comp_ctx); 581 - return err; 591 + return efa_com_comp_status_to_errno( 592 + comp_ctx->user_cqe->acq_common_descriptor.status); 582 593 } 583 594 584 595 /* ··· 625 642 ibdev_dbg(aq->efa_dev, "%s (opcode %d)\n", 626 643 efa_com_cmd_str(cmd->aq_common_descriptor.opcode), 627 644 cmd->aq_common_descriptor.opcode); 628 - comp_ctx = efa_com_submit_admin_cmd(aq, cmd, cmd_size, comp, comp_size); 629 - if (IS_ERR(comp_ctx)) { 645 + 646 + comp_ctx = efa_com_alloc_comp_ctx(aq); 647 + if (!comp_ctx) { 648 + clear_bit(EFA_AQ_STATE_RUNNING_BIT, &aq->state); 649 + up(&aq->avail_cmds); 650 + return -EINVAL; 651 + } 652 + 653 + err = efa_com_submit_admin_cmd(aq, comp_ctx, cmd, cmd_size, comp, comp_size); 654 + if (err) { 630 655 ibdev_err_ratelimited( 631 656 aq->efa_dev, 632 - "Failed to submit command %s (opcode %u) err %pe\n", 657 + "Failed to submit command %s (opcode %u) err %d\n", 633 658 efa_com_cmd_str(cmd->aq_common_descriptor.opcode), 634 - cmd->aq_common_descriptor.opcode, comp_ctx); 659 + cmd->aq_common_descriptor.opcode, err); 635 660 661 + efa_com_dealloc_comp_ctx(aq, comp_ctx); 636 662 up(&aq->avail_cmds); 637 663 atomic64_inc(&aq->stats.cmd_err); 638 - return PTR_ERR(comp_ctx); 664 + return err; 639 665 } 640 666 641 667 err = efa_com_wait_and_process_admin_cq(comp_ctx, aq); 642 668 if (err) { 643 669 ibdev_err_ratelimited( 644 670 aq->efa_dev, 645 - "Failed to process command %s (opcode %u) comp_status %d err %d\n", 671 + "Failed to process command %s (opcode %u) err %d\n", 646 672 efa_com_cmd_str(cmd->aq_common_descriptor.opcode), 647 - cmd->aq_common_descriptor.opcode, 648 - comp_ctx->user_cqe->acq_common_descriptor.status, err); 673 + cmd->aq_common_descriptor.opcode, err); 649 674 atomic64_inc(&aq->stats.cmd_err); 650 675 } 651 676 677 + efa_com_dealloc_comp_ctx(aq, comp_ctx); 652 678 up(&aq->avail_cmds); 653 679 654 680 return err;

+3 -1

drivers/infiniband/hw/ionic/ionic_controlpath.c

··· 508 508 { 509 509 const struct ib_global_route *grh; 510 510 enum rdma_network_type net; 511 + u8 smac[ETH_ALEN]; 511 512 u16 vlan; 512 513 int rc; 513 514 ··· 519 518 520 519 grh = rdma_ah_read_grh(attr); 521 520 522 - rc = rdma_read_gid_l2_fields(grh->sgid_attr, &vlan, &hdr->eth.smac_h[0]); 521 + rc = rdma_read_gid_l2_fields(grh->sgid_attr, &vlan, smac); 523 522 if (rc) 524 523 return rc; 525 524 ··· 537 536 if (rc) 538 537 return rc; 539 538 539 + ether_addr_copy(hdr->eth.smac_h, smac); 540 540 ether_addr_copy(hdr->eth.dmac_h, attr->roce.dmac); 541 541 542 542 if (net == RDMA_NETWORK_IPV4) {

+16 -13

drivers/infiniband/hw/irdma/cm.c

··· 2241 2241 int oldarpindex; 2242 2242 int arpindex; 2243 2243 struct net_device *netdev = iwdev->netdev; 2244 + int ret; 2244 2245 2245 2246 /* create an hte and cm_node for this instance */ 2246 2247 cm_node = kzalloc_obj(*cm_node, GFP_ATOMIC); 2247 2248 if (!cm_node) 2248 - return NULL; 2249 + return ERR_PTR(-ENOMEM); 2249 2250 2250 2251 /* set our node specific transport info */ 2251 2252 cm_node->ipv4 = cm_info->ipv4; ··· 2349 2348 arpindex = -EINVAL; 2350 2349 } 2351 2350 2352 - if (arpindex < 0) 2351 + if (arpindex < 0) { 2352 + ret = -EINVAL; 2353 2353 goto err; 2354 + } 2354 2355 2355 2356 ether_addr_copy(cm_node->rem_mac, 2356 2357 iwdev->rf->arp_table[arpindex].mac_addr); ··· 2363 2360 err: 2364 2361 kfree(cm_node); 2365 2362 2366 - return NULL; 2363 + return ERR_PTR(ret); 2367 2364 } 2368 2365 2369 2366 static void irdma_destroy_connection(struct irdma_cm_node *cm_node) ··· 3024 3021 3025 3022 /* create a CM connection node */ 3026 3023 cm_node = irdma_make_cm_node(cm_core, iwdev, cm_info, NULL); 3027 - if (!cm_node) 3028 - return -ENOMEM; 3024 + if (IS_ERR(cm_node)) 3025 + return PTR_ERR(cm_node); 3029 3026 3030 3027 /* set our node side to client (active) side */ 3031 3028 cm_node->tcp_cntxt.client = 1; ··· 3222 3219 cm_info.cm_id = listener->cm_id; 3223 3220 cm_node = irdma_make_cm_node(cm_core, iwdev, &cm_info, 3224 3221 listener); 3225 - if (!cm_node) { 3222 + if (IS_ERR(cm_node)) { 3226 3223 ibdev_dbg(&cm_core->iwdev->ibdev, 3227 - "CM: allocate node failed\n"); 3224 + "CM: allocate node failed ret=%ld\n", PTR_ERR(cm_node)); 3228 3225 refcount_dec(&listener->refcnt); 3229 3226 return; 3230 3227 } ··· 4242 4239 irdma_cm_event_reset(event); 4243 4240 break; 4244 4241 case IRDMA_CM_EVENT_CONNECTED: 4245 - if (!event->cm_node->cm_id || 4246 - event->cm_node->state != IRDMA_CM_STATE_OFFLOADED) 4242 + if (!cm_node->cm_id || 4243 + cm_node->state != IRDMA_CM_STATE_OFFLOADED) 4247 4244 break; 4248 4245 irdma_cm_event_connected(event); 4249 4246 break; 4250 4247 case IRDMA_CM_EVENT_MPA_REJECT: 4251 - if (!event->cm_node->cm_id || 4248 + if (!cm_node->cm_id || 4252 4249 cm_node->state == IRDMA_CM_STATE_OFFLOADED) 4253 4250 break; 4254 4251 irdma_send_cm_event(cm_node, cm_node->cm_id, 4255 4252 IW_CM_EVENT_CONNECT_REPLY, -ECONNREFUSED); 4256 4253 break; 4257 4254 case IRDMA_CM_EVENT_ABORTED: 4258 - if (!event->cm_node->cm_id || 4259 - event->cm_node->state == IRDMA_CM_STATE_OFFLOADED) 4255 + if (!cm_node->cm_id || 4256 + cm_node->state == IRDMA_CM_STATE_OFFLOADED) 4260 4257 break; 4261 4258 irdma_event_connect_error(event); 4262 4259 break; ··· 4266 4263 break; 4267 4264 } 4268 4265 4269 - irdma_rem_ref_cm_node(event->cm_node); 4266 + irdma_rem_ref_cm_node(cm_node); 4270 4267 kfree(event); 4271 4268 } 4272 4269

+22 -17

drivers/infiniband/hw/irdma/uk.c

··· 1438 1438 * irdma_round_up_wq - return round up qp wq depth 1439 1439 * @wqdepth: wq depth in quanta to round up 1440 1440 */ 1441 - static int irdma_round_up_wq(u32 wqdepth) 1441 + static u64 irdma_round_up_wq(u64 wqdepth) 1442 1442 { 1443 1443 int scount = 1; 1444 1444 ··· 1491 1491 int irdma_get_sqdepth(struct irdma_uk_attrs *uk_attrs, u32 sq_size, u8 shift, 1492 1492 u32 *sqdepth) 1493 1493 { 1494 - u32 min_size = (u32)uk_attrs->min_hw_wq_size << shift; 1494 + u32 min_hw_quanta = (u32)uk_attrs->min_hw_wq_size << shift; 1495 + u64 hw_quanta = 1496 + irdma_round_up_wq(((u64)sq_size << shift) + IRDMA_SQ_RSVD); 1495 1497 1496 - *sqdepth = irdma_round_up_wq((sq_size << shift) + IRDMA_SQ_RSVD); 1497 - 1498 - if (*sqdepth < min_size) 1499 - *sqdepth = min_size; 1500 - else if (*sqdepth > uk_attrs->max_hw_wq_quanta) 1498 + if (hw_quanta < min_hw_quanta) 1499 + hw_quanta = min_hw_quanta; 1500 + else if (hw_quanta > uk_attrs->max_hw_wq_quanta) 1501 1501 return -EINVAL; 1502 1502 1503 + *sqdepth = hw_quanta; 1503 1504 return 0; 1504 1505 } 1505 1506 ··· 1514 1513 int irdma_get_rqdepth(struct irdma_uk_attrs *uk_attrs, u32 rq_size, u8 shift, 1515 1514 u32 *rqdepth) 1516 1515 { 1517 - u32 min_size = (u32)uk_attrs->min_hw_wq_size << shift; 1516 + u32 min_hw_quanta = (u32)uk_attrs->min_hw_wq_size << shift; 1517 + u64 hw_quanta = 1518 + irdma_round_up_wq(((u64)rq_size << shift) + IRDMA_RQ_RSVD); 1518 1519 1519 - *rqdepth = irdma_round_up_wq((rq_size << shift) + IRDMA_RQ_RSVD); 1520 - 1521 - if (*rqdepth < min_size) 1522 - *rqdepth = min_size; 1523 - else if (*rqdepth > uk_attrs->max_hw_rq_quanta) 1520 + if (hw_quanta < min_hw_quanta) 1521 + hw_quanta = min_hw_quanta; 1522 + else if (hw_quanta > uk_attrs->max_hw_rq_quanta) 1524 1523 return -EINVAL; 1525 1524 1525 + *rqdepth = hw_quanta; 1526 1526 return 0; 1527 1527 } 1528 1528 ··· 1537 1535 int irdma_get_srqdepth(struct irdma_uk_attrs *uk_attrs, u32 srq_size, u8 shift, 1538 1536 u32 *srqdepth) 1539 1537 { 1540 - *srqdepth = irdma_round_up_wq((srq_size << shift) + IRDMA_RQ_RSVD); 1538 + u32 min_hw_quanta = (u32)uk_attrs->min_hw_wq_size << shift; 1539 + u64 hw_quanta = 1540 + irdma_round_up_wq(((u64)srq_size << shift) + IRDMA_RQ_RSVD); 1541 1541 1542 - if (*srqdepth < ((u32)uk_attrs->min_hw_wq_size << shift)) 1543 - *srqdepth = uk_attrs->min_hw_wq_size << shift; 1544 - else if (*srqdepth > uk_attrs->max_hw_srq_quanta) 1542 + if (hw_quanta < min_hw_quanta) 1543 + hw_quanta = min_hw_quanta; 1544 + else if (hw_quanta > uk_attrs->max_hw_srq_quanta) 1545 1545 return -EINVAL; 1546 1546 1547 + *srqdepth = hw_quanta; 1547 1548 return 0; 1548 1549 } 1549 1550

-2

drivers/infiniband/hw/irdma/utils.c

··· 2322 2322 struct irdma_qp *qp = sc_qp->qp_uk.back_qp; 2323 2323 struct ib_qp_attr attr; 2324 2324 2325 - if (qp->iwdev->rf->reset) 2326 - return; 2327 2325 attr.qp_state = IB_QPS_ERR; 2328 2326 2329 2327 if (rdma_protocol_roce(qp->ibqp.device, 1))

+6 -4

drivers/infiniband/hw/irdma/verbs.c

··· 558 558 } 559 559 560 560 irdma_qp_rem_ref(&iwqp->ibqp); 561 - wait_for_completion(&iwqp->free_qp); 561 + if (!iwdev->rf->reset) 562 + wait_for_completion(&iwqp->free_qp); 562 563 irdma_free_lsmm_rsrc(iwqp); 563 564 irdma_cqp_qp_destroy_cmd(&iwdev->rf->sc_dev, &iwqp->sc_qp); 564 565 ··· 1106 1105 spin_lock_init(&iwqp->sc_qp.pfpdu.lock); 1107 1106 iwqp->sig_all = init_attr->sq_sig_type == IB_SIGNAL_ALL_WR; 1108 1107 rf->qp_table[qp_num] = iwqp; 1108 + init_completion(&iwqp->free_qp); 1109 1109 1110 1110 if (udata) { 1111 1111 /* GEN_1 legacy support with libi40iw does not have expanded uresp struct */ ··· 1131 1129 } 1132 1130 } 1133 1131 1134 - init_completion(&iwqp->free_qp); 1135 1132 return 0; 1136 1133 1137 1134 error: ··· 1463 1462 ctx_info->remote_atomics_en = true; 1464 1463 } 1465 1464 1466 - wait_event(iwqp->mod_qp_waitq, !atomic_read(&iwqp->hw_mod_qp_pend)); 1467 - 1468 1465 ibdev_dbg(&iwdev->ibdev, 1469 1466 "VERBS: caller: %pS qp_id=%d to_ibqpstate=%d ibqpstate=%d irdma_qpstate=%d attr_mask=0x%x\n", 1470 1467 __builtin_return_address(0), ibqp->qp_num, attr->qp_state, ··· 1539 1540 case IB_QPS_ERR: 1540 1541 case IB_QPS_RESET: 1541 1542 if (iwqp->iwarp_state == IRDMA_QP_STATE_ERROR) { 1543 + iwqp->ibqp_state = attr->qp_state; 1542 1544 spin_unlock_irqrestore(&iwqp->lock, flags); 1543 1545 if (udata && udata->inlen) { 1544 1546 if (ib_copy_from_udata(&ureq, udata, ··· 1745 1745 case IB_QPS_ERR: 1746 1746 case IB_QPS_RESET: 1747 1747 if (iwqp->iwarp_state == IRDMA_QP_STATE_ERROR) { 1748 + iwqp->ibqp_state = attr->qp_state; 1748 1749 spin_unlock_irqrestore(&iwqp->lock, flags); 1749 1750 if (udata && udata->inlen) { 1750 1751 if (ib_copy_from_udata(&ureq, udata, ··· 3724 3723 3725 3724 err: 3726 3725 ib_umem_release(region); 3726 + iwmr->region = NULL; 3727 3727 return err; 3728 3728 } 3729 3729

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