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Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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arm64: dts: nuvoton: Add pinctrl

This is critical to support multifunction pins shared between devices as
well as generic GPIOs.

Signed-off-by: William A. Kennington III <william@wkennington.com>
Link: https://patch.msgid.link/20250416015902.2091251-1-william@wkennington.com
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
Link: https://lore.kernel.org/r/20250515-nuvoton-arm64-dt-v1-1-25769b8c1509@codeconstruct.com.au
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

authored by

William A. Kennington III and committed by
Arnd Bergmann 7e1a0dfb 816a748b

+65
+65
arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi
··· 176 176 }; 177 177 }; 178 178 }; 179 + 180 + pinctrl: pinctrl@f0010000 { 181 + compatible = "nuvoton,npcm845-pinctrl"; 182 + ranges = <0x0 0x0 0xf0010000 0x8000>; 183 + #address-cells = <1>; 184 + #size-cells = <1>; 185 + nuvoton,sysgcr = <&gcr>; 186 + status = "okay"; 187 + gpio0: gpio@f0010000 { 188 + gpio-controller; 189 + #gpio-cells = <2>; 190 + reg = <0x0 0xB0>; 191 + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 192 + gpio-ranges = <&pinctrl 0 0 32>; 193 + }; 194 + gpio1: gpio@f0011000 { 195 + gpio-controller; 196 + #gpio-cells = <2>; 197 + reg = <0x1000 0xB0>; 198 + interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 199 + gpio-ranges = <&pinctrl 0 32 32>; 200 + }; 201 + gpio2: gpio@f0012000 { 202 + gpio-controller; 203 + #gpio-cells = <2>; 204 + reg = <0x2000 0xB0>; 205 + interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 206 + gpio-ranges = <&pinctrl 0 64 32>; 207 + }; 208 + gpio3: gpio@f0013000 { 209 + gpio-controller; 210 + #gpio-cells = <2>; 211 + reg = <0x3000 0xB0>; 212 + interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 213 + gpio-ranges = <&pinctrl 0 96 32>; 214 + }; 215 + gpio4: gpio@f0014000 { 216 + gpio-controller; 217 + #gpio-cells = <2>; 218 + reg = <0x4000 0xB0>; 219 + interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 220 + gpio-ranges = <&pinctrl 0 128 32>; 221 + }; 222 + gpio5: gpio@f0015000 { 223 + gpio-controller; 224 + #gpio-cells = <2>; 225 + reg = <0x5000 0xB0>; 226 + interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 227 + gpio-ranges = <&pinctrl 0 160 32>; 228 + }; 229 + gpio6: gpio@f0016000 { 230 + gpio-controller; 231 + #gpio-cells = <2>; 232 + reg = <0x6000 0xB0>; 233 + interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 234 + gpio-ranges = <&pinctrl 0 192 32>; 235 + }; 236 + gpio7: gpio@f0017000 { 237 + gpio-controller; 238 + #gpio-cells = <2>; 239 + reg = <0x7000 0xB0>; 240 + interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 241 + gpio-ranges = <&pinctrl 0 224 32>; 242 + }; 243 + }; 179 244 };