Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'qcom-arm32-for-6.13' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt
Qualcomm Arm32 DeviceTree updates for v6.13
IPQ4019 flash partition scheme is moved to nvmem-layout. SDX55 and SDX65
PCIe EP controllers gain missing linux,pci-domain properties.
Stylistic improvements across a range of platforms and devices.
* tag 'qcom-arm32-for-6.13' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux:
ARM: dts: qcom: ipq4019: use nvmem-layout
ARM: dts: qcom: change labels to lower-case
ARM: dts: qcom: sdx65: Add 'linux,pci-domain' to PCIe EP controller node
ARM: dts: qcom: sdx55: Add 'linux,pci-domain' to PCIe EP controller node
ARM: dts: qcom: minor whitespace cleanup
ARM: dts: qcom: drop underscore in node names
Link: https://lore.kernel.org/r/20241104034744.14378-1-andersson@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
+186
-181
+19
-19
arch/arm/boot/dts/qcom/qcom-apq8064.dtsi
+19
-19
arch/arm/boot/dts/qcom/qcom-apq8064.dtsi
···
36
36
#address-cells = <1>;
37
37
#size-cells = <0>;
38
38
39
-
CPU0: cpu@0 {
39
+
cpu0: cpu@0 {
40
40
compatible = "qcom,krait";
41
41
enable-method = "qcom,kpss-acc-v1";
42
42
device_type = "cpu";
43
43
reg = <0>;
44
-
next-level-cache = <&L2>;
44
+
next-level-cache = <&l2>;
45
45
qcom,acc = <&acc0>;
46
46
qcom,saw = <&saw0>;
47
-
cpu-idle-states = <&CPU_SPC>;
47
+
cpu-idle-states = <&cpu_spc>;
48
48
};
49
49
50
-
CPU1: cpu@1 {
50
+
cpu1: cpu@1 {
51
51
compatible = "qcom,krait";
52
52
enable-method = "qcom,kpss-acc-v1";
53
53
device_type = "cpu";
54
54
reg = <1>;
55
-
next-level-cache = <&L2>;
55
+
next-level-cache = <&l2>;
56
56
qcom,acc = <&acc1>;
57
57
qcom,saw = <&saw1>;
58
-
cpu-idle-states = <&CPU_SPC>;
58
+
cpu-idle-states = <&cpu_spc>;
59
59
};
60
60
61
-
CPU2: cpu@2 {
61
+
cpu2: cpu@2 {
62
62
compatible = "qcom,krait";
63
63
enable-method = "qcom,kpss-acc-v1";
64
64
device_type = "cpu";
65
65
reg = <2>;
66
-
next-level-cache = <&L2>;
66
+
next-level-cache = <&l2>;
67
67
qcom,acc = <&acc2>;
68
68
qcom,saw = <&saw2>;
69
-
cpu-idle-states = <&CPU_SPC>;
69
+
cpu-idle-states = <&cpu_spc>;
70
70
};
71
71
72
-
CPU3: cpu@3 {
72
+
cpu3: cpu@3 {
73
73
compatible = "qcom,krait";
74
74
enable-method = "qcom,kpss-acc-v1";
75
75
device_type = "cpu";
76
76
reg = <3>;
77
-
next-level-cache = <&L2>;
77
+
next-level-cache = <&l2>;
78
78
qcom,acc = <&acc3>;
79
79
qcom,saw = <&saw3>;
80
-
cpu-idle-states = <&CPU_SPC>;
80
+
cpu-idle-states = <&cpu_spc>;
81
81
};
82
82
83
-
L2: l2-cache {
83
+
l2: l2-cache {
84
84
compatible = "cache";
85
85
cache-level = <2>;
86
86
cache-unified;
87
87
};
88
88
89
89
idle-states {
90
-
CPU_SPC: cpu-spc {
90
+
cpu_spc: cpu-spc {
91
91
compatible = "qcom,idle-state-spc",
92
92
"arm,idle-state";
93
93
entry-latency-us = <400>;
···
675
675
tsens_calib: calib@404 {
676
676
reg = <0x404 0x10>;
677
677
};
678
-
tsens_backup: backup_calib@414 {
678
+
tsens_backup: backup-calib@414 {
679
679
reg = <0x414 0x10>;
680
680
};
681
681
};
···
1625
1625
clocks = <&rpmcc RPM_QDSS_CLK>;
1626
1626
clock-names = "apb_pclk";
1627
1627
1628
-
cpu = <&CPU0>;
1628
+
cpu = <&cpu0>;
1629
1629
1630
1630
out-ports {
1631
1631
port {
···
1643
1643
clocks = <&rpmcc RPM_QDSS_CLK>;
1644
1644
clock-names = "apb_pclk";
1645
1645
1646
-
cpu = <&CPU1>;
1646
+
cpu = <&cpu1>;
1647
1647
1648
1648
out-ports {
1649
1649
port {
···
1661
1661
clocks = <&rpmcc RPM_QDSS_CLK>;
1662
1662
clock-names = "apb_pclk";
1663
1663
1664
-
cpu = <&CPU2>;
1664
+
cpu = <&cpu2>;
1665
1665
1666
1666
out-ports {
1667
1667
port {
···
1679
1679
clocks = <&rpmcc RPM_QDSS_CLK>;
1680
1680
clock-names = "apb_pclk";
1681
1681
1682
-
cpu = <&CPU3>;
1682
+
cpu = <&cpu3>;
1683
1683
1684
1684
out-ports {
1685
1685
port {
+39
-39
arch/arm/boot/dts/qcom/qcom-apq8084.dtsi
+39
-39
arch/arm/boot/dts/qcom/qcom-apq8084.dtsi
···
17
17
#size-cells = <1>;
18
18
ranges;
19
19
20
-
smem_mem: smem_region@fa00000 {
20
+
smem_mem: smem-region@fa00000 {
21
21
reg = <0xfa00000 0x200000>;
22
22
no-map;
23
23
};
···
32
32
compatible = "qcom,krait";
33
33
reg = <0>;
34
34
enable-method = "qcom,kpss-acc-v2";
35
-
next-level-cache = <&L2>;
35
+
next-level-cache = <&l2>;
36
36
qcom,acc = <&acc0>;
37
37
qcom,saw = <&saw0>;
38
-
cpu-idle-states = <&CPU_SPC>;
38
+
cpu-idle-states = <&cpu_spc>;
39
39
};
40
40
41
41
cpu@1 {
···
43
43
compatible = "qcom,krait";
44
44
reg = <1>;
45
45
enable-method = "qcom,kpss-acc-v2";
46
-
next-level-cache = <&L2>;
46
+
next-level-cache = <&l2>;
47
47
qcom,acc = <&acc1>;
48
48
qcom,saw = <&saw1>;
49
-
cpu-idle-states = <&CPU_SPC>;
49
+
cpu-idle-states = <&cpu_spc>;
50
50
};
51
51
52
52
cpu@2 {
···
54
54
compatible = "qcom,krait";
55
55
reg = <2>;
56
56
enable-method = "qcom,kpss-acc-v2";
57
-
next-level-cache = <&L2>;
57
+
next-level-cache = <&l2>;
58
58
qcom,acc = <&acc2>;
59
59
qcom,saw = <&saw2>;
60
-
cpu-idle-states = <&CPU_SPC>;
60
+
cpu-idle-states = <&cpu_spc>;
61
61
};
62
62
63
63
cpu@3 {
···
65
65
compatible = "qcom,krait";
66
66
reg = <3>;
67
67
enable-method = "qcom,kpss-acc-v2";
68
-
next-level-cache = <&L2>;
68
+
next-level-cache = <&l2>;
69
69
qcom,acc = <&acc3>;
70
70
qcom,saw = <&saw3>;
71
-
cpu-idle-states = <&CPU_SPC>;
71
+
cpu-idle-states = <&cpu_spc>;
72
72
};
73
73
74
-
L2: l2-cache {
74
+
l2: l2-cache {
75
75
compatible = "cache";
76
76
cache-level = <2>;
77
77
cache-unified;
···
79
79
};
80
80
81
81
idle-states {
82
-
CPU_SPC: cpu-spc {
82
+
cpu_spc: cpu-spc {
83
83
compatible = "qcom,idle-state-spc",
84
84
"arm,idle-state";
85
85
entry-latency-us = <150>;
···
311
311
bits = <0 6>;
312
312
};
313
313
314
-
tsens_s10_p1: s10_p1@d8 {
314
+
tsens_s10_p1: s10-p1@d8 {
315
315
reg = <0xd8 0x2>;
316
316
bits = <6 6>;
317
317
};
···
371
371
bits = <4 6>;
372
372
};
373
373
374
-
tsens_s10_p2: s10_p2@e2 {
374
+
tsens_s10_p2: s10-p2@e2 {
375
375
reg = <0xe2 0x2>;
376
376
bits = <2 6>;
377
377
};
378
378
379
-
tsens_s5_p2_backup: s5-p2_backup@e3 {
379
+
tsens_s5_p2_backup: s5-p2-backup@e3 {
380
380
reg = <0xe3 0x2>;
381
381
bits = <0 6>;
382
382
};
383
383
384
-
tsens_mode_backup: mode_backup@e3 {
384
+
tsens_mode_backup: mode-backup@e3 {
385
385
reg = <0xe3 0x1>;
386
386
bits = <6 2>;
387
387
};
388
388
389
-
tsens_s6_p2_backup: s6-p2_backup@e4 {
389
+
tsens_s6_p2_backup: s6-p2-backup@e4 {
390
390
reg = <0xe4 0x1>;
391
391
bits = <0 6>;
392
392
};
393
393
394
-
tsens_s7_p2_backup: s7-p2_backup@e4 {
394
+
tsens_s7_p2_backup: s7-p2-backup@e4 {
395
395
reg = <0xe4 0x2>;
396
396
bits = <6 6>;
397
397
};
398
398
399
-
tsens_s8_p2_backup: s8-p2_backup@e5 {
399
+
tsens_s8_p2_backup: s8-p2-backup@e5 {
400
400
reg = <0xe5 0x2>;
401
401
bits = <4 6>;
402
402
};
403
403
404
-
tsens_s9_p2_backup: s9-p2_backup@e6 {
404
+
tsens_s9_p2_backup: s9-p2-backup@e6 {
405
405
reg = <0xe6 0x2>;
406
406
bits = <2 6>;
407
407
};
408
408
409
-
tsens_s10_p2_backup: s10_p2_backup@e7 {
409
+
tsens_s10_p2_backup: s10-p2-backup@e7 {
410
410
reg = <0xe7 0x1>;
411
411
bits = <0 6>;
412
412
};
413
413
414
-
tsens_base1_backup: base1_backup@440 {
414
+
tsens_base1_backup: base1-backup@440 {
415
415
reg = <0x440 0x1>;
416
416
bits = <0 8>;
417
417
};
418
418
419
-
tsens_s0_p1_backup: s0-p1_backup@441 {
419
+
tsens_s0_p1_backup: s0-p1-backup@441 {
420
420
reg = <0x441 0x1>;
421
421
bits = <0 6>;
422
422
};
423
423
424
-
tsens_s1_p1_backup: s1-p1_backup@442 {
424
+
tsens_s1_p1_backup: s1-p1-backup@442 {
425
425
reg = <0x441 0x2>;
426
426
bits = <6 6>;
427
427
};
428
428
429
-
tsens_s2_p1_backup: s2-p1_backup@442 {
429
+
tsens_s2_p1_backup: s2-p1-backup@442 {
430
430
reg = <0x442 0x2>;
431
431
bits = <4 6>;
432
432
};
433
433
434
-
tsens_s3_p1_backup: s3-p1_backup@443 {
434
+
tsens_s3_p1_backup: s3-p1-backup@443 {
435
435
reg = <0x443 0x1>;
436
436
bits = <2 6>;
437
437
};
438
438
439
-
tsens_s4_p1_backup: s4-p1_backup@444 {
439
+
tsens_s4_p1_backup: s4-p1-backup@444 {
440
440
reg = <0x444 0x1>;
441
441
bits = <0 6>;
442
442
};
443
443
444
-
tsens_s5_p1_backup: s5-p1_backup@444 {
444
+
tsens_s5_p1_backup: s5-p1-backup@444 {
445
445
reg = <0x444 0x2>;
446
446
bits = <6 6>;
447
447
};
448
448
449
-
tsens_s6_p1_backup: s6-p1_backup@445 {
449
+
tsens_s6_p1_backup: s6-p1-backup@445 {
450
450
reg = <0x445 0x2>;
451
451
bits = <4 6>;
452
452
};
453
453
454
-
tsens_s7_p1_backup: s7-p1_backup@446 {
454
+
tsens_s7_p1_backup: s7-p1-backup@446 {
455
455
reg = <0x446 0x1>;
456
456
bits = <2 6>;
457
457
};
458
458
459
-
tsens_use_backup: use_backup@447 {
459
+
tsens_use_backup: use-backup@447 {
460
460
reg = <0x447 0x1>;
461
461
bits = <5 3>;
462
462
};
463
463
464
-
tsens_s8_p1_backup: s8-p1_backup@448 {
464
+
tsens_s8_p1_backup: s8-p1-backup@448 {
465
465
reg = <0x448 0x1>;
466
466
bits = <0 6>;
467
467
};
468
468
469
-
tsens_s9_p1_backup: s9-p1_backup@448 {
469
+
tsens_s9_p1_backup: s9-p1-backup@448 {
470
470
reg = <0x448 0x2>;
471
471
bits = <6 6>;
472
472
};
473
473
474
-
tsens_s10_p1_backup: s10_p1_backup@449 {
474
+
tsens_s10_p1_backup: s10-p1-backup@449 {
475
475
reg = <0x449 0x2>;
476
476
bits = <4 6>;
477
477
};
478
478
479
-
tsens_base2_backup: base2_backup@44a {
479
+
tsens_base2_backup: base2-backup@44a {
480
480
reg = <0x44a 0x2>;
481
481
bits = <2 8>;
482
482
};
483
483
484
-
tsens_s0_p2_backup: s0-p2_backup@44b {
484
+
tsens_s0_p2_backup: s0-p2-backup@44b {
485
485
reg = <0x44b 0x3>;
486
486
bits = <2 6>;
487
487
};
488
488
489
-
tsens_s1_p2_backup: s1-p2_backup@44c {
489
+
tsens_s1_p2_backup: s1-p2-backup@44c {
490
490
reg = <0x44c 0x1>;
491
491
bits = <0 6>;
492
492
};
493
493
494
-
tsens_s2_p2_backup: s2-p2_backup@44c {
494
+
tsens_s2_p2_backup: s2-p2-backup@44c {
495
495
reg = <0x44c 0x2>;
496
496
bits = <6 6>;
497
497
};
498
498
499
-
tsens_s3_p2_backup: s3-p2_backup@44d {
499
+
tsens_s3_p2_backup: s3-p2-backup@44d {
500
500
reg = <0x44d 0x2>;
501
501
bits = <4 6>;
502
502
};
503
503
504
-
tsens_s4_p2_backup: s4-p2_backup@44e {
504
+
tsens_s4_p2_backup: s4-p2-backup@44e {
505
505
reg = <0x44e 0x1>;
506
506
bits = <2 6>;
507
507
};
+11
-8
arch/arm/boot/dts/qcom/qcom-ipq4018-ap120c-ac.dtsi
+11
-8
arch/arm/boot/dts/qcom/qcom-ipq4018-ap120c-ac.dtsi
···
166
166
label = "ART";
167
167
reg = <0x00170000 0x00010000>;
168
168
read-only;
169
-
compatible = "nvmem-cells";
170
-
#address-cells = <1>;
171
-
#size-cells = <1>;
172
169
173
-
precal_art_1000: precal@1000 {
174
-
reg = <0x1000 0x2f20>;
175
-
};
170
+
nvmem-layout {
171
+
compatible = "fixed-layout";
172
+
#address-cells = <1>;
173
+
#size-cells = <1>;
176
174
177
-
precal_art_5000: precal@5000 {
178
-
reg = <0x5000 0x2f20>;
175
+
precal_art_1000: precal@1000 {
176
+
reg = <0x1000 0x2f20>;
177
+
};
178
+
179
+
precal_art_5000: precal@5000 {
180
+
reg = <0x5000 0x2f20>;
181
+
};
179
182
};
180
183
};
181
184
+1
-1
arch/arm/boot/dts/qcom/qcom-ipq4018-jalapeno.dts
+1
-1
arch/arm/boot/dts/qcom/qcom-ipq4018-jalapeno.dts
+5
-5
arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi
+5
-5
arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi
···
47
47
device_type = "cpu";
48
48
compatible = "arm,cortex-a7";
49
49
enable-method = "qcom,kpss-acc-v2";
50
-
next-level-cache = <&L2>;
50
+
next-level-cache = <&l2>;
51
51
qcom,acc = <&acc0>;
52
52
qcom,saw = <&saw0>;
53
53
reg = <0x0>;
···
61
61
device_type = "cpu";
62
62
compatible = "arm,cortex-a7";
63
63
enable-method = "qcom,kpss-acc-v2";
64
-
next-level-cache = <&L2>;
64
+
next-level-cache = <&l2>;
65
65
qcom,acc = <&acc1>;
66
66
qcom,saw = <&saw1>;
67
67
reg = <0x1>;
···
75
75
device_type = "cpu";
76
76
compatible = "arm,cortex-a7";
77
77
enable-method = "qcom,kpss-acc-v2";
78
-
next-level-cache = <&L2>;
78
+
next-level-cache = <&l2>;
79
79
qcom,acc = <&acc2>;
80
80
qcom,saw = <&saw2>;
81
81
reg = <0x2>;
···
89
89
device_type = "cpu";
90
90
compatible = "arm,cortex-a7";
91
91
enable-method = "qcom,kpss-acc-v2";
92
-
next-level-cache = <&L2>;
92
+
next-level-cache = <&l2>;
93
93
qcom,acc = <&acc3>;
94
94
qcom,saw = <&saw3>;
95
95
reg = <0x3>;
···
99
99
operating-points-v2 = <&cpu0_opp_table>;
100
100
};
101
101
102
-
L2: l2-cache {
102
+
l2: l2-cache {
103
103
compatible = "cache";
104
104
cache-level = <2>;
105
105
cache-unified;
+4
-4
arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi
+4
-4
arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi
···
27
27
enable-method = "qcom,kpss-acc-v1";
28
28
device_type = "cpu";
29
29
reg = <0>;
30
-
next-level-cache = <&L2>;
30
+
next-level-cache = <&l2>;
31
31
qcom,acc = <&acc0>;
32
32
qcom,saw = <&saw0>;
33
33
};
···
37
37
enable-method = "qcom,kpss-acc-v1";
38
38
device_type = "cpu";
39
39
reg = <1>;
40
-
next-level-cache = <&L2>;
40
+
next-level-cache = <&l2>;
41
41
qcom,acc = <&acc1>;
42
42
qcom,saw = <&saw1>;
43
43
};
44
44
45
-
L2: l2-cache {
45
+
l2: l2-cache {
46
46
compatible = "cache";
47
47
cache-level = <2>;
48
48
cache-unified;
···
383
383
tsens_calib: calib@400 {
384
384
reg = <0x400 0xb>;
385
385
};
386
-
tsens_calib_backup: calib_backup@410 {
386
+
tsens_calib_backup: calib-backup@410 {
387
387
reg = <0x410 0xb>;
388
388
};
389
389
};
+2
-2
arch/arm/boot/dts/qcom/qcom-mdm9615.dtsi
+2
-2
arch/arm/boot/dts/qcom/qcom-mdm9615.dtsi
···
30
30
compatible = "arm,cortex-a5";
31
31
reg = <0>;
32
32
device_type = "cpu";
33
-
next-level-cache = <&L2>;
33
+
next-level-cache = <&l2>;
34
34
};
35
35
};
36
36
···
61
61
ranges;
62
62
compatible = "simple-bus";
63
63
64
-
L2: cache-controller@2040000 {
64
+
l2: cache-controller@2040000 {
65
65
compatible = "arm,pl310-cache";
66
66
reg = <0x02040000 0x1000>;
67
67
arm,data-latency = <2 2 0>;
+17
-17
arch/arm/boot/dts/qcom/qcom-msm8226.dtsi
+17
-17
arch/arm/boot/dts/qcom/qcom-msm8226.dtsi
···
39
39
#address-cells = <1>;
40
40
#size-cells = <0>;
41
41
42
-
CPU0: cpu@0 {
42
+
cpu0: cpu@0 {
43
43
compatible = "arm,cortex-a7";
44
44
enable-method = "qcom,msm8226-smp";
45
45
device_type = "cpu";
46
46
reg = <0>;
47
-
next-level-cache = <&L2>;
47
+
next-level-cache = <&l2>;
48
48
clocks = <&apcs>;
49
49
operating-points-v2 = <&cpu_opp_table>;
50
50
qcom,acc = <&acc0>;
···
52
52
#cooling-cells = <2>;
53
53
};
54
54
55
-
CPU1: cpu@1 {
55
+
cpu1: cpu@1 {
56
56
compatible = "arm,cortex-a7";
57
57
enable-method = "qcom,msm8226-smp";
58
58
device_type = "cpu";
59
59
reg = <1>;
60
-
next-level-cache = <&L2>;
60
+
next-level-cache = <&l2>;
61
61
clocks = <&apcs>;
62
62
operating-points-v2 = <&cpu_opp_table>;
63
63
qcom,acc = <&acc1>;
···
65
65
#cooling-cells = <2>;
66
66
};
67
67
68
-
CPU2: cpu@2 {
68
+
cpu2: cpu@2 {
69
69
compatible = "arm,cortex-a7";
70
70
enable-method = "qcom,msm8226-smp";
71
71
device_type = "cpu";
72
72
reg = <2>;
73
-
next-level-cache = <&L2>;
73
+
next-level-cache = <&l2>;
74
74
clocks = <&apcs>;
75
75
operating-points-v2 = <&cpu_opp_table>;
76
76
qcom,acc = <&acc2>;
···
78
78
#cooling-cells = <2>;
79
79
};
80
80
81
-
CPU3: cpu@3 {
81
+
cpu3: cpu@3 {
82
82
compatible = "arm,cortex-a7";
83
83
enable-method = "qcom,msm8226-smp";
84
84
device_type = "cpu";
85
85
reg = <3>;
86
-
next-level-cache = <&L2>;
86
+
next-level-cache = <&l2>;
87
87
clocks = <&apcs>;
88
88
operating-points-v2 = <&cpu_opp_table>;
89
89
qcom,acc = <&acc3>;
···
91
91
#cooling-cells = <2>;
92
92
};
93
93
94
-
L2: l2-cache {
94
+
l2: l2-cache {
95
95
compatible = "cache";
96
96
cache-level = <2>;
97
97
cache-unified;
···
1264
1264
cooling-maps {
1265
1265
map0 {
1266
1266
trip = <&cpu_alert0>;
1267
-
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1268
-
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1269
-
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1270
-
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1267
+
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1268
+
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1269
+
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1270
+
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1271
1271
};
1272
1272
};
1273
1273
···
1295
1295
cooling-maps {
1296
1296
map0 {
1297
1297
trip = <&cpu_alert1>;
1298
-
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1299
-
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1300
-
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1301
-
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1298
+
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1299
+
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1300
+
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1301
+
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1302
1302
};
1303
1303
};
1304
1304
+3
-3
arch/arm/boot/dts/qcom/qcom-msm8660.dtsi
+3
-3
arch/arm/boot/dts/qcom/qcom-msm8660.dtsi
···
22
22
enable-method = "qcom,gcc-msm8660";
23
23
device_type = "cpu";
24
24
reg = <0>;
25
-
next-level-cache = <&L2>;
25
+
next-level-cache = <&l2>;
26
26
};
27
27
28
28
cpu@1 {
···
30
30
enable-method = "qcom,gcc-msm8660";
31
31
device_type = "cpu";
32
32
reg = <1>;
33
-
next-level-cache = <&L2>;
33
+
next-level-cache = <&l2>;
34
34
};
35
35
36
-
L2: l2-cache {
36
+
l2: l2-cache {
37
37
compatible = "cache";
38
38
cache-level = <2>;
39
39
cache-unified;
+3
-3
arch/arm/boot/dts/qcom/qcom-msm8960.dtsi
+3
-3
arch/arm/boot/dts/qcom/qcom-msm8960.dtsi
···
25
25
enable-method = "qcom,kpss-acc-v1";
26
26
device_type = "cpu";
27
27
reg = <0>;
28
-
next-level-cache = <&L2>;
28
+
next-level-cache = <&l2>;
29
29
qcom,acc = <&acc0>;
30
30
qcom,saw = <&saw0>;
31
31
};
···
35
35
enable-method = "qcom,kpss-acc-v1";
36
36
device_type = "cpu";
37
37
reg = <1>;
38
-
next-level-cache = <&L2>;
38
+
next-level-cache = <&l2>;
39
39
qcom,acc = <&acc1>;
40
40
qcom,saw = <&saw1>;
41
41
};
42
42
43
-
L2: l2-cache {
43
+
l2: l2-cache {
44
44
compatible = "cache";
45
45
cache-level = <2>;
46
46
cache-unified;
+1
-1
arch/arm/boot/dts/qcom/qcom-msm8974-lge-nexus5-hammerhead.dts
+1
-1
arch/arm/boot/dts/qcom/qcom-msm8974-lge-nexus5-hammerhead.dts
+46
-46
arch/arm/boot/dts/qcom/qcom-msm8974.dtsi
+46
-46
arch/arm/boot/dts/qcom/qcom-msm8974.dtsi
···
35
35
#size-cells = <0>;
36
36
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
37
37
38
-
CPU0: cpu@0 {
38
+
cpu0: cpu@0 {
39
39
compatible = "qcom,krait";
40
40
enable-method = "qcom,kpss-acc-v2";
41
41
device_type = "cpu";
42
42
reg = <0>;
43
-
next-level-cache = <&L2>;
43
+
next-level-cache = <&l2>;
44
44
qcom,acc = <&acc0>;
45
45
qcom,saw = <&saw0>;
46
-
cpu-idle-states = <&CPU_SPC>;
46
+
cpu-idle-states = <&cpu_spc>;
47
47
};
48
48
49
-
CPU1: cpu@1 {
49
+
cpu1: cpu@1 {
50
50
compatible = "qcom,krait";
51
51
enable-method = "qcom,kpss-acc-v2";
52
52
device_type = "cpu";
53
53
reg = <1>;
54
-
next-level-cache = <&L2>;
54
+
next-level-cache = <&l2>;
55
55
qcom,acc = <&acc1>;
56
56
qcom,saw = <&saw1>;
57
-
cpu-idle-states = <&CPU_SPC>;
57
+
cpu-idle-states = <&cpu_spc>;
58
58
};
59
59
60
-
CPU2: cpu@2 {
60
+
cpu2: cpu@2 {
61
61
compatible = "qcom,krait";
62
62
enable-method = "qcom,kpss-acc-v2";
63
63
device_type = "cpu";
64
64
reg = <2>;
65
-
next-level-cache = <&L2>;
65
+
next-level-cache = <&l2>;
66
66
qcom,acc = <&acc2>;
67
67
qcom,saw = <&saw2>;
68
-
cpu-idle-states = <&CPU_SPC>;
68
+
cpu-idle-states = <&cpu_spc>;
69
69
};
70
70
71
-
CPU3: cpu@3 {
71
+
cpu3: cpu@3 {
72
72
compatible = "qcom,krait";
73
73
enable-method = "qcom,kpss-acc-v2";
74
74
device_type = "cpu";
75
75
reg = <3>;
76
-
next-level-cache = <&L2>;
76
+
next-level-cache = <&l2>;
77
77
qcom,acc = <&acc3>;
78
78
qcom,saw = <&saw3>;
79
-
cpu-idle-states = <&CPU_SPC>;
79
+
cpu-idle-states = <&cpu_spc>;
80
80
};
81
81
82
-
L2: l2-cache {
82
+
l2: l2-cache {
83
83
compatible = "cache";
84
84
cache-level = <2>;
85
85
cache-unified;
···
87
87
};
88
88
89
89
idle-states {
90
-
CPU_SPC: cpu-spc {
90
+
cpu_spc: cpu-spc {
91
91
compatible = "qcom,idle-state-spc",
92
92
"arm,idle-state";
93
93
entry-latency-us = <150>;
···
960
960
clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
961
961
clock-names = "apb_pclk", "atclk";
962
962
963
-
cpu = <&CPU0>;
963
+
cpu = <&cpu0>;
964
964
965
965
out-ports {
966
966
port {
···
978
978
clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
979
979
clock-names = "apb_pclk", "atclk";
980
980
981
-
cpu = <&CPU1>;
981
+
cpu = <&cpu1>;
982
982
983
983
out-ports {
984
984
port {
···
996
996
clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
997
997
clock-names = "apb_pclk", "atclk";
998
998
999
-
cpu = <&CPU2>;
999
+
cpu = <&cpu2>;
1000
1000
1001
1001
out-ports {
1002
1002
port {
···
1014
1014
clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1015
1015
clock-names = "apb_pclk", "atclk";
1016
1016
1017
-
cpu = <&CPU3>;
1017
+
cpu = <&cpu3>;
1018
1018
1019
1019
out-ports {
1020
1020
port {
···
1299
1299
bits = <0 6>;
1300
1300
};
1301
1301
1302
-
tsens_s10_p1: s10_p1@d8 {
1302
+
tsens_s10_p1: s10-p1@d8 {
1303
1303
reg = <0xd8 0x2>;
1304
1304
bits = <6 6>;
1305
1305
};
···
1359
1359
bits = <4 6>;
1360
1360
};
1361
1361
1362
-
tsens_s10_p2: s10_p2@e2 {
1362
+
tsens_s10_p2: s10-p2@e2 {
1363
1363
reg = <0xe2 0x2>;
1364
1364
bits = <2 6>;
1365
1365
};
1366
1366
1367
-
tsens_s5_p2_backup: s5-p2_backup@e3 {
1367
+
tsens_s5_p2_backup: s5-p2-backup@e3 {
1368
1368
reg = <0xe3 0x2>;
1369
1369
bits = <0 6>;
1370
1370
};
1371
1371
1372
-
tsens_mode_backup: mode_backup@e3 {
1372
+
tsens_mode_backup: mode-backup@e3 {
1373
1373
reg = <0xe3 0x1>;
1374
1374
bits = <6 2>;
1375
1375
};
1376
1376
1377
-
tsens_s6_p2_backup: s6-p2_backup@e4 {
1377
+
tsens_s6_p2_backup: s6-p2-backup@e4 {
1378
1378
reg = <0xe4 0x1>;
1379
1379
bits = <0 6>;
1380
1380
};
1381
1381
1382
-
tsens_s7_p2_backup: s7-p2_backup@e4 {
1382
+
tsens_s7_p2_backup: s7-p2-backup@e4 {
1383
1383
reg = <0xe4 0x2>;
1384
1384
bits = <6 6>;
1385
1385
};
1386
1386
1387
-
tsens_s8_p2_backup: s8-p2_backup@e5 {
1387
+
tsens_s8_p2_backup: s8-p2-backup@e5 {
1388
1388
reg = <0xe5 0x2>;
1389
1389
bits = <4 6>;
1390
1390
};
1391
1391
1392
-
tsens_s9_p2_backup: s9-p2_backup@e6 {
1392
+
tsens_s9_p2_backup: s9-p2-backup@e6 {
1393
1393
reg = <0xe6 0x2>;
1394
1394
bits = <2 6>;
1395
1395
};
1396
1396
1397
-
tsens_s10_p2_backup: s10_p2_backup@e7 {
1397
+
tsens_s10_p2_backup: s10-p2-backup@e7 {
1398
1398
reg = <0xe7 0x1>;
1399
1399
bits = <0 6>;
1400
1400
};
1401
1401
1402
-
tsens_base1_backup: base1_backup@440 {
1402
+
tsens_base1_backup: base1-backup@440 {
1403
1403
reg = <0x440 0x1>;
1404
1404
bits = <0 8>;
1405
1405
};
1406
1406
1407
-
tsens_s0_p1_backup: s0-p1_backup@441 {
1407
+
tsens_s0_p1_backup: s0-p1-backup@441 {
1408
1408
reg = <0x441 0x1>;
1409
1409
bits = <0 6>;
1410
1410
};
1411
1411
1412
-
tsens_s1_p1_backup: s1-p1_backup@442 {
1412
+
tsens_s1_p1_backup: s1-p1-backup@442 {
1413
1413
reg = <0x441 0x2>;
1414
1414
bits = <6 6>;
1415
1415
};
1416
1416
1417
-
tsens_s2_p1_backup: s2-p1_backup@442 {
1417
+
tsens_s2_p1_backup: s2-p1-backup@442 {
1418
1418
reg = <0x442 0x2>;
1419
1419
bits = <4 6>;
1420
1420
};
1421
1421
1422
-
tsens_s3_p1_backup: s3-p1_backup@443 {
1422
+
tsens_s3_p1_backup: s3-p1-backup@443 {
1423
1423
reg = <0x443 0x1>;
1424
1424
bits = <2 6>;
1425
1425
};
1426
1426
1427
-
tsens_s4_p1_backup: s4-p1_backup@444 {
1427
+
tsens_s4_p1_backup: s4-p1-backup@444 {
1428
1428
reg = <0x444 0x1>;
1429
1429
bits = <0 6>;
1430
1430
};
1431
1431
1432
-
tsens_s5_p1_backup: s5-p1_backup@444 {
1432
+
tsens_s5_p1_backup: s5-p1-backup@444 {
1433
1433
reg = <0x444 0x2>;
1434
1434
bits = <6 6>;
1435
1435
};
1436
1436
1437
-
tsens_s6_p1_backup: s6-p1_backup@445 {
1437
+
tsens_s6_p1_backup: s6-p1-backup@445 {
1438
1438
reg = <0x445 0x2>;
1439
1439
bits = <4 6>;
1440
1440
};
1441
1441
1442
-
tsens_s7_p1_backup: s7-p1_backup@446 {
1442
+
tsens_s7_p1_backup: s7-p1-backup@446 {
1443
1443
reg = <0x446 0x1>;
1444
1444
bits = <2 6>;
1445
1445
};
1446
1446
1447
-
tsens_use_backup: use_backup@447 {
1447
+
tsens_use_backup: use-backup@447 {
1448
1448
reg = <0x447 0x1>;
1449
1449
bits = <5 3>;
1450
1450
};
1451
1451
1452
-
tsens_s8_p1_backup: s8-p1_backup@448 {
1452
+
tsens_s8_p1_backup: s8-p1-backup@448 {
1453
1453
reg = <0x448 0x1>;
1454
1454
bits = <0 6>;
1455
1455
};
1456
1456
1457
-
tsens_s9_p1_backup: s9-p1_backup@448 {
1457
+
tsens_s9_p1_backup: s9-p1-backup@448 {
1458
1458
reg = <0x448 0x2>;
1459
1459
bits = <6 6>;
1460
1460
};
1461
1461
1462
-
tsens_s10_p1_backup: s10_p1_backup@449 {
1462
+
tsens_s10_p1_backup: s10-p1-backup@449 {
1463
1463
reg = <0x449 0x2>;
1464
1464
bits = <4 6>;
1465
1465
};
1466
1466
1467
-
tsens_base2_backup: base2_backup@44a {
1467
+
tsens_base2_backup: base2-backup@44a {
1468
1468
reg = <0x44a 0x2>;
1469
1469
bits = <2 8>;
1470
1470
};
1471
1471
1472
-
tsens_s0_p2_backup: s0-p2_backup@44b {
1472
+
tsens_s0_p2_backup: s0-p2-backup@44b {
1473
1473
reg = <0x44b 0x3>;
1474
1474
bits = <2 6>;
1475
1475
};
1476
1476
1477
-
tsens_s1_p2_backup: s1-p2_backup@44c {
1477
+
tsens_s1_p2_backup: s1-p2-backup@44c {
1478
1478
reg = <0x44c 0x1>;
1479
1479
bits = <0 6>;
1480
1480
};
1481
1481
1482
-
tsens_s2_p2_backup: s2-p2_backup@44c {
1482
+
tsens_s2_p2_backup: s2-p2-backup@44c {
1483
1483
reg = <0x44c 0x2>;
1484
1484
bits = <6 6>;
1485
1485
};
1486
1486
1487
-
tsens_s3_p2_backup: s3-p2_backup@44d {
1487
+
tsens_s3_p2_backup: s3-p2-backup@44d {
1488
1488
reg = <0x44d 0x2>;
1489
1489
bits = <4 6>;
1490
1490
};
1491
1491
1492
-
tsens_s4_p2_backup: s4-p2_backup@44e {
1492
+
tsens_s4_p2_backup: s4-p2-backup@44e {
1493
1493
reg = <0x44e 0x1>;
1494
1494
bits = <2 6>;
1495
1495
};
+1
arch/arm/boot/dts/qcom/qcom-sdx55.dtsi
+1
arch/arm/boot/dts/qcom/qcom-sdx55.dtsi
+34
-33
arch/arm/boot/dts/qcom/qcom-sdx65.dtsi
+34
-33
arch/arm/boot/dts/qcom/qcom-sdx65.dtsi
···
345
345
346
346
max-link-speed = <3>;
347
347
num-lanes = <2>;
348
+
linux,pci-domain = <0>;
348
349
349
350
status = "disabled";
350
351
};
···
593
592
reg = <0x15000000 0x40000>;
594
593
#iommu-cells = <2>;
595
594
#global-interrupts = <1>;
596
-
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
597
-
<GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
598
-
<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
599
-
<GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
600
-
<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
601
-
<GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
602
-
<GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
603
-
<GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
604
-
<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
605
-
<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
606
-
<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
607
-
<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
608
-
<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
609
-
<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
610
-
<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
611
-
<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
612
-
<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
613
-
<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
614
-
<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
615
-
<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
616
-
<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
617
-
<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
618
-
<GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
619
-
<GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>,
620
-
<GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>,
621
-
<GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>,
622
-
<GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
623
-
<GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
624
-
<GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
625
-
<GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
626
-
<GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,
627
-
<GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
628
-
<GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
595
+
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
596
+
<GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
597
+
<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
598
+
<GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
599
+
<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
600
+
<GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
601
+
<GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
602
+
<GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
603
+
<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
604
+
<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
605
+
<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
606
+
<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
607
+
<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
608
+
<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
609
+
<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
610
+
<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
611
+
<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
612
+
<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
613
+
<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
614
+
<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
615
+
<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
616
+
<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
617
+
<GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
618
+
<GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>,
619
+
<GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>,
620
+
<GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>,
621
+
<GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
622
+
<GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
623
+
<GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
624
+
<GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
625
+
<GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,
626
+
<GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
627
+
<GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
629
628
};
630
629
631
630
intc: interrupt-controller@17800000 {