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clk: renesas: r9a09g057: Add reset entry for SYS

Add the missing reset entry for the `SYS` module in the clock driver. The
corresponding core clock entry for `SYS` is already present.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250102181839.352599-6-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

authored by

Lad Prabhakar and committed by
Geert Uytterhoeven 7e3557b4 7088d2d7

+1
+1
drivers/clk/renesas/r9a09g057-cpg.c
··· 220 220 }; 221 221 222 222 static const struct rzv2h_reset r9a09g057_resets[] __initconst = { 223 + DEF_RST(3, 0, 1, 1), /* SYS_0_PRESETN */ 223 224 DEF_RST(3, 6, 1, 7), /* ICU_0_PRESETN_I */ 224 225 DEF_RST(6, 13, 2, 30), /* GTM_0_PRESETZ */ 225 226 DEF_RST(6, 14, 2, 31), /* GTM_1_PRESETZ */