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drm/msm/a8xx: Fix ubwc config related to swizzling

To disable l2/l3 swizzling in A8x, set the respective bits in both
GRAS_NC_MODE_CNTL and RB_CCU_NC_MODE_CNTL registers. This is required
for Glymur where it is recommended to keep l2/l3 swizzling disabled.

Fixes: 288a93200892 ("drm/msm/adreno: Introduce A8x GPU Support")
Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Message-ID: <20260305-a8xx-ubwc-fix-v1-1-d99b6da4c5a9@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>

authored by

Akhil P Oommen and committed by
Rob Clark 7e459c41 e4eb6e4d

+12 -2
+12 -2
drivers/gpu/drm/msm/adreno/a8xx_gpu.c
··· 310 310 hbb = cfg->highest_bank_bit - 13; 311 311 hbb_hi = hbb >> 2; 312 312 hbb_lo = hbb & 3; 313 - a8xx_write_pipe(gpu, PIPE_BV, REG_A8XX_GRAS_NC_MODE_CNTL, hbb << 5); 314 - a8xx_write_pipe(gpu, PIPE_BR, REG_A8XX_GRAS_NC_MODE_CNTL, hbb << 5); 313 + 314 + a8xx_write_pipe(gpu, PIPE_BV, REG_A8XX_GRAS_NC_MODE_CNTL, 315 + hbb << 5 | 316 + level3_swizzling_dis << 4 | 317 + level2_swizzling_dis << 3); 318 + 319 + a8xx_write_pipe(gpu, PIPE_BR, REG_A8XX_GRAS_NC_MODE_CNTL, 320 + hbb << 5 | 321 + level3_swizzling_dis << 4 | 322 + level2_swizzling_dis << 3); 315 323 316 324 a8xx_write_pipe(gpu, PIPE_BR, REG_A8XX_RB_CCU_NC_MODE_CNTL, 317 325 yuvnotcomptofc << 6 | 326 + level3_swizzling_dis << 5 | 327 + level2_swizzling_dis << 4 | 318 328 hbb_hi << 3 | 319 329 hbb_lo << 1); 320 330